[people/ms/linux.git] / drivers / ata / pata_hpt3x3.c

/*
 *	pata_hpt3x3		-	HPT3x3 driver
 *	(c) Copyright 2005-2006 Red Hat
 *
 *	Was pata_hpt34x but the naming was confusing as it supported the
 *	343 and 363 so it has been renamed.
 *
 *	Based on:
 *	linux/drivers/ide/pci/hpt34x.c		Version 0.40	Sept 10, 2002
 *	Copyright (C) 1998-2000	Andre Hedrick <andre@linux-ide.org>
 *
 *	May be copied or modified under the terms of the GNU General Public
 *	License
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt3x3"
#define DRV_VERSION	"0.5.3"

/**
 *	hpt3x3_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Set our PIO requirements. This is fairly simple on the HPT3x3 as
 *	all we have to do is clear the MWDMA and UDMA bits then load the
 *	mode number.
 */

static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 r1, r2;
	int dn = 2 * ap->port_no + adev->devno;

	pci_read_config_dword(pdev, 0x44, &r1);
	pci_read_config_dword(pdev, 0x48, &r2);
	/* Load the PIO timing number */
	r1 &= ~(7 << (3 * dn));
	r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
	r2 &= ~(0x11 << dn);	/* Clear MWDMA and UDMA bits */

	pci_write_config_dword(pdev, 0x44, r1);
	pci_write_config_dword(pdev, 0x48, r2);
}

#if defined(CONFIG_PATA_HPT3X3_DMA)
/**
 *	hpt3x3_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 *
 *	0x44 : bit 0-2 master mode, 3-5 slave mode, etc
 *	0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
 */

static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 r1, r2;
	int dn = 2 * ap->port_no + adev->devno;
	int mode_num = adev->dma_mode & 0x0F;

	pci_read_config_dword(pdev, 0x44, &r1);
	pci_read_config_dword(pdev, 0x48, &r2);
	/* Load the timing number */
	r1 &= ~(7 << (3 * dn));
	r1 |= (mode_num << (3 * dn));
	r2 &= ~(0x11 << dn);	/* Clear MWDMA and UDMA bits */

	if (adev->dma_mode >= XFER_UDMA_0)
		r2 |= (0x10 << dn);	/* Ultra mode */
	else
		r2 |= (0x01 << dn);	/* MWDMA */

	pci_write_config_dword(pdev, 0x44, r1);
	pci_write_config_dword(pdev, 0x48, r2);
}
#endif /* CONFIG_PATA_HPT3X3_DMA */

/**
 *	hpt3x3_atapi_dma	-	ATAPI DMA check
 *	@qc: Queued command
 *
 *	Just say no - we don't do ATAPI DMA
 */

static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
{
	return 1;
}

static struct scsi_host_template hpt3x3_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations hpt3x3_port_ops = {
	.set_piomode	= hpt3x3_set_piomode,
#if defined(CONFIG_PATA_HPT3X3_DMA)
	.set_dmamode	= hpt3x3_set_dmamode,
#endif
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,
	.check_atapi_dma= hpt3x3_atapi_dma,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,

	.port_start	= ata_sff_port_start,
};

/**
 *	hpt3x3_init_chipset	-	chip setup
 *	@dev: PCI device
 *
 *	Perform the setup required at boot and on resume.
 */

static void hpt3x3_init_chipset(struct pci_dev *dev)
{
	u16 cmd;
	/* Initialize the board */
	pci_write_config_word(dev, 0x80, 0x00);
	/* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (cmd & PCI_COMMAND_MEMORY)
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
	else
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
}

/**
 *	hpt3x3_init_one		-	Initialise an HPT343/363
 *	@pdev: PCI device
 *	@id: Entry in match table
 *
 *	Perform basic initialisation. We set the device up so we access all
 *	ports via BAR4. This is neccessary to work around errata.
 */

static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static int printed_version;
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
#if defined(CONFIG_PATA_HPT3X3_DMA)
		/* Further debug needed */
		.mwdma_mask = 0x07,
		.udma_mask = 0x07,
#endif
		.port_ops = &hpt3x3_port_ops
	};
	/* Register offsets of taskfiles in BAR4 area */
	static const u8 offset_cmd[2] = { 0x20, 0x28 };
	static const u8 offset_ctl[2] = { 0x36, 0x3E };
	const struct ata_port_info *ppi[] = { &info, NULL };
	struct ata_host *host;
	int i, rc;
	void __iomem *base;

	hpt3x3_init_chipset(pdev);

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	if (!host)
		return -ENOMEM;
	/* acquire resources and fill host */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* Everything is relative to BAR4 if we set up this way */
	rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;

	base = host->iomap[4];	/* Bus mastering base */

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		struct ata_ioports *ioaddr = &ap->ioaddr;

		ioaddr->cmd_addr = base + offset_cmd[i];
		ioaddr->altstatus_addr =
		ioaddr->ctl_addr = base + offset_ctl[i];
		ioaddr->scr_addr = NULL;
		ata_std_ports(ioaddr);
		ioaddr->bmdma_addr = base + 8 * i;

		ata_port_pbar_desc(ap, 4, -1, "ioport");
		ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
	}
	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
				 &hpt3x3_sht);
}

#ifdef CONFIG_PM
static int hpt3x3_reinit_one(struct pci_dev *dev)
{
	hpt3x3_init_chipset(dev);
	return ata_pci_device_resume(dev);
}
#endif

static const struct pci_device_id hpt3x3[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },

	{ },
};

static struct pci_driver hpt3x3_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= hpt3x3,
	.probe 		= hpt3x3_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= hpt3x3_reinit_one,
#endif
};

static int __init hpt3x3_init(void)
{
	return pci_register_driver(&hpt3x3_pci_driver);
}


static void __exit hpt3x3_exit(void)
{
	pci_unregister_driver(&hpt3x3_pci_driver);
}


MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt3x3);
MODULE_VERSION(DRV_VERSION);

module_init(hpt3x3_init);
module_exit(hpt3x3_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_hpt3x3 - HPT3x3 driver
	3	* (c) Copyright 2005-2006 Red Hat
	4	*
	5	* Was pata_hpt34x but the naming was confusing as it supported the
	6	* 343 and 363 so it has been renamed.
	7	*
	8	* Based on:
	9	* linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
	10	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	11	*
	12	* May be copied or modified under the terms of the GNU General Public
	13	* License
	14	*/
85cd7251	15
669a5db4 JG	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/pci.h>
	19	#include <linux/init.h>
	20	#include <linux/blkdev.h>
	21	#include <linux/delay.h>
	22	#include <scsi/scsi_host.h>
	23	#include <linux/libata.h>
	24
	25	#define DRV_NAME "pata_hpt3x3"
66e7da4e	26	#define DRV_VERSION "0.5.3"
669a5db4	27
669a5db4 JG	28	/**
	29	* hpt3x3_set_piomode - PIO setup
	30	* @ap: ATA interface
	31	* @adev: device on the interface
	32	*
	33	* Set our PIO requirements. This is fairly simple on the HPT3x3 as
	34	* all we have to do is clear the MWDMA and UDMA bits then load the
	35	* mode number.
	36	*/
	37
	38	static void hpt3x3_set_piomode(struct ata_port ap, struct ata_device adev)
	39	{
	40	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	41	u32 r1, r2;
	42	int dn = 2 * ap->port_no + adev->devno;
	43
	44	pci_read_config_dword(pdev, 0x44, &r1);
	45	pci_read_config_dword(pdev, 0x48, &r2);
	46	/* Load the PIO timing number */
	47	r1 &= ~(7 << (3 * dn));
	48	r1 \|= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
	49	r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
	50
	51	pci_write_config_dword(pdev, 0x44, r1);
	52	pci_write_config_dword(pdev, 0x48, r2);
	53	}
	54
790956e7	55	#if defined(CONFIG_PATA_HPT3X3_DMA)
669a5db4 JG	56	/**
	57	* hpt3x3_set_dmamode - DMA timing setup
	58	* @ap: ATA interface
	59	* @adev: Device being configured
	60	*
	61	* Set up the channel for MWDMA or UDMA modes. Much the same as with
	62	* PIO, load the mode number and then set MWDMA or UDMA flag.
66e7da4e AC	63	*
	64	* 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
	65	* 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
669a5db4 JG	66	*/
	67
	68	static void hpt3x3_set_dmamode(struct ata_port ap, struct ata_device adev)
	69	{
	70	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	71	u32 r1, r2;
	72	int dn = 2 * ap->port_no + adev->devno;
	73	int mode_num = adev->dma_mode & 0x0F;
	74
	75	pci_read_config_dword(pdev, 0x44, &r1);
	76	pci_read_config_dword(pdev, 0x48, &r2);
	77	/* Load the timing number */
	78	r1 &= ~(7 << (3 * dn));
	79	r1 \|= (mode_num << (3 * dn));
	80	r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
	81
	82	if (adev->dma_mode >= XFER_UDMA_0)
66e7da4e	83	r2 \|= (0x10 << dn); /* Ultra mode */
669a5db4	84	else
66e7da4e	85	r2 \|= (0x01 << dn); /* MWDMA */
669a5db4 JG	86
	87	pci_write_config_dword(pdev, 0x44, r1);
	88	pci_write_config_dword(pdev, 0x48, r2);
	89	}
790956e7	90	#endif /* CONFIG_PATA_HPT3X3_DMA */
669a5db4	91
66e7da4e AC	92	/**
	93	* hpt3x3_atapi_dma - ATAPI DMA check
	94	* @qc: Queued command
	95	*
	96	* Just say no - we don't do ATAPI DMA
	97	*/
	98
	99	static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
	100	{
	101	return 1;
	102	}
	103
669a5db4	104	static struct scsi_host_template hpt3x3_sht = {
68d1d07b	105	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	106	};
	107
	108	static struct ata_port_operations hpt3x3_port_ops = {
669a5db4	109	.set_piomode = hpt3x3_set_piomode,
790956e7 JG	110	#if defined(CONFIG_PATA_HPT3X3_DMA)
	111	.set_dmamode = hpt3x3_set_dmamode,
	112	#endif
669a5db4 JG	113	.mode_filter = ata_pci_default_filter,
	114
	115	.tf_load = ata_tf_load,
	116	.tf_read = ata_tf_read,
	117	.check_status = ata_check_status,
	118	.exec_command = ata_exec_command,
	119	.dev_select = ata_std_dev_select,
	120
	121	.freeze = ata_bmdma_freeze,
	122	.thaw = ata_bmdma_thaw,
a73984a0	123	.error_handler = ata_bmdma_error_handler,
669a5db4	124	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	125	.cable_detect = ata_cable_40wire,
669a5db4 JG	126
	127	.bmdma_setup = ata_bmdma_setup,
	128	.bmdma_start = ata_bmdma_start,
	129	.bmdma_stop = ata_bmdma_stop,
	130	.bmdma_status = ata_bmdma_status,
66e7da4e	131	.check_atapi_dma= hpt3x3_atapi_dma,
669a5db4 JG	132
	133	.qc_prep = ata_qc_prep,
	134	.qc_issue = ata_qc_issue_prot,
bda30288	135
0d5ff566	136	.data_xfer = ata_data_xfer,
669a5db4 JG	137
	138	.irq_handler = ata_interrupt,
	139	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	140	.irq_on = ata_irq_on,
669a5db4	141
81ad1837	142	.port_start = ata_sff_port_start,
669a5db4 JG	143	};
669a5db4 JG	144
aff0df05 AC	145	/**
	146	* hpt3x3_init_chipset - chip setup
	147	* @dev: PCI device
	148	*
	149	* Perform the setup required at boot and on resume.
	150	*/
f20b16ff	151
aff0df05 AC	152	static void hpt3x3_init_chipset(struct pci_dev *dev)
	153	{
	154	u16 cmd;
	155	/* Initialize the board */
	156	pci_write_config_word(dev, 0x80, 0x00);
	157	/* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
	158	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	159	if (cmd & PCI_COMMAND_MEMORY)
	160	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
	161	else
	162	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
	163	}
	164
669a5db4 JG	165	/**
669a5db4 JG	166	* hpt3x3_init_one - Initialise an HPT343/363
66e7da4e	167	* @pdev: PCI device
669a5db4 JG	168	* @id: Entry in match table
669a5db4 JG	169	*
66e7da4e AC	170	* Perform basic initialisation. We set the device up so we access all
66e7da4e AC	171	* ports via BAR4. This is neccessary to work around errata.
669a5db4 JG	172	*/
669a5db4 JG	173
66e7da4e	174	static int hpt3x3_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4	175	{
66e7da4e	176	static int printed_version;
1626aeb8	177	static const struct ata_port_info info = {
1d2808fd	178	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4	179	.pio_mask = 0x1f,
66e7da4e AC	180	#if defined(CONFIG_PATA_HPT3X3_DMA)
66e7da4e AC	181	/* Further debug needed */
669a5db4 JG	182	.mwdma_mask = 0x07,
669a5db4 JG	183	.udma_mask = 0x07,
66e7da4e	184	#endif
669a5db4 JG	185	.port_ops = &hpt3x3_port_ops
669a5db4 JG	186	};
66e7da4e AC	187	/* Register offsets of taskfiles in BAR4 area */
	188	static const u8 offset_cmd[2] = { 0x20, 0x28 };
	189	static const u8 offset_ctl[2] = { 0x36, 0x3E };
1626aeb8	190	const struct ata_port_info *ppi[] = { &info, NULL };
66e7da4e AC	191	struct ata_host *host;
	192	int i, rc;
	193	void __iomem *base;
	194
	195	hpt3x3_init_chipset(pdev);
	196
	197	if (!printed_version++)
	198	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	199
	200	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	201	if (!host)
	202	return -ENOMEM;
	203	/* acquire resources and fill host */
	204	rc = pcim_enable_device(pdev);
	205	if (rc)
	206	return rc;
	207
	208	/* Everything is relative to BAR4 if we set up this way */
	209	rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
	210	if (rc == -EBUSY)
	211	pcim_pin_device(pdev);
	212	if (rc)
	213	return rc;
	214	host->iomap = pcim_iomap_table(pdev);
	215	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	216	if (rc)
	217	return rc;
	218	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	219	if (rc)
	220	return rc;
	221
	222	base = host->iomap[4]; /* Bus mastering base */
	223
	224	for (i = 0; i < host->n_ports; i++) {
cbcdd875 TH	225	struct ata_port *ap = host->ports[i];
cbcdd875 TH	226	struct ata_ioports *ioaddr = &ap->ioaddr;
66e7da4e AC	227
	228	ioaddr->cmd_addr = base + offset_cmd[i];
	229	ioaddr->altstatus_addr =
	230	ioaddr->ctl_addr = base + offset_ctl[i];
	231	ioaddr->scr_addr = NULL;
	232	ata_std_ports(ioaddr);
	233	ioaddr->bmdma_addr = base + 8 * i;
cbcdd875 TH	234
	235	ata_port_pbar_desc(ap, 4, -1, "ioport");
	236	ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
66e7da4e AC	237	}
	238	pci_set_master(pdev);
	239	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
	240	&hpt3x3_sht);
669a5db4 JG	241	}
669a5db4 JG	242
438ac6d5	243	#ifdef CONFIG_PM
aff0df05 AC	244	static int hpt3x3_reinit_one(struct pci_dev *dev)
	245	{
	246	hpt3x3_init_chipset(dev);
	247	return ata_pci_device_resume(dev);
	248	}
438ac6d5	249	#endif
aff0df05	250
2d2744fc JG	251	static const struct pci_device_id hpt3x3[] = {
	252	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
	253
	254	{ },
669a5db4 JG	255	};
	256
	257	static struct pci_driver hpt3x3_pci_driver = {
2d2744fc	258	.name = DRV_NAME,
669a5db4 JG	259	.id_table = hpt3x3,
669a5db4 JG	260	.probe = hpt3x3_init_one,
aff0df05	261	.remove = ata_pci_remove_one,
438ac6d5	262	#ifdef CONFIG_PM
aff0df05 AC	263	.suspend = ata_pci_device_suspend,
aff0df05 AC	264	.resume = hpt3x3_reinit_one,
438ac6d5	265	#endif
669a5db4 JG	266	};
	267
	268	static int __init hpt3x3_init(void)
	269	{
	270	return pci_register_driver(&hpt3x3_pci_driver);
	271	}
	272
	273
	274	static void __exit hpt3x3_exit(void)
	275	{
	276	pci_unregister_driver(&hpt3x3_pci_driver);
	277	}
	278
	279
	280	MODULE_AUTHOR("Alan Cox");
	281	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
	282	MODULE_LICENSE("GPL");
	283	MODULE_DEVICE_TABLE(pci, hpt3x3);
	284	MODULE_VERSION(DRV_VERSION);
	285
	286	module_init(hpt3x3_init);
	287	module_exit(hpt3x3_exit);