[people/ms/linux.git] / drivers / ata / pata_ninja32.c

/*
 * pata_ninja32.c 	- Ninja32 PATA for new ATA layer
 *			  (C) 2007 Red Hat Inc
 *
 * Note: The controller like many controllers has shared timings for
 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
 * in the dma_stop function. Thus we actually don't need a set_dmamode
 * method as the PIO method is always called and will set the right PIO
 * timing parameters.
 *
 * The Ninja32 Cardbus is not a generic SFF controller. Instead it is
 * laid out as follows off BAR 0. This is based upon Mark Lord's delkin
 * driver and the extensive analysis done by the BSD developers, notably
 * ITOH Yasufumi.
 *
 *	Base + 0x00 IRQ Status
 *	Base + 0x01 IRQ control
 *	Base + 0x02 Chipset control
 *	Base + 0x03 Unknown
 *	Base + 0x04 VDMA and reset control + wait bits
 *	Base + 0x08 BMIMBA
 *	Base + 0x0C DMA Length
 *	Base + 0x10 Taskfile
 *	Base + 0x18 BMDMA Status ?
 *	Base + 0x1C
 *	Base + 0x1D Bus master control
 *		bit 0 = enable
 *		bit 1 = 0 write/1 read
 *		bit 2 = 1 sgtable
 *		bit 3 = go
 *		bit 4-6 wait bits
 *		bit 7 = done
 *	Base + 0x1E AltStatus
 *	Base + 0x1F timing register
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_ninja32"
#define DRV_VERSION "0.1.5"


/**
 *	ninja32_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	but we want to set the PIO timing by default.
 */

static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static u16 pio_timing[5] = {
		0xd6, 0x85, 0x44, 0x33, 0x13
	};
	iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
		 ap->ioaddr.bmdma_addr + 0x1f);
	ap->private_data = adev;
}


static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
{
	struct ata_device *adev = &ap->link.device[device];
	if (ap->private_data != adev) {
		iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
		ata_sff_dev_select(ap, device);
		ninja32_set_piomode(ap, adev);
	}
}

static struct scsi_host_template ninja32_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations ninja32_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.sff_dev_select = ninja32_dev_select,
	.cable_detect	= ata_cable_40wire,
	.set_piomode	= ninja32_set_piomode,
	.sff_data_xfer	= ata_sff_data_xfer32
};

static void ninja32_program(void __iomem *base)
{
	iowrite8(0x05, base + 0x01);	/* Enable interrupt lines */
	iowrite8(0xBE, base + 0x02);	/* Burst, ?? setup */
	iowrite8(0x01, base + 0x03);	/* Unknown */
	iowrite8(0x20, base + 0x04);	/* WAIT0 */
	iowrite8(0x8f, base + 0x05);	/* Unknown */
	iowrite8(0xa4, base + 0x1c);	/* Unknown */
	iowrite8(0x83, base + 0x1d);	/* BMDMA control: WAIT0 */
}

static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ata_host *host;
	struct ata_port *ap;
	void __iomem *base;
	int rc;

	host = ata_host_alloc(&dev->dev, 1);
	if (!host)
		return -ENOMEM;
	ap = host->ports[0];

	/* Set up the PCI device */
	rc = pcim_enable_device(dev);
	if (rc)
		return rc;
	rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(dev);
	if (rc)
		return rc;

	host->iomap = pcim_iomap_table(dev);
	rc = dma_set_mask(&dev->dev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = dma_set_coherent_mask(&dev->dev, ATA_DMA_MASK);
	if (rc)
		return rc;
	pci_set_master(dev);

	/* Set up the register mappings. We use the I/O mapping as only the
	   older chips also have MMIO on BAR 1 */
	base = host->iomap[0];
	if (!base)
		return -ENOMEM;
	ap->ops = &ninja32_port_ops;
	ap->pio_mask = ATA_PIO4;
	ap->flags |= ATA_FLAG_SLAVE_POSS;

	ap->ioaddr.cmd_addr = base + 0x10;
	ap->ioaddr.ctl_addr = base + 0x1E;
	ap->ioaddr.altstatus_addr = base + 0x1E;
	ap->ioaddr.bmdma_addr = base;
	ata_sff_std_ports(&ap->ioaddr);
	ap->pflags = ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;

	ninja32_program(base);
	/* FIXME: Should we disable them at remove ? */
	return ata_host_activate(host, dev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &ninja32_sht);
}

#ifdef CONFIG_PM_SLEEP
static int ninja32_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = pci_get_drvdata(pdev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;
	ninja32_program(host->iomap[0]);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id ninja32[] = {
	{ 0x10FC, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ 0x1145, 0x8008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ 0x1145, 0xf008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ 0x1145, 0xf02C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ },
};

static struct pci_driver ninja32_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= ninja32,
	.probe 		= ninja32_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend	= ata_pci_device_suspend,
	.resume		= ninja32_reinit_one,
#endif
};

module_pci_driver(ninja32_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, ninja32);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
51dbd490 AC	1	/*
	2	* pata_ninja32.c - Ninja32 PATA for new ATA layer
	3	* (C) 2007 Red Hat Inc
51dbd490 AC	4	*
	5	* Note: The controller like many controllers has shared timings for
	6	* PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
	7	* in the dma_stop function. Thus we actually don't need a set_dmamode
	8	* method as the PIO method is always called and will set the right PIO
	9	* timing parameters.
	10	*
	11	* The Ninja32 Cardbus is not a generic SFF controller. Instead it is
	12	* laid out as follows off BAR 0. This is based upon Mark Lord's delkin
	13	* driver and the extensive analysis done by the BSD developers, notably
	14	* ITOH Yasufumi.
	15	*
	16	* Base + 0x00 IRQ Status
	17	* Base + 0x01 IRQ control
	18	* Base + 0x02 Chipset control
41946450	19	* Base + 0x03 Unknown
51dbd490 AC	20	* Base + 0x04 VDMA and reset control + wait bits
	21	* Base + 0x08 BMIMBA
	22	* Base + 0x0C DMA Length
	23	* Base + 0x10 Taskfile
	24	* Base + 0x18 BMDMA Status ?
	25	* Base + 0x1C
	26	* Base + 0x1D Bus master control
	27	* bit 0 = enable
	28	* bit 1 = 0 write/1 read
	29	* bit 2 = 1 sgtable
	30	* bit 3 = go
	31	* bit 4-6 wait bits
	32	* bit 7 = done
	33	* Base + 0x1E AltStatus
	34	* Base + 0x1F timing register
	35	*/
	36
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
51dbd490 AC	40	#include <linux/blkdev.h>
	41	#include <linux/delay.h>
	42	#include <scsi/scsi_host.h>
	43	#include <linux/libata.h>
	44
	45	#define DRV_NAME "pata_ninja32"
e3cf95dd	46	#define DRV_VERSION "0.1.5"
51dbd490 AC	47
	48
	49	/**
	50	* ninja32_set_piomode - set initial PIO mode data
	51	* @ap: ATA interface
	52	* @adev: ATA device
	53	*
	54	* Called to do the PIO mode setup. Our timing registers are shared
	55	* but we want to set the PIO timing by default.
	56	*/
	57
	58	static void ninja32_set_piomode(struct ata_port ap, struct ata_device adev)
	59	{
	60	static u16 pio_timing[5] = {
	61	0xd6, 0x85, 0x44, 0x33, 0x13
	62	};
11b7becc JG	63	iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
11b7becc JG	64	ap->ioaddr.bmdma_addr + 0x1f);
51dbd490 AC	65	ap->private_data = adev;
	66	}
	67
	68
	69	static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
	70	{
	71	struct ata_device *adev = &ap->link.device[device];
	72	if (ap->private_data != adev) {
	73	iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
9363c382	74	ata_sff_dev_select(ap, device);
51dbd490 AC	75	ninja32_set_piomode(ap, adev);
	76	}
	77	}
	78
	79	static struct scsi_host_template ninja32_sht = {
68d1d07b	80	ATA_BMDMA_SHT(DRV_NAME),
51dbd490 AC	81	};
	82
	83	static struct ata_port_operations ninja32_port_ops = {
029cfd6b	84	.inherits = &ata_bmdma_port_ops,
5682ed33	85	.sff_dev_select = ninja32_dev_select,
51dbd490	86	.cable_detect = ata_cable_40wire,
029cfd6b	87	.set_piomode = ninja32_set_piomode,
e3cf95dd	88	.sff_data_xfer = ata_sff_data_xfer32
51dbd490 AC	89	};
51dbd490 AC	90
e7c0d217 AC	91	static void ninja32_program(void __iomem *base)
	92	{
	93	iowrite8(0x05, base + 0x01); /* Enable interrupt lines */
	94	iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */
	95	iowrite8(0x01, base + 0x03); /* Unknown */
	96	iowrite8(0x20, base + 0x04); /* WAIT0 */
	97	iowrite8(0x8f, base + 0x05); /* Unknown */
	98	iowrite8(0xa4, base + 0x1c); /* Unknown */
	99	iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */
	100	}
	101
51dbd490 AC	102	static int ninja32_init_one(struct pci_dev dev, const struct pci_device_id id)
	103	{
	104	struct ata_host *host;
	105	struct ata_port *ap;
	106	void __iomem *base;
	107	int rc;
	108
	109	host = ata_host_alloc(&dev->dev, 1);
	110	if (!host)
	111	return -ENOMEM;
	112	ap = host->ports[0];
	113
	114	/* Set up the PCI device */
	115	rc = pcim_enable_device(dev);
	116	if (rc)
	117	return rc;
	118	rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
	119	if (rc == -EBUSY)
	120	pcim_pin_device(dev);
	121	if (rc)
	122	return rc;
	123
	124	host->iomap = pcim_iomap_table(dev);
c54c719b	125	rc = dma_set_mask(&dev->dev, ATA_DMA_MASK);
51dbd490 AC	126	if (rc)
51dbd490 AC	127	return rc;
c54c719b	128	rc = dma_set_coherent_mask(&dev->dev, ATA_DMA_MASK);
51dbd490 AC	129	if (rc)
	130	return rc;
	131	pci_set_master(dev);
	132
b604958a AC	133	/* Set up the register mappings. We use the I/O mapping as only the
b604958a AC	134	older chips also have MMIO on BAR 1 */
51dbd490 AC	135	base = host->iomap[0];
	136	if (!base)
	137	return -ENOMEM;
	138	ap->ops = &ninja32_port_ops;
14bdef98	139	ap->pio_mask = ATA_PIO4;
51dbd490 AC	140	ap->flags \|= ATA_FLAG_SLAVE_POSS;
	141
	142	ap->ioaddr.cmd_addr = base + 0x10;
	143	ap->ioaddr.ctl_addr = base + 0x1E;
	144	ap->ioaddr.altstatus_addr = base + 0x1E;
	145	ap->ioaddr.bmdma_addr = base;
9363c382	146	ata_sff_std_ports(&ap->ioaddr);
e3cf95dd	147	ap->pflags = ATA_PFLAG_PIO32 \| ATA_PFLAG_PIO32CHANGE;
51dbd490	148
e7c0d217	149	ninja32_program(base);
51dbd490	150	/* FIXME: Should we disable them at remove ? */
c3b28894	151	return ata_host_activate(host, dev->irq, ata_bmdma_interrupt,
11b7becc	152	IRQF_SHARED, &ninja32_sht);
51dbd490 AC	153	}
51dbd490 AC	154
58eb8cd5	155	#ifdef CONFIG_PM_SLEEP
e7c0d217 AC	156	static int ninja32_reinit_one(struct pci_dev *pdev)
e7c0d217 AC	157	{
0a86e1c8	158	struct ata_host *host = pci_get_drvdata(pdev);
e7c0d217 AC	159	int rc;
	160
	161	rc = ata_pci_device_do_resume(pdev);
	162	if (rc)
	163	return rc;
	164	ninja32_program(host->iomap[0]);
	165	ata_host_resume(host);
4fca377f	166	return 0;
e7c0d217 AC	167	}
	168	#endif
	169
51dbd490	170	static const struct pci_device_id ninja32[] = {
b604958a AC	171	{ 0x10FC, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	172	{ 0x1145, 0x8008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	173	{ 0x1145, 0xf008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
11b7becc JG	174	{ 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
11b7becc JG	175	{ 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
b604958a	176	{ 0x1145, 0xf02C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
51dbd490 AC	177	{ },
	178	};
	179
	180	static struct pci_driver ninja32_pci_driver = {
	181	.name = DRV_NAME,
	182	.id_table = ninja32,
	183	.probe = ninja32_init_one,
e7c0d217	184	.remove = ata_pci_remove_one,
58eb8cd5	185	#ifdef CONFIG_PM_SLEEP
e7c0d217 AC	186	.suspend = ata_pci_device_suspend,
	187	.resume = ninja32_reinit_one,
	188	#endif
51dbd490 AC	189	};
51dbd490 AC	190
2fc75da0	191	module_pci_driver(ninja32_pci_driver);
51dbd490 AC	192
	193	MODULE_AUTHOR("Alan Cox");
	194	MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
	195	MODULE_LICENSE("GPL");
	196	MODULE_DEVICE_TABLE(pci, ninja32);
	197	MODULE_VERSION(DRV_VERSION);