[thirdparty/u-boot.git] / drivers / ata / sata_ceva.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2015 - 2016 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 */
#include <common.h>
#include <dm.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/io.h>

/* Vendor Specific Register Offsets */
#define AHCI_VEND_PCFG  0xA4
#define AHCI_VEND_PPCFG 0xA8
#define AHCI_VEND_PP2C  0xAC
#define AHCI_VEND_PP3C  0xB0
#define AHCI_VEND_PP4C  0xB4
#define AHCI_VEND_PP5C  0xB8
#define AHCI_VEND_AXICC 0xBc
#define AHCI_VEND_PAXIC 0xC0
#define AHCI_VEND_PTC   0xC8

/* Vendor Specific Register bit definitions */
#define PAXIC_ADBW_BW64 0x1
#define PAXIC_MAWIDD	(1 << 8)
#define PAXIC_MARIDD	(1 << 16)
#define PAXIC_OTL	(0x4 << 20)

#define PCFG_TPSS_VAL	(0x32 << 16)
#define PCFG_TPRS_VAL	(0x2 << 12)
#define PCFG_PAD_VAL	0x2

#define PPCFG_TTA	0x1FFFE
#define PPCFG_PSSO_EN	(1 << 28)
#define PPCFG_PSS_EN	(1 << 29)
#define PPCFG_ESDF_EN	(1 << 31)

#define PP2C_CIBGMN	0x0F
#define PP2C_CIBGMX	(0x25 << 8)
#define PP2C_CIBGN	(0x18 << 16)
#define PP2C_CINMP	(0x29 << 24)

#define PP3C_CWBGMN	0x04
#define PP3C_CWBGMX	(0x0B << 8)
#define PP3C_CWBGN	(0x08 << 16)
#define PP3C_CWNMP	(0x0F << 24)

#define PP4C_BMX	0x0a
#define PP4C_BNM	(0x08 << 8)
#define PP4C_SFD	(0x4a << 16)
#define PP4C_PTST	(0x06 << 24)

#define PP5C_RIT	0x60216
#define PP5C_RCT	(0x7f0 << 20)

#define PTC_RX_WM_VAL	0x40
#define PTC_RSVD	(1 << 27)

#define PORT0_BASE	0x100
#define PORT1_BASE	0x180

/* Port Control Register Bit Definitions */
#define PORT_SCTL_SPD_GEN3	(0x3 << 4)
#define PORT_SCTL_SPD_GEN2	(0x2 << 4)
#define PORT_SCTL_SPD_GEN1	(0x1 << 4)
#define PORT_SCTL_IPM		(0x3 << 8)

#define PORT_BASE	0x100
#define PORT_OFFSET	0x80
#define NR_PORTS	2
#define DRV_NAME	"ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2	1

/* flag bit definition */
#define FLAG_COHERENT	1

/* register config value */
#define CEVA_PHY1_CFG	0xa003fffe
#define CEVA_PHY2_CFG	0x28184d1f
#define CEVA_PHY3_CFG	0x0e081509
#define CEVA_TRANS_CFG	0x08000029
#define CEVA_AXICC_CFG	0x3fffffff

/* for ls1021a */
#define LS1021_AHCI_VEND_AXICC 0xC0
#define LS1021_CEVA_PHY2_CFG	0x28183414
#define LS1021_CEVA_PHY3_CFG	0x0e080e06
#define LS1021_CEVA_PHY4_CFG	0x064a080b
#define LS1021_CEVA_PHY5_CFG	0x2aa86470

/* ecc addr-val pair */
#define ECC_DIS_ADDR_CH2	0x80000000
#define ECC_DIS_VAL_CH2		0x20140520
#define SATA_ECC_REG_ADDR	0x20220520
#define SATA_ECC_DISABLE	0x00020000

enum ceva_soc {
	CEVA_1V84,
	CEVA_LS1012A,
	CEVA_LS1021A,
	CEVA_LS1043A,
	CEVA_LS1046A,
};

struct ceva_sata_priv {
	ulong base;
	enum ceva_soc soc;
	ulong flag;
};

static int ceva_init_sata(struct ceva_sata_priv *priv)
{
	ulong base = priv->base;
	ulong tmp;

	switch (priv->soc) {
	case CEVA_1V84:
		tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
		writel(tmp, base + AHCI_VEND_PAXIC);
		tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
		writel(tmp, base + AHCI_VEND_PCFG);
		tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
		writel(tmp, base + AHCI_VEND_PPCFG);
		tmp = PTC_RX_WM_VAL | PTC_RSVD;
		writel(tmp, base + AHCI_VEND_PTC);
		break;

	case CEVA_LS1021A:
		writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR);
		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
		writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
		writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
		writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
		writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
		if (priv->flag & FLAG_COHERENT)
			writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC);
		break;

	case CEVA_LS1012A:
	case CEVA_LS1043A:
	case CEVA_LS1046A:
		writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
		if (priv->flag & FLAG_COHERENT)
			writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
		break;
	}

	return 0;
}

static int sata_ceva_bind(struct udevice *dev)
{
	struct udevice *scsi_dev;

	return ahci_bind_scsi(dev, &scsi_dev);
}

static int sata_ceva_probe(struct udevice *dev)
{
	struct ceva_sata_priv *priv = dev_get_priv(dev);

	ceva_init_sata(priv);

	return ahci_probe_scsi(dev, priv->base);
}

static const struct udevice_id sata_ceva_ids[] = {
	{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
	{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
	{ .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
	{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
	{ .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
	{ }
};

static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
{
	struct ceva_sata_priv *priv = dev_get_priv(dev);

	if (dev_read_bool(dev, "dma-coherent"))
		priv->flag |= FLAG_COHERENT;

	priv->base = dev_read_addr(dev);
	if (priv->base == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->soc = dev_get_driver_data(dev);

	return 0;
}

U_BOOT_DRIVER(ceva_host_blk) = {
	.name = "ceva_sata",
	.id = UCLASS_AHCI,
	.of_match = sata_ceva_ids,
	.bind = sata_ceva_bind,
	.ops = &scsi_ops,
	.priv_auto_alloc_size = sizeof(struct ceva_sata_priv),
	.probe = sata_ceva_probe,
	.ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
679b994a MS	2	/*
	3	* (C) Copyright 2015 - 2016 Xilinx, Inc.
	4	* Michal Simek <michal.simek@xilinx.com>
679b994a MS	5	*/
679b994a MS	6	#include <common.h>
49c4c78e	7	#include <dm.h>
679b994a MS	8	#include <ahci.h>
679b994a MS	9	#include <scsi.h>
679b994a MS	10	#include <asm/io.h>
	11
	12	/* Vendor Specific Register Offsets */
	13	#define AHCI_VEND_PCFG 0xA4
	14	#define AHCI_VEND_PPCFG 0xA8
	15	#define AHCI_VEND_PP2C 0xAC
	16	#define AHCI_VEND_PP3C 0xB0
	17	#define AHCI_VEND_PP4C 0xB4
	18	#define AHCI_VEND_PP5C 0xB8
79ed61e9	19	#define AHCI_VEND_AXICC 0xBc
679b994a MS	20	#define AHCI_VEND_PAXIC 0xC0
	21	#define AHCI_VEND_PTC 0xC8
	22
	23	/* Vendor Specific Register bit definitions */
	24	#define PAXIC_ADBW_BW64 0x1
	25	#define PAXIC_MAWIDD (1 << 8)
	26	#define PAXIC_MARIDD (1 << 16)
	27	#define PAXIC_OTL (0x4 << 20)
	28
	29	#define PCFG_TPSS_VAL (0x32 << 16)
	30	#define PCFG_TPRS_VAL (0x2 << 12)
	31	#define PCFG_PAD_VAL 0x2
	32
	33	#define PPCFG_TTA 0x1FFFE
	34	#define PPCFG_PSSO_EN (1 << 28)
	35	#define PPCFG_PSS_EN (1 << 29)
	36	#define PPCFG_ESDF_EN (1 << 31)
	37
	38	#define PP2C_CIBGMN 0x0F
	39	#define PP2C_CIBGMX (0x25 << 8)
	40	#define PP2C_CIBGN (0x18 << 16)
	41	#define PP2C_CINMP (0x29 << 24)
	42
	43	#define PP3C_CWBGMN 0x04
	44	#define PP3C_CWBGMX (0x0B << 8)
	45	#define PP3C_CWBGN (0x08 << 16)
	46	#define PP3C_CWNMP (0x0F << 24)
	47
	48	#define PP4C_BMX 0x0a
	49	#define PP4C_BNM (0x08 << 8)
	50	#define PP4C_SFD (0x4a << 16)
	51	#define PP4C_PTST (0x06 << 24)
	52
	53	#define PP5C_RIT 0x60216
	54	#define PP5C_RCT (0x7f0 << 20)
	55
	56	#define PTC_RX_WM_VAL 0x40
	57	#define PTC_RSVD (1 << 27)
	58
	59	#define PORT0_BASE 0x100
	60	#define PORT1_BASE 0x180
	61
	62	/* Port Control Register Bit Definitions */
	63	#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
	64	#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
	65	#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
	66	#define PORT_SCTL_IPM (0x3 << 8)
	67
	68	#define PORT_BASE 0x100
	69	#define PORT_OFFSET 0x80
	70	#define NR_PORTS 2
	71	#define DRV_NAME "ahci-ceva"
	72	#define CEVA_FLAG_BROKEN_GEN2 1
	73
79ed61e9 YT	74	/* flag bit definition */
	75	#define FLAG_COHERENT 1
	76
	77	/* register config value */
	78	#define CEVA_PHY1_CFG 0xa003fffe
	79	#define CEVA_PHY2_CFG 0x28184d1f
	80	#define CEVA_PHY3_CFG 0x0e081509
	81	#define CEVA_TRANS_CFG 0x08000029
	82	#define CEVA_AXICC_CFG 0x3fffffff
	83
df983a76 PM	84	/* for ls1021a */
	85	#define LS1021_AHCI_VEND_AXICC 0xC0
	86	#define LS1021_CEVA_PHY2_CFG 0x28183414
	87	#define LS1021_CEVA_PHY3_CFG 0x0e080e06
	88	#define LS1021_CEVA_PHY4_CFG 0x064a080b
	89	#define LS1021_CEVA_PHY5_CFG 0x2aa86470
	90
79ed61e9 YT	91	/* ecc addr-val pair */
79ed61e9 YT	92	#define ECC_DIS_ADDR_CH2 0x80000000
df983a76 PM	93	#define ECC_DIS_VAL_CH2 0x20140520
	94	#define SATA_ECC_REG_ADDR 0x20220520
	95	#define SATA_ECC_DISABLE 0x00020000
79ed61e9 YT	96
	97	enum ceva_soc {
	98	CEVA_1V84,
	99	CEVA_LS1012A,
df983a76	100	CEVA_LS1021A,
822d0608	101	CEVA_LS1043A,
5fcae597	102	CEVA_LS1046A,
79ed61e9 YT	103	};
79ed61e9 YT	104
c3898a88 MS	105	struct ceva_sata_priv {
c3898a88 MS	106	ulong base;
79ed61e9 YT	107	enum ceva_soc soc;
79ed61e9 YT	108	ulong flag;
c3898a88 MS	109	};
c3898a88 MS	110
79ed61e9	111	static int ceva_init_sata(struct ceva_sata_priv *priv)
679b994a	112	{
79ed61e9	113	ulong base = priv->base;
679b994a	114	ulong tmp;
679b994a	115
79ed61e9 YT	116	switch (priv->soc) {
	117	case CEVA_1V84:
	118	tmp = PAXIC_ADBW_BW64 \| PAXIC_MAWIDD \| PAXIC_MARIDD \| PAXIC_OTL;
	119	writel(tmp, base + AHCI_VEND_PAXIC);
	120	tmp = PCFG_TPSS_VAL \| PCFG_TPRS_VAL \| PCFG_PAD_VAL;
	121	writel(tmp, base + AHCI_VEND_PCFG);
	122	tmp = PPCFG_TTA \| PPCFG_PSS_EN \| PPCFG_ESDF_EN;
	123	writel(tmp, base + AHCI_VEND_PPCFG);
679b994a	124	tmp = PTC_RX_WM_VAL \| PTC_RSVD;
79ed61e9 YT	125	writel(tmp, base + AHCI_VEND_PTC);
	126	break;
	127
df983a76 PM	128	case CEVA_LS1021A:
	129	writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR);
	130	writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
	131	writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
	132	writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
	133	writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
	134	writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
	135	writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
	136	if (priv->flag & FLAG_COHERENT)
	137	writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC);
	138	break;
	139
79ed61e9	140	case CEVA_LS1012A:
822d0608	141	case CEVA_LS1043A:
5fcae597	142	case CEVA_LS1046A:
79ed61e9 YT	143	writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
	144	writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
	145	writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
	146	if (priv->flag & FLAG_COHERENT)
	147	writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
	148	break;
679b994a	149	}
79ed61e9	150
679b994a MS	151	return 0;
679b994a MS	152	}
49c4c78e	153
c3898a88	154	static int sata_ceva_bind(struct udevice *dev)
49c4c78e	155	{
c3898a88 MS	156	struct udevice *scsi_dev;
	157
	158	return ahci_bind_scsi(dev, &scsi_dev);
	159	}
49c4c78e	160
c3898a88 MS	161	static int sata_ceva_probe(struct udevice *dev)
	162	{
	163	struct ceva_sata_priv *priv = dev_get_priv(dev);
7cf1afce	164
79ed61e9	165	ceva_init_sata(priv);
cba64a2a	166
c3898a88	167	return ahci_probe_scsi(dev, priv->base);
49c4c78e MS	168	}
	169
	170	static const struct udevice_id sata_ceva_ids[] = {
79ed61e9 YT	171	{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
79ed61e9 YT	172	{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
df983a76	173	{ .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
822d0608	174	{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
5fcae597	175	{ .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
49c4c78e MS	176	{ }
	177	};
	178
	179	static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
	180	{
c3898a88	181	struct ceva_sata_priv *priv = dev_get_priv(dev);
49c4c78e	182
79ed61e9 YT	183	if (dev_read_bool(dev, "dma-coherent"))
	184	priv->flag \|= FLAG_COHERENT;
	185
	186	priv->base = dev_read_addr(dev);
c3898a88	187	if (priv->base == FDT_ADDR_T_NONE)
49c4c78e MS	188	return -EINVAL;
49c4c78e MS	189
79ed61e9 YT	190	priv->soc = dev_get_driver_data(dev);
79ed61e9 YT	191
49c4c78e MS	192	return 0;
	193	}
	194
	195	U_BOOT_DRIVER(ceva_host_blk) = {
	196	.name = "ceva_sata",
c3898a88	197	.id = UCLASS_AHCI,
49c4c78e	198	.of_match = sata_ceva_ids,
c3898a88	199	.bind = sata_ceva_bind,
f6ab5a92	200	.ops = &scsi_ops,
c3898a88	201	.priv_auto_alloc_size = sizeof(struct ceva_sata_priv),
49c4c78e MS	202	.probe = sata_ceva_probe,
49c4c78e MS	203	.ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
49c4c78e	204	};