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arm: sunxi: Enable DM_MMC and DM_SCSI
[thirdparty/u-boot.git] / drivers / ata / sata_mv.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
169789dc
TK		 2/*
3 * Copyright (C) Excito Elektronik i Skåne AB, 2010.
4 * Author: Tor Krill <tor@excito.com>
5 *
0506620f 6 * Copyright (C) 2015, 2019 Stefan Roese <sr@denx.de>
169789dc
TK		 7 */
8
9/*
10 * This driver supports the SATA controller of some Mavell SoC's.
11 * Here a (most likely incomplete) list of the supported SoC's:
12 * - Kirkwood
13 * - Armada 370
14 * - Armada XP
15 *
16 * This driver implementation is an alternative to the already available
17 * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
18 * But this driver only supports PIO mode and as this new driver also
19 * supports transfer via DMA, its much faster.
20 *
21 * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
22 * by this driver. As they have an AHCI compatible SATA controller
23 * integrated.
24 */
25
26/*
27 * TODO:
28 * Better error recovery
29 * No support for using PRDs (Thus max 64KB transfers)
30 * No NCQ support
31 * No port multiplier support
32 */
33
34#include <common.h>
0506620f
SR		 35#include <ahci.h>
36#include <dm.h>
37#include <dm/device-internal.h>
38#include <dm/lists.h>
169789dc
TK		 39#include <fis.h>
40#include <libata.h>
41#include <malloc.h>
42#include <sata.h>
1221ce45 43#include <linux/errno.h>
169789dc
TK		 44#include <asm/io.h>
45#include <linux/mbus.h>
46
6d294971 47#include <asm/arch/soc.h>
169789dc 48#if defined(CONFIG_KIRKWOOD)
169789dc
TK		 49#define SATAHC_BASE KW_SATA_BASE
50#else
169789dc
TK		 51#define SATAHC_BASE MVEBU_AXP_SATA_BASE
52#endif
53
54#define SATA0_BASE (SATAHC_BASE + 0x2000)
55#define SATA1_BASE (SATAHC_BASE + 0x4000)
56
57/* EDMA registers */
58#define EDMA_CFG 0x000
59#define EDMA_CFG_NCQ (1 << 5)
60#define EDMA_CFG_EQUE (1 << 9)
61#define EDMA_TIMER 0x004
62#define EDMA_IECR 0x008
63#define EDMA_IEMR 0x00c
64#define EDMA_RQBA_HI 0x010
65#define EDMA_RQIPR 0x014
66#define EDMA_RQIPR_IPMASK (0x1f << 5)
67#define EDMA_RQIPR_IPSHIFT 5
68#define EDMA_RQOPR 0x018
69#define EDMA_RQOPR_OPMASK (0x1f << 5)
70#define EDMA_RQOPR_OPSHIFT 5
71#define EDMA_RSBA_HI 0x01c
72#define EDMA_RSIPR 0x020
73#define EDMA_RSIPR_IPMASK (0x1f << 3)
74#define EDMA_RSIPR_IPSHIFT 3
75#define EDMA_RSOPR 0x024
76#define EDMA_RSOPR_OPMASK (0x1f << 3)
77#define EDMA_RSOPR_OPSHIFT 3
78#define EDMA_CMD 0x028
79#define EDMA_CMD_ENEDMA (0x01 << 0)
80#define EDMA_CMD_DISEDMA (0x01 << 1)
81#define EDMA_CMD_ATARST (0x01 << 2)
82#define EDMA_CMD_FREEZE (0x01 << 4)
83#define EDMA_TEST_CTL 0x02c
84#define EDMA_STATUS 0x030
85#define EDMA_IORTO 0x034
86#define EDMA_CDTR 0x040
87#define EDMA_HLTCND 0x060
88#define EDMA_NTSR 0x094
89
90/* Basic DMA registers */
91#define BDMA_CMD 0x224
92#define BDMA_STATUS 0x228
93#define BDMA_DTLB 0x22c
94#define BDMA_DTHB 0x230
95#define BDMA_DRL 0x234
96#define BDMA_DRH 0x238
97
98/* SATA Interface registers */
99#define SIR_ICFG 0x050
100#define SIR_CFG_GEN2EN (0x1 << 7)
101#define SIR_PLL_CFG 0x054
102#define SIR_SSTATUS 0x300
103#define SSTATUS_DET_MASK (0x0f << 0)
104#define SIR_SERROR 0x304
105#define SIR_SCONTROL 0x308
106#define SIR_SCONTROL_DETEN (0x01 << 0)
107#define SIR_LTMODE 0x30c
108#define SIR_LTMODE_NELBE (0x01 << 7)
109#define SIR_PHYMODE3 0x310
110#define SIR_PHYMODE4 0x314
111#define SIR_PHYMODE1 0x32c
112#define SIR_PHYMODE2 0x330
113#define SIR_BIST_CTRL 0x334
114#define SIR_BIST_DW1 0x338
115#define SIR_BIST_DW2 0x33c
116#define SIR_SERR_IRQ_MASK 0x340
117#define SIR_SATA_IFCTRL 0x344
118#define SIR_SATA_TESTCTRL 0x348
119#define SIR_SATA_IFSTATUS 0x34c
120#define SIR_VEND_UNIQ 0x35c
121#define SIR_FIS_CFG 0x360
122#define SIR_FIS_IRQ_CAUSE 0x364
123#define SIR_FIS_IRQ_MASK 0x368
124#define SIR_FIS_DWORD0 0x370
125#define SIR_FIS_DWORD1 0x374
126#define SIR_FIS_DWORD2 0x378
127#define SIR_FIS_DWORD3 0x37c
128#define SIR_FIS_DWORD4 0x380
129#define SIR_FIS_DWORD5 0x384
130#define SIR_FIS_DWORD6 0x388
131#define SIR_PHYM9_GEN2 0x398
132#define SIR_PHYM9_GEN1 0x39c
133#define SIR_PHY_CFG 0x3a0
134#define SIR_PHYCTL 0x3a4
135#define SIR_PHYM10 0x3a8
136#define SIR_PHYM12 0x3b0
137
138/* Shadow registers */
139#define PIO_DATA 0x100
140#define PIO_ERR_FEATURES 0x104
141#define PIO_SECTOR_COUNT 0x108
142#define PIO_LBA_LOW 0x10c
143#define PIO_LBA_MID 0x110
144#define PIO_LBA_HI 0x114
145#define PIO_DEVICE 0x118
146#define PIO_CMD_STATUS 0x11c
147#define PIO_STATUS_ERR (0x01 << 0)
148#define PIO_STATUS_DRQ (0x01 << 3)
149#define PIO_STATUS_DF (0x01 << 5)
150#define PIO_STATUS_DRDY (0x01 << 6)
151#define PIO_STATUS_BSY (0x01 << 7)
152#define PIO_CTRL_ALTSTAT 0x120
153
154/* SATAHC arbiter registers */
155#define SATAHC_CFG 0x000
156#define SATAHC_RQOP 0x004
157#define SATAHC_RQIP 0x008
158#define SATAHC_ICT 0x00c
159#define SATAHC_ITT 0x010
160#define SATAHC_ICR 0x014
161#define SATAHC_ICR_PORT0 (0x01 << 0)
162#define SATAHC_ICR_PORT1 (0x01 << 1)
163#define SATAHC_MIC 0x020
164#define SATAHC_MIM 0x024
165#define SATAHC_LED_CFG 0x02c
166
167#define REQUEST_QUEUE_SIZE 32
168#define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
169
170struct crqb {
171 u32 dtb_low; /* DW0 */
172 u32 dtb_high; /* DW1 */
173 u32 control_flags; /* DW2 */
174 u32 drb_count; /* DW3 */
175 u32 ata_cmd_feat; /* DW4 */
176 u32 ata_addr; /* DW5 */
177 u32 ata_addr_exp; /* DW6 */
178 u32 ata_sect_count; /* DW7 */
179};
180
181#define CRQB_ALIGN 0x400
182
183#define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
184#define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
185#define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
186#define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
187#define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
188#define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
189#define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
190#define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
191
192#define CRQB_CMDFEAT_CMDMASK (0xff << 16)
193#define CRQB_CMDFEAT_CMDSHIFT 16
194#define CRQB_CMDFEAT_FEATMASK (0xff << 16)
195#define CRQB_CMDFEAT_FEATSHIFT 24
196
197#define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
198#define CRQB_ADDR_LBA_LOWSHIFT 0
199#define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
200#define CRQB_ADDR_LBA_MIDSHIFT 8
201#define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
202#define CRQB_ADDR_LBA_HIGHSHIFT 16
203#define CRQB_ADDR_DEVICE_MASK (0xff << 24)
204#define CRQB_ADDR_DEVICE_SHIFT 24
205
206#define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
207#define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
208#define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
209#define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
210#define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
211#define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
212#define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
213#define CRQB_ADDR_FEATURE_EXP_SHIFT 24
214
215#define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
216#define CRQB_SECTCOUNT_COUNT_SHIFT 0
217#define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
218#define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
219
6d294971
MW		 220#define MVSATA_WIN_CONTROL(w) (SATAHC_BASE + 0x30 + ((w) << 4))
221#define MVSATA_WIN_BASE(w) (SATAHC_BASE + 0x34 + ((w) << 4))
169789dc
TK		 222
223struct eprd {
224 u32 phyaddr_low;
225 u32 bytecount_eot;
226 u32 phyaddr_hi;
227 u32 reserved;
228};
229
230#define EPRD_PHYADDR_MASK 0xfffffffe
231#define EPRD_BYTECOUNT_MASK 0x0000ffff
232#define EPRD_EOT (0x01 << 31)
233
234struct crpb {
235 u32 id;
236 u32 flags;
237 u32 timestamp;
238};
239
240#define CRPB_ALIGN 0x100
241
242#define READ_CMD 0
243#define WRITE_CMD 1
244
245/*
246 * Since we don't use PRDs yet max transfer size
247 * is 64KB
248 */
249#define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
250
251/* Keep track if hw is initialized or not */
252static u32 hw_init;
253
254struct mv_priv {
255 char name[12];
256 u32 link;
257 u32 regbase;
258 u32 queue_depth;
259 u16 pio;
260 u16 mwdma;
261 u16 udma;
0506620f 262 int dev_nr;
169789dc
TK		 263
264 void *crqb_alloc;
265 struct crqb *request;
266
267 void *crpb_alloc;
268 struct crpb *response;
269};
270
271static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
272{
273 ulong start;
274
275 start = get_timer(0);
276 do {
277 if ((in_le32(addr) & mask) == val)
278 return 0;
279 } while (get_timer(start) < timeout_msec);
280
281 return -ETIMEDOUT;
282}
283
284/* Cut from sata_mv in linux kernel */
0506620f 285static int mv_stop_edma_engine(struct udevice *dev, int port)
169789dc 286{
0506620f 287 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 288 int i;
289
290 /* Disable eDMA. The disable bit auto clears. */
291 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
292
293 /* Wait for the chip to confirm eDMA is off. */
294 for (i = 10000; i > 0; i--) {
295 u32 reg = in_le32(priv->regbase + EDMA_CMD);
296 if (!(reg & EDMA_CMD_ENEDMA)) {
297 debug("EDMA stop on port %d succesful\n", port);
298 return 0;
299 }
300 udelay(10);
301 }
302 debug("EDMA stop on port %d failed\n", port);
303 return -1;
304}
305
0506620f 306static int mv_start_edma_engine(struct udevice *dev, int port)
169789dc 307{
0506620f 308 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 309 u32 tmp;
310
311 /* Check preconditions */
312 tmp = in_le32(priv->regbase + SIR_SSTATUS);
313 if ((tmp & SSTATUS_DET_MASK) != 0x03) {
314 printf("Device error on port: %d\n", port);
315 return -1;
316 }
317
318 tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
319 if (tmp & (ATA_BUSY | ATA_DRQ)) {
320 printf("Device not ready on port: %d\n", port);
321 return -1;
322 }
323
324 /* Clear interrupt cause */
325 out_le32(priv->regbase + EDMA_IECR, 0x0);
326
327 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
328 tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
329 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
330
331 /* Configure edma operation */
332 tmp = in_le32(priv->regbase + EDMA_CFG);
333 tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
334 tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
335 out_le32(priv->regbase + EDMA_CFG, tmp);
336
337 out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
338
339 /* Configure fis, set all to no-wait for now */
340 out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
341
342 /* Setup request queue */
343 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
344 out_le32(priv->regbase + EDMA_RQIPR, priv->request);
345 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
346
347 /* Setup response queue */
348 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
349 out_le32(priv->regbase + EDMA_RSOPR, priv->response);
350 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
351
352 /* Start edma */
353 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
354
355 return 0;
356}
357
0506620f 358static int mv_reset_channel(struct udevice *dev, int port)
169789dc 359{
0506620f 360 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 361
362 /* Make sure edma is stopped */
0506620f 363 mv_stop_edma_engine(dev, port);
169789dc
TK		 364
365 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
366 udelay(25); /* allow reset propagation */
367 out_le32(priv->regbase + EDMA_CMD, 0);
368 mdelay(10);
369
370 return 0;
371}
372
0506620f 373static void mv_reset_port(struct udevice *dev, int port)
169789dc 374{
0506620f 375 struct mv_priv *priv = dev_get_platdata(dev);
169789dc 376
0506620f 377 mv_reset_channel(dev, port);
169789dc
TK		 378
379 out_le32(priv->regbase + EDMA_CMD, 0x0);
380 out_le32(priv->regbase + EDMA_CFG, 0x101f);
381 out_le32(priv->regbase + EDMA_IECR, 0x0);
382 out_le32(priv->regbase + EDMA_IEMR, 0x0);
383 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
384 out_le32(priv->regbase + EDMA_RQIPR, 0x0);
385 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
386 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
387 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
388 out_le32(priv->regbase + EDMA_RSOPR, 0x0);
389 out_le32(priv->regbase + EDMA_IORTO, 0xfa);
390}
391
392static void mv_reset_one_hc(void)
393{
394 out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
395 out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
396 out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
397}
398
0506620f 399static int probe_port(struct udevice *dev, int port)
169789dc 400{
0506620f 401 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 402 int tries, tries2, set15 = 0;
403 u32 tmp;
404
405 debug("Probe port: %d\n", port);
406
407 for (tries = 0; tries < 2; tries++) {
408 /* Clear SError */
409 out_le32(priv->regbase + SIR_SERROR, 0x0);
410
411 /* trigger com-init */
412 tmp = in_le32(priv->regbase + SIR_SCONTROL);
413 tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
414 out_le32(priv->regbase + SIR_SCONTROL, tmp);
415
416 mdelay(1);
417
418 tmp = in_le32(priv->regbase + SIR_SCONTROL);
419 tries2 = 5;
420 do {
421 tmp = (tmp & 0x0f0) | 0x300;
422 out_le32(priv->regbase + SIR_SCONTROL, tmp);
423 mdelay(10);
424 tmp = in_le32(priv->regbase + SIR_SCONTROL);
425 } while ((tmp & 0xf0f) != 0x300 && tries2--);
426
427 mdelay(10);
428
429 for (tries2 = 0; tries2 < 200; tries2++) {
430 tmp = in_le32(priv->regbase + SIR_SSTATUS);
431 if ((tmp & SSTATUS_DET_MASK) == 0x03) {
432 debug("Found device on port\n");
433 return 0;
434 }
435 mdelay(1);
436 }
437
438 if ((tmp & SSTATUS_DET_MASK) == 0) {
439 debug("No device attached on port %d\n", port);
440 return -ENODEV;
441 }
442
443 if (!set15) {
444 /* Try on 1.5Gb/S */
445 debug("Try 1.5Gb link\n");
446 set15 = 1;
447 out_le32(priv->regbase + SIR_SCONTROL, 0x304);
448
449 tmp = in_le32(priv->regbase + SIR_ICFG);
450 tmp &= ~SIR_CFG_GEN2EN;
451 out_le32(priv->regbase + SIR_ICFG, tmp);
452
0506620f 453 mv_reset_channel(dev, port);
169789dc
TK		 454 }
455 }
456
457 debug("Failed to probe port\n");
458 return -1;
459}
460
461/* Get request queue in pointer */
0506620f 462static int get_reqip(struct udevice *dev, int port)
169789dc 463{
0506620f 464 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 465 u32 tmp;
466
467 tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
468 tmp = tmp >> EDMA_RQIPR_IPSHIFT;
469
470 return tmp;
471}
472
0506620f 473static void set_reqip(struct udevice *dev, int port, int reqin)
169789dc 474{
0506620f 475 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 476 u32 tmp;
477
478 tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
479 tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
480 out_le32(priv->regbase + EDMA_RQIPR, tmp);
481}
482
483/* Get next available slot, ignoring possible overwrite */
0506620f 484static int get_next_reqip(struct udevice *dev, int port)
169789dc 485{
0506620f 486 int slot = get_reqip(dev, port);
169789dc
TK		 487 slot = (slot + 1) % REQUEST_QUEUE_SIZE;
488 return slot;
489}
490
491/* Get response queue in pointer */
0506620f 492static int get_rspip(struct udevice *dev, int port)
169789dc 493{
0506620f 494 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 495 u32 tmp;
496
497 tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
498 tmp = tmp >> EDMA_RSIPR_IPSHIFT;
499
500 return tmp;
501}
502
503/* Get response queue out pointer */
0506620f 504static int get_rspop(struct udevice *dev, int port)
169789dc 505{
0506620f 506 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 507 u32 tmp;
508
509 tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
510 tmp = tmp >> EDMA_RSOPR_OPSHIFT;
511 return tmp;
512}
513
514/* Get next response queue pointer */
0506620f 515static int get_next_rspop(struct udevice *dev, int port)
169789dc 516{
0506620f 517 return (get_rspop(dev, port) + 1) % RESPONSE_QUEUE_SIZE;
169789dc
TK		 518}
519
520/* Set response queue pointer */
0506620f 521static void set_rspop(struct udevice *dev, int port, int reqin)
169789dc 522{
0506620f 523 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 524 u32 tmp;
525
526 tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
527 tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
528
529 out_le32(priv->regbase + EDMA_RSOPR, tmp);
530}
531
0506620f
SR		 532static int wait_dma_completion(struct udevice *dev, int port, int index,
533 u32 timeout_msec)
169789dc
TK		 534{
535 u32 tmp, res;
536
537 tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
538 res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
539 tmp, timeout_msec);
540 if (res)
541 printf("Failed to wait for completion on port %d\n", port);
542
543 return res;
544}
545
0506620f 546static void process_responses(struct udevice *dev, int port)
169789dc
TK		 547{
548#ifdef DEBUG
0506620f 549 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 550#endif
551 u32 tmp;
0506620f 552 u32 outind = get_rspop(dev, port);
169789dc
TK		 553
554 /* Ack interrupts */
555 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
556 if (port == 0)
557 tmp &= ~(BIT(0) | BIT(8));
558 else
559 tmp &= ~(BIT(1) | BIT(9));
560 tmp &= ~(BIT(4));
561 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
562
0506620f 563 while (get_rspip(dev, port) != outind) {
169789dc
TK		 564#ifdef DEBUG
565 debug("Response index %d flags %08x on port %d\n", outind,
566 priv->response[outind].flags, port);
567#endif
0506620f
SR		 568 outind = get_next_rspop(dev, port);
569 set_rspop(dev, port, outind);
169789dc
TK		 570 }
571}
572
0506620f
SR		 573static int mv_ata_exec_ata_cmd(struct udevice *dev, int port,
574 struct sata_fis_h2d *cfis,
169789dc
TK		 575 u8 *buffer, u32 len, u32 iswrite)
576{
0506620f 577 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 578 struct crqb *req;
579 int slot;
5102af4d 580 u32 start;
169789dc
TK		 581
582 if (len >= 64 * 1024) {
583 printf("We only support <64K transfers for now\n");
584 return -1;
585 }
586
587 /* Initialize request */
0506620f 588 slot = get_reqip(dev, port);
169789dc
TK		 589 memset(&priv->request[slot], 0, sizeof(struct crqb));
590 req = &priv->request[slot];
591
592 req->dtb_low = (u32)buffer;
593
594 /* Dont use PRDs */
595 req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
596 req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
597 req->control_flags |=
598 ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
599 & CRQB_CNTRLFLAGS_PMPORTMASK);
600
601 req->drb_count = len;
602
603 req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
604 CRQB_CMDFEAT_CMDMASK;
605 req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
606 CRQB_CMDFEAT_FEATMASK;
607
608 req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
609 CRQB_ADDR_LBA_LOWMASK;
610 req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
611 CRQB_ADDR_LBA_MIDMASK;
612 req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
613 CRQB_ADDR_LBA_HIGHMASK;
614 req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
615 CRQB_ADDR_DEVICE_MASK;
616
617 req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
618 CRQB_ADDR_LBA_LOW_EXP_MASK;
619 req->ata_addr_exp |=
620 (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
621 CRQB_ADDR_LBA_MID_EXP_MASK;
622 req->ata_addr_exp |=
623 (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
624 CRQB_ADDR_LBA_HIGH_EXP_MASK;
625 req->ata_addr_exp |=
626 (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
627 CRQB_ADDR_FEATURE_EXP_MASK;
628
629 req->ata_sect_count =
630 (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
631 CRQB_SECTCOUNT_COUNT_MASK;
632 req->ata_sect_count |=
633 (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
634 CRQB_SECTCOUNT_COUNT_EXP_MASK;
635
636 /* Flush data */
5102af4d
SR		 637 start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
638 flush_dcache_range(start,
639 start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
169789dc
TK		 640
641 /* Trigger operation */
0506620f
SR		 642 slot = get_next_reqip(dev, port);
643 set_reqip(dev, port, slot);
169789dc
TK		 644
645 /* Wait for completion */
0506620f 646 if (wait_dma_completion(dev, port, slot, 10000)) {
169789dc
TK		 647 printf("ATA operation timed out\n");
648 return -1;
649 }
650
0506620f 651 process_responses(dev, port);
169789dc
TK		 652
653 /* Invalidate data on read */
5102af4d
SR		 654 if (buffer && len) {
655 start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
656 invalidate_dcache_range(start,
657 start + ALIGN(len, ARCH_DMA_MINALIGN));
658 }
169789dc
TK		 659
660 return len;
661}
662
0506620f
SR		 663static u32 mv_sata_rw_cmd_ext(struct udevice *dev, int port, lbaint_t start,
664 u32 blkcnt,
169789dc
TK		 665 u8 *buffer, int is_write)
666{
667 struct sata_fis_h2d cfis;
668 u32 res;
669 u64 block;
670
671 block = (u64)start;
672
673 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
674
675 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
676 cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
677
678 cfis.lba_high_exp = (block >> 40) & 0xff;
679 cfis.lba_mid_exp = (block >> 32) & 0xff;
680 cfis.lba_low_exp = (block >> 24) & 0xff;
681 cfis.lba_high = (block >> 16) & 0xff;
682 cfis.lba_mid = (block >> 8) & 0xff;
683 cfis.lba_low = block & 0xff;
684 cfis.device = ATA_LBA;
685 cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
686 cfis.sector_count = blkcnt & 0xff;
687
0506620f
SR		 688 res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
689 ATA_SECT_SIZE * blkcnt, is_write);
169789dc
TK		 690
691 return res >= 0 ? blkcnt : res;
692}
693
0506620f
SR		 694static u32 mv_sata_rw_cmd(struct udevice *dev, int port, lbaint_t start,
695 u32 blkcnt, u8 *buffer, int is_write)
169789dc
TK		 696{
697 struct sata_fis_h2d cfis;
698 lbaint_t block;
699 u32 res;
700
701 block = start;
702
703 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
704
705 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
706 cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
707 cfis.device = ATA_LBA;
708
709 cfis.device |= (block >> 24) & 0xf;
710 cfis.lba_high = (block >> 16) & 0xff;
711 cfis.lba_mid = (block >> 8) & 0xff;
712 cfis.lba_low = block & 0xff;
713 cfis.sector_count = (u8)(blkcnt & 0xff);
714
0506620f
SR		 715 res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
716 ATA_SECT_SIZE * blkcnt, is_write);
169789dc
TK		 717
718 return res >= 0 ? blkcnt : res;
719}
720
0506620f
SR		 721static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
722 lbaint_t blkcnt, void *buffer, int is_write)
169789dc 723{
0506620f 724 struct blk_desc *desc = dev_get_uclass_platdata(dev);
169789dc
TK		 725 lbaint_t start, blks;
726 u8 *addr;
727 int max_blks;
728
cfdf632c 729 debug("%s: " LBAFU " " LBAFU "\n", __func__, blknr, blkcnt);
169789dc
TK		 730
731 start = blknr;
732 blks = blkcnt;
733 addr = (u8 *)buffer;
734
735 max_blks = MV_ATA_MAX_SECTORS;
736 do {
737 if (blks > max_blks) {
0506620f
SR		 738 if (desc->lba48) {
739 mv_sata_rw_cmd_ext(dev, port, start, max_blks,
740 addr, is_write);
169789dc 741 } else {
0506620f
SR		 742 mv_sata_rw_cmd(dev, port, start, max_blks,
743 addr, is_write);
169789dc
TK		 744 }
745 start += max_blks;
746 blks -= max_blks;
747 addr += ATA_SECT_SIZE * max_blks;
748 } else {
0506620f
SR		 749 if (desc->lba48) {
750 mv_sata_rw_cmd_ext(dev, port, start, blks, addr,
169789dc
TK		 751 is_write);
752 } else {
0506620f 753 mv_sata_rw_cmd(dev, port, start, blks, addr,
169789dc
TK		 754 is_write);
755 }
756 start += blks;
757 blks = 0;
758 addr += ATA_SECT_SIZE * blks;
759 }
760 } while (blks != 0);
761
762 return blkcnt;
763}
764
0506620f 765static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
169789dc
TK		 766 struct sata_fis_h2d *cfis, u8 *buffer,
767 u32 len, u32 iswrite)
768{
0506620f 769 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 770 int i;
771 u16 *tp;
772
773 debug("%s\n", __func__);
774
775 out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
776 out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
777 out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
778 out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
779 out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
780 out_le32(priv->regbase + PIO_DEVICE, cfis->device);
781 out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
782
783 if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
784 ATA_BUSY, 0x0, 10000)) {
785 debug("Failed to wait for completion\n");
786 return -1;
787 }
788
789 if (len > 0) {
790 tp = (u16 *)buffer;
791 for (i = 0; i < len / 2; i++) {
792 if (iswrite)
793 out_le16(priv->regbase + PIO_DATA, *tp++);
794 else
795 *tp++ = in_le16(priv->regbase + PIO_DATA);
796 }
797 }
798
799 return len;
800}
801
0506620f 802static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
169789dc
TK		 803{
804 struct sata_fis_h2d h2d;
805
806 memset(&h2d, 0, sizeof(struct sata_fis_h2d));
807
808 h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
809 h2d.command = ATA_CMD_ID_ATA;
810
811 /* Give device time to get operational */
812 mdelay(10);
813
0506620f 814 return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
169789dc
TK		 815 ATA_ID_WORDS * 2, READ_CMD);
816}
817
0506620f 818static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
169789dc 819{
0506620f 820 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 821
822 priv->pio = id[ATA_ID_PIO_MODES];
823 priv->mwdma = id[ATA_ID_MWDMA_MODES];
824 priv->udma = id[ATA_ID_UDMA_MODES];
825 debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
826 priv->udma);
827}
828
0506620f 829static void mv_sata_set_features(struct udevice *dev, int port)
169789dc 830{
0506620f 831 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 832 struct sata_fis_h2d cfis;
833 u8 udma_cap;
834
835 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
836
837 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
838 cfis.command = ATA_CMD_SET_FEATURES;
839 cfis.features = SETFEATURES_XFER;
840
841 /* First check the device capablity */
842 udma_cap = (u8) (priv->udma & 0xff);
843
844 if (udma_cap == ATA_UDMA6)
845 cfis.sector_count = XFER_UDMA_6;
846 if (udma_cap == ATA_UDMA5)
847 cfis.sector_count = XFER_UDMA_5;
848 if (udma_cap == ATA_UDMA4)
849 cfis.sector_count = XFER_UDMA_4;
850 if (udma_cap == ATA_UDMA3)
851 cfis.sector_count = XFER_UDMA_3;
852
0506620f 853 mv_ata_exec_ata_cmd_nondma(dev, port, &cfis, NULL, 0, READ_CMD);
169789dc
TK		 854}
855
856/*
857 * Initialize SATA memory windows
858 */
859static void mvsata_ide_conf_mbus_windows(void)
860{
861 const struct mbus_dram_target_info *dram;
862 int i;
863
864 dram = mvebu_mbus_dram_info();
865
866 /* Disable windows, Set Size/Base to 0 */
867 for (i = 0; i < 4; i++) {
868 writel(0, MVSATA_WIN_CONTROL(i));
869 writel(0, MVSATA_WIN_BASE(i));
870 }
871
872 for (i = 0; i < dram->num_cs; i++) {
873 const struct mbus_dram_window *cs = dram->cs + i;
874 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
875 (dram->mbus_dram_target_id << 4) | 1,
876 MVSATA_WIN_CONTROL(i));
877 writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
878 }
879}
880
0506620f 881static int sata_mv_init_sata(struct udevice *dev, int port)
169789dc 882{
0506620f 883 struct mv_priv *priv = dev_get_platdata(dev);
169789dc 884
0506620f 885 debug("Initialize sata dev: %d\n", port);
169789dc 886
0506620f
SR		 887 if (port < 0 || port >= CONFIG_SYS_SATA_MAX_DEVICE) {
888 printf("Invalid sata device %d\n", port);
169789dc
TK		 889 return -1;
890 }
891
169789dc
TK		 892 /* Allocate and align request buffer */
893 priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
894 CRQB_ALIGN);
895 if (!priv->crqb_alloc) {
896 printf("Unable to allocate memory for request queue\n");
897 return -ENOMEM;
898 }
899 memset(priv->crqb_alloc, 0,
900 sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
901 priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
902 ~(CRQB_ALIGN - 1));
903
904 /* Allocate and align response buffer */
905 priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
906 CRPB_ALIGN);
907 if (!priv->crpb_alloc) {
908 printf("Unable to allocate memory for response queue\n");
909 return -ENOMEM;
910 }
911 memset(priv->crpb_alloc, 0,
912 sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
913 priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
914 ~(CRPB_ALIGN - 1));
915
0506620f 916 sprintf(priv->name, "SATA%d", port);
169789dc 917
0506620f 918 priv->regbase = port == 0 ? SATA0_BASE : SATA1_BASE;
169789dc
TK		 919
920 if (!hw_init) {
921 debug("Initialize sata hw\n");
922 hw_init = 1;
923 mv_reset_one_hc();
924 mvsata_ide_conf_mbus_windows();
925 }
926
0506620f 927 mv_reset_port(dev, port);
169789dc 928
0506620f 929 if (probe_port(dev, port)) {
169789dc
TK		 930 priv->link = 0;
931 return -ENODEV;
932 }
933 priv->link = 1;
934
935 return 0;
936}
937
0506620f 938static int sata_mv_scan_sata(struct udevice *dev, int port)
169789dc 939{
0506620f
SR		 940 struct blk_desc *desc = dev_get_uclass_platdata(dev);
941 struct mv_priv *priv = dev_get_platdata(dev);
169789dc
TK		 942 unsigned char serial[ATA_ID_SERNO_LEN + 1];
943 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
944 unsigned char product[ATA_ID_PROD_LEN + 1];
945 u64 n_sectors;
946 u16 *id;
169789dc
TK		 947
948 if (!priv->link)
949 return -ENODEV;
950
951 id = (u16 *)malloc(ATA_ID_WORDS * 2);
952 if (!id) {
953 printf("Failed to malloc id data\n");
954 return -ENOMEM;
955 }
956
0506620f 957 mv_sata_identify(dev, port, id);
169789dc
TK		 958 ata_swap_buf_le16(id, ATA_ID_WORDS);
959#ifdef DEBUG
960 ata_dump_id(id);
961#endif
962
963 /* Serial number */
964 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
0506620f 965 memcpy(desc->product, serial, sizeof(serial));
169789dc
TK		 966
967 /* Firmware version */
968 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
0506620f 969 memcpy(desc->revision, firmware, sizeof(firmware));
169789dc
TK		 970
971 /* Product model */
972 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
0506620f 973 memcpy(desc->vendor, product, sizeof(product));
169789dc
TK		 974
975 /* Total sectors */
976 n_sectors = ata_id_n_sectors(id);
0506620f 977 desc->lba = n_sectors;
169789dc
TK		 978
979 /* Check if support LBA48 */
980 if (ata_id_has_lba48(id)) {
0506620f 981 desc->lba48 = 1;
169789dc
TK		 982 debug("Device support LBA48\n");
983 }
984
985 /* Get the NCQ queue depth from device */
986 priv->queue_depth = ata_id_queue_depth(id);
987
988 /* Get the xfer mode from device */
0506620f 989 mv_sata_xfer_mode(dev, port, id);
169789dc
TK		 990
991 /* Set the xfer mode to highest speed */
0506620f 992 mv_sata_set_features(dev, port);
169789dc
TK		 993
994 /* Start up */
0506620f 995 mv_start_edma_engine(dev, port);
169789dc
TK		 996
997 return 0;
998}
0506620f
SR		 999
1000static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
1001 lbaint_t blkcnt, void *buffer)
1002{
1003 struct mv_priv *priv = dev_get_platdata(blk);
1004
1005 return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
1006 buffer, READ_CMD);
1007}
1008
1009static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
1010 lbaint_t blkcnt, const void *buffer)
1011{
1012 struct mv_priv *priv = dev_get_platdata(blk);
1013
1014 return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
1015 (void *)buffer, WRITE_CMD);
1016}
1017
1018static const struct blk_ops sata_mv_blk_ops = {
1019 .read = sata_mv_read,
1020 .write = sata_mv_write,
1021};
1022
1023U_BOOT_DRIVER(sata_mv_driver) = {
1024 .name = "sata_mv_blk",
1025 .id = UCLASS_BLK,
1026 .ops = &sata_mv_blk_ops,
1027 .platdata_auto_alloc_size = sizeof(struct mv_priv),
1028};
1029
1030static int sata_mv_probe(struct udevice *dev)
1031{
1032 const void *blob = gd->fdt_blob;
1033 int node = dev_of_offset(dev);
1034 struct mv_priv *priv;
1035 struct udevice *blk;
1036 int nr_ports;
1037 int ret;
1038 int i;
1039
1040 /* Get number of ports of this SATA controller */
1041 nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
1042 CONFIG_SYS_SATA_MAX_DEVICE);
1043
1044 for (i = 0; i < nr_ports; i++) {
1045 ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
1046 IF_TYPE_SATA, -1, 512, 0, &blk);
1047 if (ret) {
1048 debug("Can't create device\n");
1049 return ret;
1050 }
1051
1052 priv = dev_get_platdata(blk);
1053 priv->dev_nr = i;
1054
1055 /* Init SATA port */
1056 ret = sata_mv_init_sata(blk, i);
1057 if (ret) {
1058 debug("%s: Failed to init bus\n", __func__);
1059 return ret;
1060 }
1061
1062 /* Scan SATA port */
1063 ret = sata_mv_scan_sata(blk, i);
1064 if (ret) {
1065 debug("%s: Failed to scan bus\n", __func__);
1066 return ret;
1067 }
1068 }
1069
1070 return 0;
1071}
1072
1073static int sata_mv_scan(struct udevice *dev)
1074{
1075 /* Nothing to do here */
1076
1077 return 0;
1078}
1079
1080static const struct udevice_id sata_mv_ids[] = {
1081 { .compatible = "marvell,armada-370-sata" },
586f7b91 1082 { .compatible = "marvell,orion-sata" },
0506620f
SR		 1083 { }
1084};
1085
1086struct ahci_ops sata_mv_ahci_ops = {
1087 .scan = sata_mv_scan,
1088};
1089
1090U_BOOT_DRIVER(sata_mv_ahci) = {
1091 .name = "sata_mv_ahci",
1092 .id = UCLASS_AHCI,
1093 .of_match = sata_mv_ids,
1094 .ops = &sata_mv_ahci_ops,
1095 .probe = sata_mv_probe,
1096};
"Das U-Boot" Source Tree