[thirdparty/linux.git] / drivers / ata / sata_svw.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  sata_svw.c - ServerWorks / Apple K2 SATA
 *
 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
 *		   Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  This driver probably works with non-Apple versions of the
 *  Broadcom chipset...
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/driver-api/libata.rst
 *
 *  Hardware documentation available under NDA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi.h>
#include <linux/libata.h>
#include <linux/of.h>

#define DRV_NAME	"sata_svw"
#define DRV_VERSION	"2.3"

enum {
	/* ap->flags bits */
	K2_FLAG_SATA_8_PORTS		= (1 << 24),
	K2_FLAG_NO_ATAPI_DMA		= (1 << 25),
	K2_FLAG_BAR_POS_3			= (1 << 26),

	/* Taskfile registers offsets */
	K2_SATA_TF_CMD_OFFSET		= 0x00,
	K2_SATA_TF_DATA_OFFSET		= 0x00,
	K2_SATA_TF_ERROR_OFFSET		= 0x04,
	K2_SATA_TF_NSECT_OFFSET		= 0x08,
	K2_SATA_TF_LBAL_OFFSET		= 0x0c,
	K2_SATA_TF_LBAM_OFFSET		= 0x10,
	K2_SATA_TF_LBAH_OFFSET		= 0x14,
	K2_SATA_TF_DEVICE_OFFSET	= 0x18,
	K2_SATA_TF_CMDSTAT_OFFSET      	= 0x1c,
	K2_SATA_TF_CTL_OFFSET		= 0x20,

	/* DMA base */
	K2_SATA_DMA_CMD_OFFSET		= 0x30,

	/* SCRs base */
	K2_SATA_SCR_STATUS_OFFSET	= 0x40,
	K2_SATA_SCR_ERROR_OFFSET	= 0x44,
	K2_SATA_SCR_CONTROL_OFFSET	= 0x48,

	/* Others */
	K2_SATA_SICR1_OFFSET		= 0x80,
	K2_SATA_SICR2_OFFSET		= 0x84,
	K2_SATA_SIM_OFFSET		= 0x88,

	/* Port stride */
	K2_SATA_PORT_OFFSET		= 0x100,

	chip_svw4			= 0,
	chip_svw8			= 1,
	chip_svw42			= 2,	/* bar 3 */
	chip_svw43			= 3,	/* bar 5 */
};

static u8 k2_stat_check_status(struct ata_port *ap);


static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
{
	u8 cmnd = qc->scsicmd->cmnd[0];

	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
		return -1;	/* ATAPI DMA not supported */
	else {
		switch (cmnd) {
		case READ_10:
		case READ_12:
		case READ_16:
		case WRITE_10:
		case WRITE_12:
		case WRITE_16:
			return 0;

		default:
			return -1;
		}

	}
}

static int k2_sata_scr_read(struct ata_link *link,
			    unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int k2_sata_scr_write(struct ata_link *link,
			     unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}

static int k2_sata_softreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return ata_sff_softreset(link, class, deadline);
}

static int k2_sata_hardreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return sata_sff_hardreset(link, class, deadline);
}

static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	if (tf->ctl != ap->last_ctl) {
		writeb(tf->ctl, ioaddr->ctl_addr);
		ap->last_ctl = tf->ctl;
		ata_wait_idle(ap);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = k2_stat_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
	}
}

/**
 *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	u8 dmactl;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;

	/* load PRD table addr. */
	mb();	/* make sure PRD table writes are visible to controller */
	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = readb(mmio + ATA_DMA_CMD);
	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
	if (!rw)
		dmactl |= ATA_DMA_WR;
	writeb(dmactl, mmio + ATA_DMA_CMD);

	/* issue r/w command if this is not a ATA DMA command*/
	if (qc->tf.protocol != ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}

/**
 *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;
	u8 dmactl;

	/* start host DMA transaction */
	dmactl = readb(mmio + ATA_DMA_CMD);
	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
	/* This works around possible data corruption.

	   On certain SATA controllers that can be seen when the r/w
	   command is given to the controller before the host DMA is
	   started.

	   On a Read command, the controller would initiate the
	   command to the drive even before it sees the DMA
	   start. When there are very fast drives connected to the
	   controller, or when the data request hits in the drive
	   cache, there is the possibility that the drive returns a
	   part or all of the requested data to the controller before
	   the DMA start is issued.  In this case, the controller
	   would become confused as to what to do with the data.  In
	   the worst case when all the data is returned back to the
	   controller, the controller could hang. In other cases it
	   could return partial data returning in data
	   corruption. This problem has been seen in PPC systems and
	   can also appear on an system with very fast disks, where
	   the SATA controller is sitting behind a number of bridges,
	   and hence there is significant latency between the r/w
	   command and the start command. */
	/* issue r/w command if the access is to ATA */
	if (qc->tf.protocol == ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}


static u8 k2_stat_check_status(struct ata_port *ap)
{
	return readl(ap->ioaddr.status_addr);
}

static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
{
	struct ata_port *ap;
	struct device_node *np;
	int index;

	/* Find  the ata_port */
	ap = ata_shost_to_port(shost);
	if (ap == NULL)
		return 0;

	/* Find the OF node for the PCI device proper */
	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
	if (np == NULL)
		return 0;

	/* Match it to a port node */
	index = (ap == ap->host->ports[0]) ? 0 : 1;
	for (np = np->child; np != NULL; np = np->sibling) {
		const u32 *reg = of_get_property(np, "reg", NULL);
		if (!reg)
			continue;
		if (index == *reg) {
			seq_printf(m, "devspec: %pOF\n", np);
			break;
		}
	}
	return 0;
}

static struct scsi_host_template k2_sata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
	.show_info		= k2_sata_show_info,
};


static struct ata_port_operations k2_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.softreset              = k2_sata_softreset,
	.hardreset              = k2_sata_hardreset,
	.sff_tf_load		= k2_sata_tf_load,
	.sff_tf_read		= k2_sata_tf_read,
	.sff_check_status	= k2_stat_check_status,
	.check_atapi_dma	= k2_sata_check_atapi_dma,
	.bmdma_setup		= k2_bmdma_setup_mmio,
	.bmdma_start		= k2_bmdma_start_mmio,
	.scr_read		= k2_sata_scr_read,
	.scr_write		= k2_sata_scr_write,
};

static const struct ata_port_info k2_port_info[] = {
	/* chip_svw4 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw8 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
				  K2_FLAG_SATA_8_PORTS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw42 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw43 */
	{
		.flags		= ATA_FLAG_SATA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
};

static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
	port->feature_addr	=
	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
	port->command_addr	=
	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
	port->altstatus_addr	=
	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
}


static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct ata_port_info *ppi[] =
		{ &k2_port_info[ent->driver_data], NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int n_ports, i, rc, bar_pos;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* allocate host */
	n_ports = 4;
	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
		n_ports = 8;

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	if (!host)
		return -ENOMEM;

	bar_pos = 5;
	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
		bar_pos = 3;
	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/*
	 * Check if we have resources mapped at all (second function may
	 * have been disabled by firmware)
	 */
	if (pci_resource_len(pdev, bar_pos) == 0) {
		/* In IDE mode we need to pin the device to ensure that
			pcim_release does not clear the busmaster bit in config
			space, clearing causes busmaster DMA to fail on
			ports 3 & 4 */
		pcim_pin_device(pdev);
		return -ENODEV;
	}

	/* Request and iomap PCI regions */
	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	mmio_base = host->iomap[bar_pos];

	/* different controllers have different number of ports - currently 4 or 8 */
	/* All ports are on the same function. Multi-function device is no
	 * longer available. This should not be seen in any system. */
	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = i * K2_SATA_PORT_OFFSET;

		k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, 5, -1, "mmio");
		ata_port_pbar_desc(ap, 5, offset, "port");
	}

	rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
	if (rc)
		return rc;

	/* Clear a magic bit in SCR1 according to Darwin, those help
	 * some funky seagate drives (though so far, those were already
	 * set by the firmware on the machines I had access to)
	 */
	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	       mmio_base + K2_SATA_SICR1_OFFSET);

	/* Clear SATA error & interrupts we don't use */
	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &k2_sata_sht);
}

/* 0x240 is device ID for Apple K2 device
 * 0x241 is device ID for Serverworks Frodo4
 * 0x242 is device ID for Serverworks Frodo8
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 * controller
 * */
static const struct pci_device_id k2_sata_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },

	{ }
};

static struct pci_driver k2_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= k2_sata_pci_tbl,
	.probe			= k2_sata_init_one,
	.remove			= ata_pci_remove_one,
};

module_pci_driver(k2_sata_pci_driver);

MODULE_AUTHOR("Benjamin Herrenschmidt");
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
c82ee6d3	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* sata_svw.c - ServerWorks / Apple K2 SATA
	4	*
	5	* Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
	6	* Jeff Garzik <jgarzik@pobox.com>
	7	* Please ALWAYS copy linux-ide@vger.kernel.org
	8	* on emails.
	9	*
	10	* Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
	11	*
	12	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	13	*
	14	* This driver probably works with non-Apple versions of the
	15	* Broadcom chipset...
	16	*
af36d7f0	17	* libata documentation is available via 'make {ps\|pdf}docs',
19285f3c	18	* as Documentation/driver-api/libata.rst
af36d7f0 JG	19	*
af36d7f0 JG	20	* Hardware documentation available under NDA.
1da177e4 LT	21	*/
1da177e4 LT	22
1da177e4 LT	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/pci.h>
1da177e4 LT	26	#include <linux/blkdev.h>
	27	#include <linux/delay.h>
	28	#include <linux/interrupt.h>
a9524a76	29	#include <linux/device.h>
1da177e4	30	#include <scsi/scsi_host.h>
931506d3 AS	31	#include <scsi/scsi_cmnd.h>
931506d3 AS	32	#include <scsi/scsi.h>
1da177e4	33	#include <linux/libata.h>
d610f503	34	#include <linux/of.h>
1da177e4 LT	35
1da177e4 LT	36	#define DRV_NAME "sata_svw"
2a3103ce	37	#define DRV_VERSION "2.3"
1da177e4	38
55cca65e	39	enum {
4447d351 TH	40	/* ap->flags bits */
	41	K2_FLAG_SATA_8_PORTS = (1 << 24),
	42	K2_FLAG_NO_ATAPI_DMA = (1 << 25),
931506d3	43	K2_FLAG_BAR_POS_3 = (1 << 26),
c10340ac	44
55cca65e JG	45	/* Taskfile registers offsets */
	46	K2_SATA_TF_CMD_OFFSET = 0x00,
	47	K2_SATA_TF_DATA_OFFSET = 0x00,
	48	K2_SATA_TF_ERROR_OFFSET = 0x04,
	49	K2_SATA_TF_NSECT_OFFSET = 0x08,
	50	K2_SATA_TF_LBAL_OFFSET = 0x0c,
	51	K2_SATA_TF_LBAM_OFFSET = 0x10,
	52	K2_SATA_TF_LBAH_OFFSET = 0x14,
	53	K2_SATA_TF_DEVICE_OFFSET = 0x18,
	54	K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
	55	K2_SATA_TF_CTL_OFFSET = 0x20,
1da177e4	56
55cca65e JG	57	/* DMA base */
55cca65e JG	58	K2_SATA_DMA_CMD_OFFSET = 0x30,
1da177e4	59
55cca65e JG	60	/* SCRs base */
	61	K2_SATA_SCR_STATUS_OFFSET = 0x40,
	62	K2_SATA_SCR_ERROR_OFFSET = 0x44,
	63	K2_SATA_SCR_CONTROL_OFFSET = 0x48,
1da177e4	64
55cca65e JG	65	/* Others */
	66	K2_SATA_SICR1_OFFSET = 0x80,
	67	K2_SATA_SICR2_OFFSET = 0x84,
	68	K2_SATA_SIM_OFFSET = 0x88,
1da177e4	69
55cca65e JG	70	/* Port stride */
55cca65e JG	71	K2_SATA_PORT_OFFSET = 0x100,
c10340ac	72
931506d3 AS	73	chip_svw4 = 0,
	74	chip_svw8 = 1,
	75	chip_svw42 = 2, /* bar 3 */
	76	chip_svw43 = 3, /* bar 5 */
c10340ac JG	77	};
c10340ac JG	78
ac19bff2 JG	79	static u8 k2_stat_check_status(struct ata_port *ap);
ac19bff2 JG	80
1da177e4	81
c10340ac JG	82	static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
c10340ac JG	83	{
931506d3 AS	84	u8 cmnd = qc->scsicmd->cmnd[0];
931506d3 AS	85
c10340ac JG	86	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
c10340ac JG	87	return -1; /* ATAPI DMA not supported */
931506d3 AS	88	else {
	89	switch (cmnd) {
	90	case READ_10:
	91	case READ_12:
	92	case READ_16:
	93	case WRITE_10:
	94	case WRITE_12:
	95	case WRITE_16:
	96	return 0;
	97
	98	default:
	99	return -1;
	100	}
c10340ac	101
931506d3	102	}
c10340ac JG	103	}
c10340ac JG	104
82ef04fb TH	105	static int k2_sata_scr_read(struct ata_link *link,
82ef04fb TH	106	unsigned int sc_reg, u32 *val)
1da177e4 LT	107	{
1da177e4 LT	108	if (sc_reg > SCR_CONTROL)
da3dbb17	109	return -EINVAL;
82ef04fb	110	val = readl(link->ap->ioaddr.scr_addr + (sc_reg 4));
da3dbb17	111	return 0;
1da177e4 LT	112	}
	113
	114
82ef04fb TH	115	static int k2_sata_scr_write(struct ata_link *link,
82ef04fb TH	116	unsigned int sc_reg, u32 val)
1da177e4 LT	117	{
1da177e4 LT	118	if (sc_reg > SCR_CONTROL)
da3dbb17	119	return -EINVAL;
82ef04fb	120	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	121	return 0;
1da177e4 LT	122	}
1da177e4 LT	123
b03e66a6 DM	124	static int k2_sata_softreset(struct ata_link *link,
	125	unsigned int *class, unsigned long deadline)
	126	{
	127	u8 dmactl;
	128	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	129
	130	dmactl = readb(mmio + ATA_DMA_CMD);
	131
	132	/* Clear the start bit */
	133	if (dmactl & ATA_DMA_START) {
	134	dmactl &= ~ATA_DMA_START;
	135	writeb(dmactl, mmio + ATA_DMA_CMD);
	136	}
	137
	138	return ata_sff_softreset(link, class, deadline);
	139	}
	140
	141	static int k2_sata_hardreset(struct ata_link *link,
	142	unsigned int *class, unsigned long deadline)
	143	{
	144	u8 dmactl;
	145	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	146
	147	dmactl = readb(mmio + ATA_DMA_CMD);
	148
	149	/* Clear the start bit */
	150	if (dmactl & ATA_DMA_START) {
	151	dmactl &= ~ATA_DMA_START;
	152	writeb(dmactl, mmio + ATA_DMA_CMD);
	153	}
	154
	155	return sata_sff_hardreset(link, class, deadline);
	156	}
1da177e4	157
057ace5e	158	static void k2_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	159	{
	160	struct ata_ioports *ioaddr = &ap->ioaddr;
	161	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	162
	163	if (tf->ctl != ap->last_ctl) {
0d5ff566	164	writeb(tf->ctl, ioaddr->ctl_addr);
1da177e4 LT	165	ap->last_ctl = tf->ctl;
	166	ata_wait_idle(ap);
	167	}
	168	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	169	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	170	ioaddr->feature_addr);
850a9d8a	171	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	172	ioaddr->nsect_addr);
850a9d8a	173	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	174	ioaddr->lbal_addr);
850a9d8a	175	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	176	ioaddr->lbam_addr);
850a9d8a	177	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	178	ioaddr->lbah_addr);
1da177e4	179	} else if (is_addr) {
0d5ff566 TH	180	writew(tf->feature, ioaddr->feature_addr);
	181	writew(tf->nsect, ioaddr->nsect_addr);
	182	writew(tf->lbal, ioaddr->lbal_addr);
	183	writew(tf->lbam, ioaddr->lbam_addr);
	184	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	185	}
	186
	187	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	188	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	189
	190	ata_wait_idle(ap);
	191	}
	192
	193
	194	static void k2_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	195	{
	196	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	197	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	198
ac19bff2	199	tf->command = k2_stat_check_status(ap);
0d5ff566 TH	200	tf->device = readw(ioaddr->device_addr);
	201	feature = readw(ioaddr->error_addr);
	202	nsect = readw(ioaddr->nsect_addr);
	203	lbal = readw(ioaddr->lbal_addr);
	204	lbam = readw(ioaddr->lbam_addr);
	205	lbah = readw(ioaddr->lbah_addr);
ac19bff2 JG	206
	207	tf->feature = feature;
	208	tf->nsect = nsect;
	209	tf->lbal = lbal;
	210	tf->lbam = lbam;
	211	tf->lbah = lbah;
1da177e4 LT	212
1da177e4 LT	213	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	214	tf->hob_feature = feature >> 8;
1da177e4 LT	215	tf->hob_nsect = nsect >> 8;
	216	tf->hob_lbal = lbal >> 8;
	217	tf->hob_lbam = lbam >> 8;
	218	tf->hob_lbah = lbah >> 8;
5796d1c4	219	}
1da177e4 LT	220	}
	221
	222	/**
	223	* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
	224	* @qc: Info associated with this ATA transaction.
	225	*
	226	* LOCKING:
cca3974e	227	* spin_lock_irqsave(host lock)
1da177e4 LT	228	*/
1da177e4 LT	229
5796d1c4	230	static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	231	{
	232	struct ata_port *ap = qc->ap;
	233	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	234	u8 dmactl;
59f99880 JG	235	void __iomem *mmio = ap->ioaddr.bmdma_addr;
59f99880 JG	236
1da177e4 LT	237	/* load PRD table addr. */
1da177e4 LT	238	mb(); /* make sure PRD table writes are visible to controller */
f60d7011	239	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
1da177e4 LT	240
	241	/* specify data direction, triple-check start bit is clear */
	242	dmactl = readb(mmio + ATA_DMA_CMD);
	243	dmactl &= ~(ATA_DMA_WR \| ATA_DMA_START);
	244	if (!rw)
	245	dmactl \|= ATA_DMA_WR;
	246	writeb(dmactl, mmio + ATA_DMA_CMD);
	247
	248	/* issue r/w command if this is not a ATA DMA command*/
	249	if (qc->tf.protocol != ATA_PROT_DMA)
5682ed33	250	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	251	}
	252
	253	/**
	254	* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
	255	* @qc: Info associated with this ATA transaction.
	256	*
	257	* LOCKING:
cca3974e	258	* spin_lock_irqsave(host lock)
1da177e4 LT	259	*/
1da177e4 LT	260
5796d1c4	261	static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	262	{
1da177e4 LT	263	struct ata_port *ap = qc->ap;
59f99880	264	void __iomem *mmio = ap->ioaddr.bmdma_addr;
1da177e4 LT	265	u8 dmactl;
	266
	267	/* start host DMA transaction */
	268	dmactl = readb(mmio + ATA_DMA_CMD);
	269	writeb(dmactl \| ATA_DMA_START, mmio + ATA_DMA_CMD);
ec6add99 PM	270	/* This works around possible data corruption.
	271
	272	On certain SATA controllers that can be seen when the r/w
	273	command is given to the controller before the host DMA is
	274	started.
	275
	276	On a Read command, the controller would initiate the
	277	command to the drive even before it sees the DMA
	278	start. When there are very fast drives connected to the
	279	controller, or when the data request hits in the drive
	280	cache, there is the possibility that the drive returns a
	281	part or all of the requested data to the controller before
	282	the DMA start is issued. In this case, the controller
	283	would become confused as to what to do with the data. In
	284	the worst case when all the data is returned back to the
	285	controller, the controller could hang. In other cases it
	286	could return partial data returning in data
	287	corruption. This problem has been seen in PPC systems and
	288	can also appear on an system with very fast disks, where
	289	the SATA controller is sitting behind a number of bridges,
	290	and hence there is significant latency between the r/w
	291	command and the start command. */
	292	/* issue r/w command if the access is to ATA */
1da177e4	293	if (qc->tf.protocol == ATA_PROT_DMA)
5682ed33	294	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	295	}
1da177e4 LT	296
8a60a071	297
1da177e4 LT	298	static u8 k2_stat_check_status(struct ata_port *ap)
1da177e4 LT	299	{
5796d1c4	300	return readl(ap->ioaddr.status_addr);
1da177e4 LT	301	}
1da177e4 LT	302
3f025677	303	static int k2_sata_show_info(struct seq_file m, struct Scsi_Host shost)
1da177e4 LT	304	{
	305	struct ata_port *ap;
	306	struct device_node *np;
3f025677	307	int index;
1da177e4 LT	308
1da177e4 LT	309	/* Find the ata_port */
35bb94b1	310	ap = ata_shost_to_port(shost);
1da177e4 LT	311	if (ap == NULL)
	312	return 0;
	313
	314	/* Find the OF node for the PCI device proper */
cca3974e	315	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
1da177e4 LT	316	if (np == NULL)
	317	return 0;
	318
	319	/* Match it to a port node */
cca3974e	320	index = (ap == ap->host->ports[0]) ? 0 : 1;
1da177e4	321	for (np = np->child; np != NULL; np = np->sibling) {
40cd3a45	322	const u32 *reg = of_get_property(np, "reg", NULL);
1da177e4 LT	323	if (!reg)
1da177e4 LT	324	continue;
3f025677	325	if (index == *reg) {
cf8984bf	326	seq_printf(m, "devspec: %pOF\n", np);
1da177e4	327	break;
3f025677	328	}
1da177e4	329	}
3f025677	330	return 0;
1da177e4	331	}
1da177e4	332
193515d5	333	static struct scsi_host_template k2_sata_sht = {
68d1d07b	334	ATA_BMDMA_SHT(DRV_NAME),
3f025677	335	.show_info = k2_sata_show_info,
1da177e4 LT	336	};
	337
	338
029cfd6b TH	339	static struct ata_port_operations k2_sata_ops = {
029cfd6b TH	340	.inherits = &ata_bmdma_port_ops,
b03e66a6 DM	341	.softreset = k2_sata_softreset,
b03e66a6 DM	342	.hardreset = k2_sata_hardreset,
5682ed33 TH	343	.sff_tf_load = k2_sata_tf_load,
	344	.sff_tf_read = k2_sata_tf_read,
	345	.sff_check_status = k2_stat_check_status,
c10340ac	346	.check_atapi_dma = k2_sata_check_atapi_dma,
1da177e4 LT	347	.bmdma_setup = k2_bmdma_setup_mmio,
1da177e4 LT	348	.bmdma_start = k2_bmdma_start_mmio,
1da177e4 LT	349	.scr_read = k2_sata_scr_read,
1da177e4 LT	350	.scr_write = k2_sata_scr_write,
1da177e4 LT	351	};
1da177e4 LT	352
4447d351	353	static const struct ata_port_info k2_port_info[] = {
931506d3	354	/* chip_svw4 */
4447d351	355	{
9cbe056f	356	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA,
14bdef98 EIB	357	.pio_mask = ATA_PIO4,
14bdef98 EIB	358	.mwdma_mask = ATA_MWDMA2,
bf6263a8	359	.udma_mask = ATA_UDMA6,
4447d351 TH	360	.port_ops = &k2_sata_ops,
4447d351 TH	361	},
931506d3	362	/* chip_svw8 */
4447d351	363	{
9cbe056f SS	364	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA \|
9cbe056f SS	365	K2_FLAG_SATA_8_PORTS,
14bdef98 EIB	366	.pio_mask = ATA_PIO4,
14bdef98 EIB	367	.mwdma_mask = ATA_MWDMA2,
bf6263a8	368	.udma_mask = ATA_UDMA6,
4447d351 TH	369	.port_ops = &k2_sata_ops,
4447d351 TH	370	},
931506d3 AS	371	/* chip_svw42 */
931506d3 AS	372	{
9cbe056f	373	.flags = ATA_FLAG_SATA \| K2_FLAG_BAR_POS_3,
14bdef98 EIB	374	.pio_mask = ATA_PIO4,
14bdef98 EIB	375	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	376	.udma_mask = ATA_UDMA6,
	377	.port_ops = &k2_sata_ops,
	378	},
	379	/* chip_svw43 */
	380	{
9cbe056f	381	.flags = ATA_FLAG_SATA,
14bdef98 EIB	382	.pio_mask = ATA_PIO4,
14bdef98 EIB	383	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	384	.udma_mask = ATA_UDMA6,
	385	.port_ops = &k2_sata_ops,
	386	},
4447d351 TH	387	};
4447d351 TH	388
0d5ff566	389	static void k2_sata_setup_port(struct ata_ioports port, void __iomem base)
1da177e4 LT	390	{
	391	port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
	392	port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
	393	port->feature_addr =
	394	port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
	395	port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
	396	port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
	397	port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
	398	port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
	399	port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
	400	port->command_addr =
	401	port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
	402	port->altstatus_addr =
	403	port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
	404	port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
	405	port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
	406	}
	407
	408
5796d1c4	409	static int k2_sata_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4	410	{
4447d351 TH	411	const struct ata_port_info *ppi[] =
	412	{ &k2_port_info[ent->driver_data], NULL };
	413	struct ata_host *host;
ea6ba10b	414	void __iomem *mmio_base;
931506d3	415	int n_ports, i, rc, bar_pos;
1da177e4	416
06296a1e	417	ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4	418
4447d351 TH	419	/* allocate host */
	420	n_ports = 4;
	421	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
	422	n_ports = 8;
	423
	424	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	425	if (!host)
	426	return -ENOMEM;
	427
931506d3 AS	428	bar_pos = 5;
	429	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
	430	bar_pos = 3;
1da177e4 LT	431	/*
	432	* If this driver happens to only be useful on Apple's K2, then
	433	* we should check that here as it has a normal Serverworks ID
	434	*/
24dc5f33	435	rc = pcim_enable_device(pdev);
1da177e4 LT	436	if (rc)
1da177e4 LT	437	return rc;
4447d351	438
1da177e4 LT	439	/*
	440	* Check if we have resources mapped at all (second function may
	441	* have been disabled by firmware)
	442	*/
931506d3 AS	443	if (pci_resource_len(pdev, bar_pos) == 0) {
	444	/* In IDE mode we need to pin the device to ensure that
	445	pcim_release does not clear the busmaster bit in config
	446	space, clearing causes busmaster DMA to fail on
	447	ports 3 & 4 */
	448	pcim_pin_device(pdev);
1da177e4	449	return -ENODEV;
931506d3	450	}
1da177e4	451
0d5ff566	452	/* Request and iomap PCI regions */
931506d3	453	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
0d5ff566	454	if (rc == -EBUSY)
24dc5f33	455	pcim_pin_device(pdev);
0d5ff566	456	if (rc)
24dc5f33	457	return rc;
4447d351	458	host->iomap = pcim_iomap_table(pdev);
931506d3	459	mmio_base = host->iomap[bar_pos];
4447d351 TH	460
	461	/* different controllers have different number of ports - currently 4 or 8 */
	462	/* All ports are on the same function. Multi-function device is no
	463	* longer available. This should not be seen in any system. */
cbcdd875 TH	464	for (i = 0; i < host->n_ports; i++) {
	465	struct ata_port *ap = host->ports[i];
	466	unsigned int offset = i * K2_SATA_PORT_OFFSET;
	467
	468	k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	469
	470	ata_port_pbar_desc(ap, 5, -1, "mmio");
	471	ata_port_pbar_desc(ap, 5, offset, "port");
	472	}
1da177e4	473
b5e55556	474	rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
1da177e4	475	if (rc)
24dc5f33	476	return rc;
1da177e4	477
0d5ff566 TH	478	/* Clear a magic bit in SCR1 according to Darwin, those help
	479	* some funky seagate drives (though so far, those were already
	480	* set by the firmware on the machines I had access to)
	481	*/
	482	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	483	mmio_base + K2_SATA_SICR1_OFFSET);
	484
	485	/* Clear SATA error & interrupts we don't use */
	486	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	487	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
1da177e4 LT	488
1da177e4 LT	489	pci_set_master(pdev);
c3b28894	490	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382	491	IRQF_SHARED, &k2_sata_sht);
1da177e4 LT	492	}
1da177e4 LT	493
60bf09a3 NS	494	/* 0x240 is device ID for Apple K2 device
	495	* 0x241 is device ID for Serverworks Frodo4
	496	* 0x242 is device ID for Serverworks Frodo8
	497	* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
	498	* controller
	499	* */
3b7d697d	500	static const struct pci_device_id k2_sata_pci_tbl[] = {
931506d3	501	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
aeb74914 JG	502	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
aeb74914 JG	503	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
931506d3 AS	504	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	505	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	506	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	507	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
2d2744fc	508
1da177e4 LT	509	{ }
	510	};
	511
1da177e4 LT	512	static struct pci_driver k2_sata_pci_driver = {
	513	.name = DRV_NAME,
	514	.id_table = k2_sata_pci_tbl,
	515	.probe = k2_sata_init_one,
	516	.remove = ata_pci_remove_one,
	517	};
	518
2fc75da0	519	module_pci_driver(k2_sata_pci_driver);
1da177e4	520
1da177e4 LT	521	MODULE_AUTHOR("Benjamin Herrenschmidt");
	522	MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
	523	MODULE_LICENSE("GPL");
	524	MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
	525	MODULE_VERSION(DRV_VERSION);