[people/ms/linux.git] / drivers / ata / sata_svw.c

/*
 *  sata_svw.c - ServerWorks / Apple K2 SATA
 *
 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
 *		   Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  This driver probably works with non-Apple versions of the
 *  Broadcom chipset...
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi.h>
#include <linux/libata.h>
#include <linux/of.h>

#define DRV_NAME	"sata_svw"
#define DRV_VERSION	"2.3"

enum {
	/* ap->flags bits */
	K2_FLAG_SATA_8_PORTS		= (1 << 24),
	K2_FLAG_NO_ATAPI_DMA		= (1 << 25),
	K2_FLAG_BAR_POS_3			= (1 << 26),

	/* Taskfile registers offsets */
	K2_SATA_TF_CMD_OFFSET		= 0x00,
	K2_SATA_TF_DATA_OFFSET		= 0x00,
	K2_SATA_TF_ERROR_OFFSET		= 0x04,
	K2_SATA_TF_NSECT_OFFSET		= 0x08,
	K2_SATA_TF_LBAL_OFFSET		= 0x0c,
	K2_SATA_TF_LBAM_OFFSET		= 0x10,
	K2_SATA_TF_LBAH_OFFSET		= 0x14,
	K2_SATA_TF_DEVICE_OFFSET	= 0x18,
	K2_SATA_TF_CMDSTAT_OFFSET      	= 0x1c,
	K2_SATA_TF_CTL_OFFSET		= 0x20,

	/* DMA base */
	K2_SATA_DMA_CMD_OFFSET		= 0x30,

	/* SCRs base */
	K2_SATA_SCR_STATUS_OFFSET	= 0x40,
	K2_SATA_SCR_ERROR_OFFSET	= 0x44,
	K2_SATA_SCR_CONTROL_OFFSET	= 0x48,

	/* Others */
	K2_SATA_SICR1_OFFSET		= 0x80,
	K2_SATA_SICR2_OFFSET		= 0x84,
	K2_SATA_SIM_OFFSET		= 0x88,

	/* Port stride */
	K2_SATA_PORT_OFFSET		= 0x100,

	chip_svw4			= 0,
	chip_svw8			= 1,
	chip_svw42			= 2,	/* bar 3 */
	chip_svw43			= 3,	/* bar 5 */
};

static u8 k2_stat_check_status(struct ata_port *ap);


static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
{
	u8 cmnd = qc->scsicmd->cmnd[0];

	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
		return -1;	/* ATAPI DMA not supported */
	else {
		switch (cmnd) {
		case READ_10:
		case READ_12:
		case READ_16:
		case WRITE_10:
		case WRITE_12:
		case WRITE_16:
			return 0;

		default:
			return -1;
		}

	}
}

static int k2_sata_scr_read(struct ata_link *link,
			    unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int k2_sata_scr_write(struct ata_link *link,
			     unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}

static int k2_sata_softreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return ata_sff_softreset(link, class, deadline);
}

static int k2_sata_hardreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return sata_sff_hardreset(link, class, deadline);
}

static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	if (tf->ctl != ap->last_ctl) {
		writeb(tf->ctl, ioaddr->ctl_addr);
		ap->last_ctl = tf->ctl;
		ata_wait_idle(ap);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = k2_stat_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
	}
}

/**
 *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	u8 dmactl;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;

	/* load PRD table addr. */
	mb();	/* make sure PRD table writes are visible to controller */
	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = readb(mmio + ATA_DMA_CMD);
	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
	if (!rw)
		dmactl |= ATA_DMA_WR;
	writeb(dmactl, mmio + ATA_DMA_CMD);

	/* issue r/w command if this is not a ATA DMA command*/
	if (qc->tf.protocol != ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}

/**
 *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;
	u8 dmactl;

	/* start host DMA transaction */
	dmactl = readb(mmio + ATA_DMA_CMD);
	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
	/* This works around possible data corruption.

	   On certain SATA controllers that can be seen when the r/w
	   command is given to the controller before the host DMA is
	   started.

	   On a Read command, the controller would initiate the
	   command to the drive even before it sees the DMA
	   start. When there are very fast drives connected to the
	   controller, or when the data request hits in the drive
	   cache, there is the possibility that the drive returns a
	   part or all of the requested data to the controller before
	   the DMA start is issued.  In this case, the controller
	   would become confused as to what to do with the data.  In
	   the worst case when all the data is returned back to the
	   controller, the controller could hang. In other cases it
	   could return partial data returning in data
	   corruption. This problem has been seen in PPC systems and
	   can also appear on an system with very fast disks, where
	   the SATA controller is sitting behind a number of bridges,
	   and hence there is significant latency between the r/w
	   command and the start command. */
	/* issue r/w command if the access is to ATA */
	if (qc->tf.protocol == ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}


static u8 k2_stat_check_status(struct ata_port *ap)
{
	return readl(ap->ioaddr.status_addr);
}

static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
{
	struct ata_port *ap;
	struct device_node *np;
	int index;

	/* Find  the ata_port */
	ap = ata_shost_to_port(shost);
	if (ap == NULL)
		return 0;

	/* Find the OF node for the PCI device proper */
	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
	if (np == NULL)
		return 0;

	/* Match it to a port node */
	index = (ap == ap->host->ports[0]) ? 0 : 1;
	for (np = np->child; np != NULL; np = np->sibling) {
		const u32 *reg = of_get_property(np, "reg", NULL);
		if (!reg)
			continue;
		if (index == *reg) {
			seq_printf(m, "devspec: %s\n", np->full_name);
			break;
		}
	}
	return 0;
}

static struct scsi_host_template k2_sata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
	.show_info		= k2_sata_show_info,
};


static struct ata_port_operations k2_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.softreset              = k2_sata_softreset,
	.hardreset              = k2_sata_hardreset,
	.sff_tf_load		= k2_sata_tf_load,
	.sff_tf_read		= k2_sata_tf_read,
	.sff_check_status	= k2_stat_check_status,
	.check_atapi_dma	= k2_sata_check_atapi_dma,
	.bmdma_setup		= k2_bmdma_setup_mmio,
	.bmdma_start		= k2_bmdma_start_mmio,
	.scr_read		= k2_sata_scr_read,
	.scr_write		= k2_sata_scr_write,
};

static const struct ata_port_info k2_port_info[] = {
	/* chip_svw4 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw8 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
				  K2_FLAG_SATA_8_PORTS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw42 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw43 */
	{
		.flags		= ATA_FLAG_SATA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
};

static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
	port->feature_addr	=
	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
	port->command_addr	=
	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
	port->altstatus_addr	=
	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
}


static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct ata_port_info *ppi[] =
		{ &k2_port_info[ent->driver_data], NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int n_ports, i, rc, bar_pos;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* allocate host */
	n_ports = 4;
	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
		n_ports = 8;

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	if (!host)
		return -ENOMEM;

	bar_pos = 5;
	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
		bar_pos = 3;
	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/*
	 * Check if we have resources mapped at all (second function may
	 * have been disabled by firmware)
	 */
	if (pci_resource_len(pdev, bar_pos) == 0) {
		/* In IDE mode we need to pin the device to ensure that
			pcim_release does not clear the busmaster bit in config
			space, clearing causes busmaster DMA to fail on
			ports 3 & 4 */
		pcim_pin_device(pdev);
		return -ENODEV;
	}

	/* Request and iomap PCI regions */
	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	mmio_base = host->iomap[bar_pos];

	/* different controllers have different number of ports - currently 4 or 8 */
	/* All ports are on the same function. Multi-function device is no
	 * longer available. This should not be seen in any system. */
	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = i * K2_SATA_PORT_OFFSET;

		k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, 5, -1, "mmio");
		ata_port_pbar_desc(ap, 5, offset, "port");
	}

	rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
	if (rc)
		return rc;

	/* Clear a magic bit in SCR1 according to Darwin, those help
	 * some funky seagate drives (though so far, those were already
	 * set by the firmware on the machines I had access to)
	 */
	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	       mmio_base + K2_SATA_SICR1_OFFSET);

	/* Clear SATA error & interrupts we don't use */
	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &k2_sata_sht);
}

/* 0x240 is device ID for Apple K2 device
 * 0x241 is device ID for Serverworks Frodo4
 * 0x242 is device ID for Serverworks Frodo8
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 * controller
 * */
static const struct pci_device_id k2_sata_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },

	{ }
};

static struct pci_driver k2_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= k2_sata_pci_tbl,
	.probe			= k2_sata_init_one,
	.remove			= ata_pci_remove_one,
};

module_pci_driver(k2_sata_pci_driver);

MODULE_AUTHOR("Benjamin Herrenschmidt");
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_svw.c - ServerWorks / Apple K2 SATA
	3	*
	4	* Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
	5	* Jeff Garzik <jgarzik@pobox.com>
	6	* Please ALWAYS copy linux-ide@vger.kernel.org
	7	* on emails.
	8	*
	9	* Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
	10	*
	11	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	12	*
	13	* This driver probably works with non-Apple versions of the
	14	* Broadcom chipset...
	15	*
af36d7f0 JG	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License as published by
	19	* the Free Software Foundation; either version 2, or (at your option)
	20	* any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; see the file COPYING. If not, write to
	29	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	30	*
	31	*
	32	* libata documentation is available via 'make {ps\|pdf}docs',
	33	* as Documentation/DocBook/libata.*
	34	*
	35	* Hardware documentation available under NDA.
1da177e4 LT	36	*
	37	*/
	38
1da177e4 LT	39	#include <linux/kernel.h>
	40	#include <linux/module.h>
	41	#include <linux/pci.h>
1da177e4 LT	42	#include <linux/blkdev.h>
	43	#include <linux/delay.h>
	44	#include <linux/interrupt.h>
a9524a76	45	#include <linux/device.h>
1da177e4	46	#include <scsi/scsi_host.h>
931506d3 AS	47	#include <scsi/scsi_cmnd.h>
931506d3 AS	48	#include <scsi/scsi.h>
1da177e4	49	#include <linux/libata.h>
d610f503	50	#include <linux/of.h>
1da177e4 LT	51
1da177e4 LT	52	#define DRV_NAME "sata_svw"
2a3103ce	53	#define DRV_VERSION "2.3"
1da177e4	54
55cca65e	55	enum {
4447d351 TH	56	/* ap->flags bits */
	57	K2_FLAG_SATA_8_PORTS = (1 << 24),
	58	K2_FLAG_NO_ATAPI_DMA = (1 << 25),
931506d3	59	K2_FLAG_BAR_POS_3 = (1 << 26),
c10340ac	60
55cca65e JG	61	/* Taskfile registers offsets */
	62	K2_SATA_TF_CMD_OFFSET = 0x00,
	63	K2_SATA_TF_DATA_OFFSET = 0x00,
	64	K2_SATA_TF_ERROR_OFFSET = 0x04,
	65	K2_SATA_TF_NSECT_OFFSET = 0x08,
	66	K2_SATA_TF_LBAL_OFFSET = 0x0c,
	67	K2_SATA_TF_LBAM_OFFSET = 0x10,
	68	K2_SATA_TF_LBAH_OFFSET = 0x14,
	69	K2_SATA_TF_DEVICE_OFFSET = 0x18,
	70	K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
	71	K2_SATA_TF_CTL_OFFSET = 0x20,
1da177e4	72
55cca65e JG	73	/* DMA base */
55cca65e JG	74	K2_SATA_DMA_CMD_OFFSET = 0x30,
1da177e4	75
55cca65e JG	76	/* SCRs base */
	77	K2_SATA_SCR_STATUS_OFFSET = 0x40,
	78	K2_SATA_SCR_ERROR_OFFSET = 0x44,
	79	K2_SATA_SCR_CONTROL_OFFSET = 0x48,
1da177e4	80
55cca65e JG	81	/* Others */
	82	K2_SATA_SICR1_OFFSET = 0x80,
	83	K2_SATA_SICR2_OFFSET = 0x84,
	84	K2_SATA_SIM_OFFSET = 0x88,
1da177e4	85
55cca65e JG	86	/* Port stride */
55cca65e JG	87	K2_SATA_PORT_OFFSET = 0x100,
c10340ac	88
931506d3 AS	89	chip_svw4 = 0,
	90	chip_svw8 = 1,
	91	chip_svw42 = 2, /* bar 3 */
	92	chip_svw43 = 3, /* bar 5 */
c10340ac JG	93	};
c10340ac JG	94
ac19bff2 JG	95	static u8 k2_stat_check_status(struct ata_port *ap);
ac19bff2 JG	96
1da177e4	97
c10340ac JG	98	static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
c10340ac JG	99	{
931506d3 AS	100	u8 cmnd = qc->scsicmd->cmnd[0];
931506d3 AS	101
c10340ac JG	102	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
c10340ac JG	103	return -1; /* ATAPI DMA not supported */
931506d3 AS	104	else {
	105	switch (cmnd) {
	106	case READ_10:
	107	case READ_12:
	108	case READ_16:
	109	case WRITE_10:
	110	case WRITE_12:
	111	case WRITE_16:
	112	return 0;
	113
	114	default:
	115	return -1;
	116	}
c10340ac	117
931506d3	118	}
c10340ac JG	119	}
c10340ac JG	120
82ef04fb TH	121	static int k2_sata_scr_read(struct ata_link *link,
82ef04fb TH	122	unsigned int sc_reg, u32 *val)
1da177e4 LT	123	{
1da177e4 LT	124	if (sc_reg > SCR_CONTROL)
da3dbb17	125	return -EINVAL;
82ef04fb	126	val = readl(link->ap->ioaddr.scr_addr + (sc_reg 4));
da3dbb17	127	return 0;
1da177e4 LT	128	}
	129
	130
82ef04fb TH	131	static int k2_sata_scr_write(struct ata_link *link,
82ef04fb TH	132	unsigned int sc_reg, u32 val)
1da177e4 LT	133	{
1da177e4 LT	134	if (sc_reg > SCR_CONTROL)
da3dbb17	135	return -EINVAL;
82ef04fb	136	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	137	return 0;
1da177e4 LT	138	}
1da177e4 LT	139
b03e66a6 DM	140	static int k2_sata_softreset(struct ata_link *link,
	141	unsigned int *class, unsigned long deadline)
	142	{
	143	u8 dmactl;
	144	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	145
	146	dmactl = readb(mmio + ATA_DMA_CMD);
	147
	148	/* Clear the start bit */
	149	if (dmactl & ATA_DMA_START) {
	150	dmactl &= ~ATA_DMA_START;
	151	writeb(dmactl, mmio + ATA_DMA_CMD);
	152	}
	153
	154	return ata_sff_softreset(link, class, deadline);
	155	}
	156
	157	static int k2_sata_hardreset(struct ata_link *link,
	158	unsigned int *class, unsigned long deadline)
	159	{
	160	u8 dmactl;
	161	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	162
	163	dmactl = readb(mmio + ATA_DMA_CMD);
	164
	165	/* Clear the start bit */
	166	if (dmactl & ATA_DMA_START) {
	167	dmactl &= ~ATA_DMA_START;
	168	writeb(dmactl, mmio + ATA_DMA_CMD);
	169	}
	170
	171	return sata_sff_hardreset(link, class, deadline);
	172	}
1da177e4	173
057ace5e	174	static void k2_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	175	{
	176	struct ata_ioports *ioaddr = &ap->ioaddr;
	177	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	178
	179	if (tf->ctl != ap->last_ctl) {
0d5ff566	180	writeb(tf->ctl, ioaddr->ctl_addr);
1da177e4 LT	181	ap->last_ctl = tf->ctl;
	182	ata_wait_idle(ap);
	183	}
	184	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	185	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	186	ioaddr->feature_addr);
850a9d8a	187	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	188	ioaddr->nsect_addr);
850a9d8a	189	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	190	ioaddr->lbal_addr);
850a9d8a	191	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	192	ioaddr->lbam_addr);
850a9d8a	193	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	194	ioaddr->lbah_addr);
1da177e4	195	} else if (is_addr) {
0d5ff566 TH	196	writew(tf->feature, ioaddr->feature_addr);
	197	writew(tf->nsect, ioaddr->nsect_addr);
	198	writew(tf->lbal, ioaddr->lbal_addr);
	199	writew(tf->lbam, ioaddr->lbam_addr);
	200	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	201	}
	202
	203	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	204	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	205
	206	ata_wait_idle(ap);
	207	}
	208
	209
	210	static void k2_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	211	{
	212	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	213	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	214
ac19bff2	215	tf->command = k2_stat_check_status(ap);
0d5ff566 TH	216	tf->device = readw(ioaddr->device_addr);
	217	feature = readw(ioaddr->error_addr);
	218	nsect = readw(ioaddr->nsect_addr);
	219	lbal = readw(ioaddr->lbal_addr);
	220	lbam = readw(ioaddr->lbam_addr);
	221	lbah = readw(ioaddr->lbah_addr);
ac19bff2 JG	222
	223	tf->feature = feature;
	224	tf->nsect = nsect;
	225	tf->lbal = lbal;
	226	tf->lbam = lbam;
	227	tf->lbah = lbah;
1da177e4 LT	228
1da177e4 LT	229	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	230	tf->hob_feature = feature >> 8;
1da177e4 LT	231	tf->hob_nsect = nsect >> 8;
	232	tf->hob_lbal = lbal >> 8;
	233	tf->hob_lbam = lbam >> 8;
	234	tf->hob_lbah = lbah >> 8;
5796d1c4	235	}
1da177e4 LT	236	}
	237
	238	/**
	239	* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
	240	* @qc: Info associated with this ATA transaction.
	241	*
	242	* LOCKING:
cca3974e	243	* spin_lock_irqsave(host lock)
1da177e4 LT	244	*/
1da177e4 LT	245
5796d1c4	246	static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	247	{
	248	struct ata_port *ap = qc->ap;
	249	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	250	u8 dmactl;
59f99880 JG	251	void __iomem *mmio = ap->ioaddr.bmdma_addr;
59f99880 JG	252
1da177e4 LT	253	/* load PRD table addr. */
1da177e4 LT	254	mb(); /* make sure PRD table writes are visible to controller */
f60d7011	255	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
1da177e4 LT	256
	257	/* specify data direction, triple-check start bit is clear */
	258	dmactl = readb(mmio + ATA_DMA_CMD);
	259	dmactl &= ~(ATA_DMA_WR \| ATA_DMA_START);
	260	if (!rw)
	261	dmactl \|= ATA_DMA_WR;
	262	writeb(dmactl, mmio + ATA_DMA_CMD);
	263
	264	/* issue r/w command if this is not a ATA DMA command*/
	265	if (qc->tf.protocol != ATA_PROT_DMA)
5682ed33	266	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	267	}
	268
	269	/**
	270	* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
	271	* @qc: Info associated with this ATA transaction.
	272	*
	273	* LOCKING:
cca3974e	274	* spin_lock_irqsave(host lock)
1da177e4 LT	275	*/
1da177e4 LT	276
5796d1c4	277	static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	278	{
1da177e4 LT	279	struct ata_port *ap = qc->ap;
59f99880	280	void __iomem *mmio = ap->ioaddr.bmdma_addr;
1da177e4 LT	281	u8 dmactl;
	282
	283	/* start host DMA transaction */
	284	dmactl = readb(mmio + ATA_DMA_CMD);
	285	writeb(dmactl \| ATA_DMA_START, mmio + ATA_DMA_CMD);
ec6add99 PM	286	/* This works around possible data corruption.
	287
	288	On certain SATA controllers that can be seen when the r/w
	289	command is given to the controller before the host DMA is
	290	started.
	291
	292	On a Read command, the controller would initiate the
	293	command to the drive even before it sees the DMA
	294	start. When there are very fast drives connected to the
	295	controller, or when the data request hits in the drive
	296	cache, there is the possibility that the drive returns a
	297	part or all of the requested data to the controller before
	298	the DMA start is issued. In this case, the controller
	299	would become confused as to what to do with the data. In
	300	the worst case when all the data is returned back to the
	301	controller, the controller could hang. In other cases it
	302	could return partial data returning in data
	303	corruption. This problem has been seen in PPC systems and
	304	can also appear on an system with very fast disks, where
	305	the SATA controller is sitting behind a number of bridges,
	306	and hence there is significant latency between the r/w
	307	command and the start command. */
	308	/* issue r/w command if the access is to ATA */
1da177e4	309	if (qc->tf.protocol == ATA_PROT_DMA)
5682ed33	310	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	311	}
1da177e4 LT	312
8a60a071	313
1da177e4 LT	314	static u8 k2_stat_check_status(struct ata_port *ap)
1da177e4 LT	315	{
5796d1c4	316	return readl(ap->ioaddr.status_addr);
1da177e4 LT	317	}
1da177e4 LT	318
3f025677	319	static int k2_sata_show_info(struct seq_file m, struct Scsi_Host shost)
1da177e4 LT	320	{
	321	struct ata_port *ap;
	322	struct device_node *np;
3f025677	323	int index;
1da177e4 LT	324
1da177e4 LT	325	/* Find the ata_port */
35bb94b1	326	ap = ata_shost_to_port(shost);
1da177e4 LT	327	if (ap == NULL)
	328	return 0;
	329
	330	/* Find the OF node for the PCI device proper */
cca3974e	331	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
1da177e4 LT	332	if (np == NULL)
	333	return 0;
	334
	335	/* Match it to a port node */
cca3974e	336	index = (ap == ap->host->ports[0]) ? 0 : 1;
1da177e4	337	for (np = np->child; np != NULL; np = np->sibling) {
40cd3a45	338	const u32 *reg = of_get_property(np, "reg", NULL);
1da177e4 LT	339	if (!reg)
1da177e4 LT	340	continue;
3f025677 AV	341	if (index == *reg) {
3f025677 AV	342	seq_printf(m, "devspec: %s\n", np->full_name);
1da177e4	343	break;
3f025677	344	}
1da177e4	345	}
3f025677	346	return 0;
1da177e4	347	}
1da177e4	348
193515d5	349	static struct scsi_host_template k2_sata_sht = {
68d1d07b	350	ATA_BMDMA_SHT(DRV_NAME),
3f025677	351	.show_info = k2_sata_show_info,
1da177e4 LT	352	};
	353
	354
029cfd6b TH	355	static struct ata_port_operations k2_sata_ops = {
029cfd6b TH	356	.inherits = &ata_bmdma_port_ops,
b03e66a6 DM	357	.softreset = k2_sata_softreset,
b03e66a6 DM	358	.hardreset = k2_sata_hardreset,
5682ed33 TH	359	.sff_tf_load = k2_sata_tf_load,
	360	.sff_tf_read = k2_sata_tf_read,
	361	.sff_check_status = k2_stat_check_status,
c10340ac	362	.check_atapi_dma = k2_sata_check_atapi_dma,
1da177e4 LT	363	.bmdma_setup = k2_bmdma_setup_mmio,
1da177e4 LT	364	.bmdma_start = k2_bmdma_start_mmio,
1da177e4 LT	365	.scr_read = k2_sata_scr_read,
1da177e4 LT	366	.scr_write = k2_sata_scr_write,
1da177e4 LT	367	};
1da177e4 LT	368
4447d351	369	static const struct ata_port_info k2_port_info[] = {
931506d3	370	/* chip_svw4 */
4447d351	371	{
9cbe056f	372	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA,
14bdef98 EIB	373	.pio_mask = ATA_PIO4,
14bdef98 EIB	374	.mwdma_mask = ATA_MWDMA2,
bf6263a8	375	.udma_mask = ATA_UDMA6,
4447d351 TH	376	.port_ops = &k2_sata_ops,
4447d351 TH	377	},
931506d3	378	/* chip_svw8 */
4447d351	379	{
9cbe056f SS	380	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA \|
9cbe056f SS	381	K2_FLAG_SATA_8_PORTS,
14bdef98 EIB	382	.pio_mask = ATA_PIO4,
14bdef98 EIB	383	.mwdma_mask = ATA_MWDMA2,
bf6263a8	384	.udma_mask = ATA_UDMA6,
4447d351 TH	385	.port_ops = &k2_sata_ops,
4447d351 TH	386	},
931506d3 AS	387	/* chip_svw42 */
931506d3 AS	388	{
9cbe056f	389	.flags = ATA_FLAG_SATA \| K2_FLAG_BAR_POS_3,
14bdef98 EIB	390	.pio_mask = ATA_PIO4,
14bdef98 EIB	391	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	392	.udma_mask = ATA_UDMA6,
	393	.port_ops = &k2_sata_ops,
	394	},
	395	/* chip_svw43 */
	396	{
9cbe056f	397	.flags = ATA_FLAG_SATA,
14bdef98 EIB	398	.pio_mask = ATA_PIO4,
14bdef98 EIB	399	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	400	.udma_mask = ATA_UDMA6,
	401	.port_ops = &k2_sata_ops,
	402	},
4447d351 TH	403	};
4447d351 TH	404
0d5ff566	405	static void k2_sata_setup_port(struct ata_ioports port, void __iomem base)
1da177e4 LT	406	{
	407	port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
	408	port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
	409	port->feature_addr =
	410	port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
	411	port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
	412	port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
	413	port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
	414	port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
	415	port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
	416	port->command_addr =
	417	port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
	418	port->altstatus_addr =
	419	port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
	420	port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
	421	port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
	422	}
	423
	424
5796d1c4	425	static int k2_sata_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4	426	{
4447d351 TH	427	const struct ata_port_info *ppi[] =
	428	{ &k2_port_info[ent->driver_data], NULL };
	429	struct ata_host *host;
ea6ba10b	430	void __iomem *mmio_base;
931506d3	431	int n_ports, i, rc, bar_pos;
1da177e4	432
06296a1e	433	ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4	434
4447d351 TH	435	/* allocate host */
	436	n_ports = 4;
	437	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
	438	n_ports = 8;
	439
	440	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	441	if (!host)
	442	return -ENOMEM;
	443
931506d3 AS	444	bar_pos = 5;
	445	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
	446	bar_pos = 3;
1da177e4 LT	447	/*
	448	* If this driver happens to only be useful on Apple's K2, then
	449	* we should check that here as it has a normal Serverworks ID
	450	*/
24dc5f33	451	rc = pcim_enable_device(pdev);
1da177e4 LT	452	if (rc)
1da177e4 LT	453	return rc;
4447d351	454
1da177e4 LT	455	/*
	456	* Check if we have resources mapped at all (second function may
	457	* have been disabled by firmware)
	458	*/
931506d3 AS	459	if (pci_resource_len(pdev, bar_pos) == 0) {
	460	/* In IDE mode we need to pin the device to ensure that
	461	pcim_release does not clear the busmaster bit in config
	462	space, clearing causes busmaster DMA to fail on
	463	ports 3 & 4 */
	464	pcim_pin_device(pdev);
1da177e4	465	return -ENODEV;
931506d3	466	}
1da177e4	467
0d5ff566	468	/* Request and iomap PCI regions */
931506d3	469	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
0d5ff566	470	if (rc == -EBUSY)
24dc5f33	471	pcim_pin_device(pdev);
0d5ff566	472	if (rc)
24dc5f33	473	return rc;
4447d351	474	host->iomap = pcim_iomap_table(pdev);
931506d3	475	mmio_base = host->iomap[bar_pos];
4447d351 TH	476
	477	/* different controllers have different number of ports - currently 4 or 8 */
	478	/* All ports are on the same function. Multi-function device is no
	479	* longer available. This should not be seen in any system. */
cbcdd875 TH	480	for (i = 0; i < host->n_ports; i++) {
	481	struct ata_port *ap = host->ports[i];
	482	unsigned int offset = i * K2_SATA_PORT_OFFSET;
	483
	484	k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	485
	486	ata_port_pbar_desc(ap, 5, -1, "mmio");
	487	ata_port_pbar_desc(ap, 5, offset, "port");
	488	}
1da177e4	489
c54c719b	490	rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
1da177e4	491	if (rc)
24dc5f33	492	return rc;
c54c719b	493	rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
1da177e4	494	if (rc)
24dc5f33	495	return rc;
1da177e4	496
0d5ff566 TH	497	/* Clear a magic bit in SCR1 according to Darwin, those help
	498	* some funky seagate drives (though so far, those were already
	499	* set by the firmware on the machines I had access to)
	500	*/
	501	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	502	mmio_base + K2_SATA_SICR1_OFFSET);
	503
	504	/* Clear SATA error & interrupts we don't use */
	505	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	506	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
1da177e4 LT	507
1da177e4 LT	508	pci_set_master(pdev);
c3b28894	509	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382	510	IRQF_SHARED, &k2_sata_sht);
1da177e4 LT	511	}
1da177e4 LT	512
60bf09a3 NS	513	/* 0x240 is device ID for Apple K2 device
	514	* 0x241 is device ID for Serverworks Frodo4
	515	* 0x242 is device ID for Serverworks Frodo8
	516	* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
	517	* controller
	518	* */
3b7d697d	519	static const struct pci_device_id k2_sata_pci_tbl[] = {
931506d3	520	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
aeb74914 JG	521	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
aeb74914 JG	522	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
931506d3 AS	523	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	524	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	525	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	526	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
2d2744fc	527
1da177e4 LT	528	{ }
	529	};
	530
1da177e4 LT	531	static struct pci_driver k2_sata_pci_driver = {
	532	.name = DRV_NAME,
	533	.id_table = k2_sata_pci_tbl,
	534	.probe = k2_sata_init_one,
	535	.remove = ata_pci_remove_one,
	536	};
	537
2fc75da0	538	module_pci_driver(k2_sata_pci_driver);
1da177e4	539
1da177e4 LT	540	MODULE_AUTHOR("Benjamin Herrenschmidt");
	541	MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
	542	MODULE_LICENSE("GPL");
	543	MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
	544	MODULE_VERSION(DRV_VERSION);