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1da177e4 LT |
1 | /* |
2 | * sata_svw.c - ServerWorks / Apple K2 SATA | |
3 | * | |
4 | * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and | |
5 | * Jeff Garzik <jgarzik@pobox.com> | |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
10 | * | |
11 | * Bits from Jeff Garzik, Copyright RedHat, Inc. | |
12 | * | |
13 | * This driver probably works with non-Apple versions of the | |
14 | * Broadcom chipset... | |
15 | * | |
af36d7f0 JG |
16 | * |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License as published by | |
19 | * the Free Software Foundation; either version 2, or (at your option) | |
20 | * any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; see the file COPYING. If not, write to | |
29 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | * | |
32 | * libata documentation is available via 'make {ps|pdf}docs', | |
33 | * as Documentation/DocBook/libata.* | |
34 | * | |
35 | * Hardware documentation available under NDA. | |
1da177e4 LT |
36 | * |
37 | */ | |
38 | ||
1da177e4 LT |
39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/blkdev.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/interrupt.h> | |
a9524a76 | 46 | #include <linux/device.h> |
1da177e4 LT |
47 | #include <scsi/scsi_host.h> |
48 | #include <linux/libata.h> | |
49 | ||
50 | #ifdef CONFIG_PPC_OF | |
51 | #include <asm/prom.h> | |
52 | #include <asm/pci-bridge.h> | |
53 | #endif /* CONFIG_PPC_OF */ | |
54 | ||
55 | #define DRV_NAME "sata_svw" | |
cb48cab7 | 56 | #define DRV_VERSION "2.1" |
1da177e4 | 57 | |
55cca65e | 58 | enum { |
c10340ac JG |
59 | K2_FLAG_NO_ATAPI_DMA = (1 << 29), |
60 | ||
55cca65e JG |
61 | /* Taskfile registers offsets */ |
62 | K2_SATA_TF_CMD_OFFSET = 0x00, | |
63 | K2_SATA_TF_DATA_OFFSET = 0x00, | |
64 | K2_SATA_TF_ERROR_OFFSET = 0x04, | |
65 | K2_SATA_TF_NSECT_OFFSET = 0x08, | |
66 | K2_SATA_TF_LBAL_OFFSET = 0x0c, | |
67 | K2_SATA_TF_LBAM_OFFSET = 0x10, | |
68 | K2_SATA_TF_LBAH_OFFSET = 0x14, | |
69 | K2_SATA_TF_DEVICE_OFFSET = 0x18, | |
70 | K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, | |
71 | K2_SATA_TF_CTL_OFFSET = 0x20, | |
1da177e4 | 72 | |
55cca65e JG |
73 | /* DMA base */ |
74 | K2_SATA_DMA_CMD_OFFSET = 0x30, | |
1da177e4 | 75 | |
55cca65e JG |
76 | /* SCRs base */ |
77 | K2_SATA_SCR_STATUS_OFFSET = 0x40, | |
78 | K2_SATA_SCR_ERROR_OFFSET = 0x44, | |
79 | K2_SATA_SCR_CONTROL_OFFSET = 0x48, | |
1da177e4 | 80 | |
55cca65e JG |
81 | /* Others */ |
82 | K2_SATA_SICR1_OFFSET = 0x80, | |
83 | K2_SATA_SICR2_OFFSET = 0x84, | |
84 | K2_SATA_SIM_OFFSET = 0x88, | |
1da177e4 | 85 | |
55cca65e JG |
86 | /* Port stride */ |
87 | K2_SATA_PORT_OFFSET = 0x100, | |
c10340ac JG |
88 | |
89 | board_svw4 = 0, | |
90 | board_svw8 = 1, | |
91 | }; | |
92 | ||
93 | static const struct k2_board_info { | |
94 | unsigned int n_ports; | |
95 | unsigned long port_flags; | |
96 | } k2_board_info[] = { | |
97 | /* board_svw4 */ | |
98 | { 4, K2_FLAG_NO_ATAPI_DMA }, | |
99 | ||
100 | /* board_svw8 */ | |
101 | { 8, K2_FLAG_NO_ATAPI_DMA }, | |
55cca65e | 102 | }; |
1da177e4 | 103 | |
ac19bff2 JG |
104 | static u8 k2_stat_check_status(struct ata_port *ap); |
105 | ||
1da177e4 | 106 | |
c10340ac JG |
107 | static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
108 | { | |
109 | if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA) | |
110 | return -1; /* ATAPI DMA not supported */ | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
1da177e4 LT |
115 | static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
116 | { | |
117 | if (sc_reg > SCR_CONTROL) | |
118 | return 0xffffffffU; | |
92ccc5f7 | 119 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
120 | } |
121 | ||
122 | ||
123 | static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
124 | u32 val) | |
125 | { | |
126 | if (sc_reg > SCR_CONTROL) | |
127 | return; | |
92ccc5f7 | 128 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
129 | } |
130 | ||
131 | ||
057ace5e | 132 | static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
133 | { |
134 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
135 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
136 | ||
137 | if (tf->ctl != ap->last_ctl) { | |
0d5ff566 | 138 | writeb(tf->ctl, ioaddr->ctl_addr); |
1da177e4 LT |
139 | ap->last_ctl = tf->ctl; |
140 | ata_wait_idle(ap); | |
141 | } | |
142 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
850a9d8a | 143 | writew(tf->feature | (((u16)tf->hob_feature) << 8), |
0d5ff566 | 144 | ioaddr->feature_addr); |
850a9d8a | 145 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), |
0d5ff566 | 146 | ioaddr->nsect_addr); |
850a9d8a | 147 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), |
0d5ff566 | 148 | ioaddr->lbal_addr); |
850a9d8a | 149 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), |
0d5ff566 | 150 | ioaddr->lbam_addr); |
850a9d8a | 151 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), |
0d5ff566 | 152 | ioaddr->lbah_addr); |
1da177e4 | 153 | } else if (is_addr) { |
0d5ff566 TH |
154 | writew(tf->feature, ioaddr->feature_addr); |
155 | writew(tf->nsect, ioaddr->nsect_addr); | |
156 | writew(tf->lbal, ioaddr->lbal_addr); | |
157 | writew(tf->lbam, ioaddr->lbam_addr); | |
158 | writew(tf->lbah, ioaddr->lbah_addr); | |
1da177e4 LT |
159 | } |
160 | ||
161 | if (tf->flags & ATA_TFLAG_DEVICE) | |
0d5ff566 | 162 | writeb(tf->device, ioaddr->device_addr); |
1da177e4 LT |
163 | |
164 | ata_wait_idle(ap); | |
165 | } | |
166 | ||
167 | ||
168 | static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
169 | { | |
170 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
ac19bff2 | 171 | u16 nsect, lbal, lbam, lbah, feature; |
1da177e4 | 172 | |
ac19bff2 | 173 | tf->command = k2_stat_check_status(ap); |
0d5ff566 TH |
174 | tf->device = readw(ioaddr->device_addr); |
175 | feature = readw(ioaddr->error_addr); | |
176 | nsect = readw(ioaddr->nsect_addr); | |
177 | lbal = readw(ioaddr->lbal_addr); | |
178 | lbam = readw(ioaddr->lbam_addr); | |
179 | lbah = readw(ioaddr->lbah_addr); | |
ac19bff2 JG |
180 | |
181 | tf->feature = feature; | |
182 | tf->nsect = nsect; | |
183 | tf->lbal = lbal; | |
184 | tf->lbam = lbam; | |
185 | tf->lbah = lbah; | |
1da177e4 LT |
186 | |
187 | if (tf->flags & ATA_TFLAG_LBA48) { | |
ac19bff2 | 188 | tf->hob_feature = feature >> 8; |
1da177e4 LT |
189 | tf->hob_nsect = nsect >> 8; |
190 | tf->hob_lbal = lbal >> 8; | |
191 | tf->hob_lbam = lbam >> 8; | |
192 | tf->hob_lbah = lbah >> 8; | |
193 | } | |
194 | } | |
195 | ||
196 | /** | |
197 | * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) | |
198 | * @qc: Info associated with this ATA transaction. | |
199 | * | |
200 | * LOCKING: | |
cca3974e | 201 | * spin_lock_irqsave(host lock) |
1da177e4 LT |
202 | */ |
203 | ||
204 | static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc) | |
205 | { | |
206 | struct ata_port *ap = qc->ap; | |
207 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
208 | u8 dmactl; | |
04b1add1 | 209 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; |
1da177e4 LT |
210 | /* load PRD table addr. */ |
211 | mb(); /* make sure PRD table writes are visible to controller */ | |
212 | writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); | |
213 | ||
214 | /* specify data direction, triple-check start bit is clear */ | |
215 | dmactl = readb(mmio + ATA_DMA_CMD); | |
216 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
217 | if (!rw) | |
218 | dmactl |= ATA_DMA_WR; | |
219 | writeb(dmactl, mmio + ATA_DMA_CMD); | |
220 | ||
221 | /* issue r/w command if this is not a ATA DMA command*/ | |
222 | if (qc->tf.protocol != ATA_PROT_DMA) | |
223 | ap->ops->exec_command(ap, &qc->tf); | |
224 | } | |
225 | ||
226 | /** | |
227 | * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) | |
228 | * @qc: Info associated with this ATA transaction. | |
229 | * | |
230 | * LOCKING: | |
cca3974e | 231 | * spin_lock_irqsave(host lock) |
1da177e4 LT |
232 | */ |
233 | ||
234 | static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc) | |
235 | { | |
236 | struct ata_port *ap = qc->ap; | |
04b1add1 | 237 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; |
1da177e4 LT |
238 | u8 dmactl; |
239 | ||
240 | /* start host DMA transaction */ | |
241 | dmactl = readb(mmio + ATA_DMA_CMD); | |
242 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); | |
8a60a071 JG |
243 | /* There is a race condition in certain SATA controllers that can |
244 | be seen when the r/w command is given to the controller before the | |
1da177e4 LT |
245 | host DMA is started. On a Read command, the controller would initiate |
246 | the command to the drive even before it sees the DMA start. When there | |
8a60a071 | 247 | are very fast drives connected to the controller, or when the data request |
1da177e4 LT |
248 | hits in the drive cache, there is the possibility that the drive returns a part |
249 | or all of the requested data to the controller before the DMA start is issued. | |
250 | In this case, the controller would become confused as to what to do with the data. | |
251 | In the worst case when all the data is returned back to the controller, the | |
252 | controller could hang. In other cases it could return partial data returning | |
253 | in data corruption. This problem has been seen in PPC systems and can also appear | |
8a60a071 | 254 | on an system with very fast disks, where the SATA controller is sitting behind a |
1da177e4 LT |
255 | number of bridges, and hence there is significant latency between the r/w command |
256 | and the start command. */ | |
257 | /* issue r/w command if the access is to ATA*/ | |
258 | if (qc->tf.protocol == ATA_PROT_DMA) | |
259 | ap->ops->exec_command(ap, &qc->tf); | |
260 | } | |
261 | ||
8a60a071 | 262 | |
1da177e4 LT |
263 | static u8 k2_stat_check_status(struct ata_port *ap) |
264 | { | |
92ccc5f7 | 265 | return readl((void __iomem *) ap->ioaddr.status_addr); |
1da177e4 LT |
266 | } |
267 | ||
268 | #ifdef CONFIG_PPC_OF | |
269 | /* | |
270 | * k2_sata_proc_info | |
271 | * inout : decides on the direction of the dataflow and the meaning of the | |
272 | * variables | |
273 | * buffer: If inout==FALSE data is being written to it else read from it | |
274 | * *start: If inout==FALSE start of the valid data in the buffer | |
275 | * offset: If inout==FALSE offset from the beginning of the imaginary file | |
276 | * from which we start writing into the buffer | |
277 | * length: If inout==FALSE max number of bytes to be written into the buffer | |
278 | * else number of bytes in the buffer | |
279 | */ | |
280 | static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start, | |
281 | off_t offset, int count, int inout) | |
282 | { | |
283 | struct ata_port *ap; | |
284 | struct device_node *np; | |
285 | int len, index; | |
286 | ||
287 | /* Find the ata_port */ | |
35bb94b1 | 288 | ap = ata_shost_to_port(shost); |
1da177e4 LT |
289 | if (ap == NULL) |
290 | return 0; | |
291 | ||
292 | /* Find the OF node for the PCI device proper */ | |
cca3974e | 293 | np = pci_device_to_OF_node(to_pci_dev(ap->host->dev)); |
1da177e4 LT |
294 | if (np == NULL) |
295 | return 0; | |
296 | ||
297 | /* Match it to a port node */ | |
cca3974e | 298 | index = (ap == ap->host->ports[0]) ? 0 : 1; |
1da177e4 | 299 | for (np = np->child; np != NULL; np = np->sibling) { |
af5f92d8 | 300 | const u32 *reg = get_property(np, "reg", NULL); |
1da177e4 LT |
301 | if (!reg) |
302 | continue; | |
303 | if (index == *reg) | |
304 | break; | |
305 | } | |
306 | if (np == NULL) | |
307 | return 0; | |
308 | ||
309 | len = sprintf(page, "devspec: %s\n", np->full_name); | |
310 | ||
311 | return len; | |
312 | } | |
313 | #endif /* CONFIG_PPC_OF */ | |
314 | ||
315 | ||
193515d5 | 316 | static struct scsi_host_template k2_sata_sht = { |
1da177e4 LT |
317 | .module = THIS_MODULE, |
318 | .name = DRV_NAME, | |
319 | .ioctl = ata_scsi_ioctl, | |
320 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
321 | .can_queue = ATA_DEF_QUEUE, |
322 | .this_id = ATA_SHT_THIS_ID, | |
323 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
324 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
325 | .emulated = ATA_SHT_EMULATED, | |
326 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
327 | .proc_name = DRV_NAME, | |
328 | .dma_boundary = ATA_DMA_BOUNDARY, | |
329 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 330 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 LT |
331 | #ifdef CONFIG_PPC_OF |
332 | .proc_info = k2_sata_proc_info, | |
333 | #endif | |
334 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
335 | }; |
336 | ||
337 | ||
057ace5e | 338 | static const struct ata_port_operations k2_sata_ops = { |
1da177e4 LT |
339 | .port_disable = ata_port_disable, |
340 | .tf_load = k2_sata_tf_load, | |
341 | .tf_read = k2_sata_tf_read, | |
342 | .check_status = k2_stat_check_status, | |
343 | .exec_command = ata_exec_command, | |
344 | .dev_select = ata_std_dev_select, | |
c10340ac | 345 | .check_atapi_dma = k2_sata_check_atapi_dma, |
1da177e4 LT |
346 | .bmdma_setup = k2_bmdma_setup_mmio, |
347 | .bmdma_start = k2_bmdma_start_mmio, | |
348 | .bmdma_stop = ata_bmdma_stop, | |
349 | .bmdma_status = ata_bmdma_status, | |
350 | .qc_prep = ata_qc_prep, | |
351 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 352 | .data_xfer = ata_data_xfer, |
d7a80dad TH |
353 | .freeze = ata_bmdma_freeze, |
354 | .thaw = ata_bmdma_thaw, | |
355 | .error_handler = ata_bmdma_error_handler, | |
356 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
1da177e4 LT |
357 | .irq_handler = ata_interrupt, |
358 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
359 | .irq_on = ata_irq_on, |
360 | .irq_ack = ata_irq_ack, | |
1da177e4 LT |
361 | .scr_read = k2_sata_scr_read, |
362 | .scr_write = k2_sata_scr_write, | |
363 | .port_start = ata_port_start, | |
1da177e4 LT |
364 | }; |
365 | ||
0d5ff566 | 366 | static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) |
1da177e4 LT |
367 | { |
368 | port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; | |
369 | port->data_addr = base + K2_SATA_TF_DATA_OFFSET; | |
370 | port->feature_addr = | |
371 | port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; | |
372 | port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; | |
373 | port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; | |
374 | port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; | |
375 | port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; | |
376 | port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; | |
377 | port->command_addr = | |
378 | port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; | |
379 | port->altstatus_addr = | |
380 | port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; | |
381 | port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; | |
382 | port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; | |
383 | } | |
384 | ||
385 | ||
386 | static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
387 | { | |
388 | static int printed_version; | |
24dc5f33 TH |
389 | struct device *dev = &pdev->dev; |
390 | struct ata_probe_ent *probe_ent; | |
ea6ba10b | 391 | void __iomem *mmio_base; |
c10340ac JG |
392 | const struct k2_board_info *board_info = |
393 | &k2_board_info[ent->driver_data]; | |
1da177e4 | 394 | int rc; |
60bf09a3 | 395 | int i; |
1da177e4 LT |
396 | |
397 | if (!printed_version++) | |
a9524a76 | 398 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
399 | |
400 | /* | |
401 | * If this driver happens to only be useful on Apple's K2, then | |
402 | * we should check that here as it has a normal Serverworks ID | |
403 | */ | |
24dc5f33 | 404 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
405 | if (rc) |
406 | return rc; | |
407 | /* | |
408 | * Check if we have resources mapped at all (second function may | |
409 | * have been disabled by firmware) | |
410 | */ | |
411 | if (pci_resource_len(pdev, 5) == 0) | |
412 | return -ENODEV; | |
413 | ||
0d5ff566 TH |
414 | /* Request and iomap PCI regions */ |
415 | rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); | |
416 | if (rc == -EBUSY) | |
24dc5f33 | 417 | pcim_pin_device(pdev); |
0d5ff566 | 418 | if (rc) |
24dc5f33 | 419 | return rc; |
1da177e4 LT |
420 | |
421 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
422 | if (rc) | |
24dc5f33 | 423 | return rc; |
1da177e4 LT |
424 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
425 | if (rc) | |
24dc5f33 | 426 | return rc; |
1da177e4 | 427 | |
24dc5f33 TH |
428 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); |
429 | if (probe_ent == NULL) | |
430 | return -ENOMEM; | |
1da177e4 | 431 | |
1da177e4 LT |
432 | probe_ent->dev = pci_dev_to_dev(pdev); |
433 | INIT_LIST_HEAD(&probe_ent->node); | |
434 | ||
1da177e4 | 435 | probe_ent->sht = &k2_sata_sht; |
cca3974e | 436 | probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
c10340ac | 437 | ATA_FLAG_MMIO | board_info->port_flags; |
1da177e4 LT |
438 | probe_ent->port_ops = &k2_sata_ops; |
439 | probe_ent->n_ports = 4; | |
440 | probe_ent->irq = pdev->irq; | |
1d6f359a | 441 | probe_ent->irq_flags = IRQF_SHARED; |
0d5ff566 | 442 | probe_ent->iomap = pcim_iomap_table(pdev); |
1da177e4 LT |
443 | |
444 | /* We don't care much about the PIO/UDMA masks, but the core won't like us | |
445 | * if we don't fill these | |
446 | */ | |
447 | probe_ent->pio_mask = 0x1f; | |
448 | probe_ent->mwdma_mask = 0x7; | |
449 | probe_ent->udma_mask = 0x7f; | |
450 | ||
0d5ff566 TH |
451 | mmio_base = probe_ent->iomap[5]; |
452 | ||
60bf09a3 NS |
453 | /* different controllers have different number of ports - currently 4 or 8 */ |
454 | /* All ports are on the same function. Multi-function device is no | |
455 | * longer available. This should not be seen in any system. */ | |
c10340ac | 456 | for (i = 0; i < board_info->n_ports; i++) |
0d5ff566 TH |
457 | k2_sata_setup_port(&probe_ent->port[i], |
458 | mmio_base + i * K2_SATA_PORT_OFFSET); | |
459 | ||
460 | /* Clear a magic bit in SCR1 according to Darwin, those help | |
461 | * some funky seagate drives (though so far, those were already | |
462 | * set by the firmware on the machines I had access to) | |
463 | */ | |
464 | writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, | |
465 | mmio_base + K2_SATA_SICR1_OFFSET); | |
466 | ||
467 | /* Clear SATA error & interrupts we don't use */ | |
468 | writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); | |
469 | writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); | |
1da177e4 LT |
470 | |
471 | pci_set_master(pdev); | |
472 | ||
24dc5f33 TH |
473 | if (!ata_device_add(probe_ent)) |
474 | return -ENODEV; | |
1da177e4 | 475 | |
24dc5f33 | 476 | devm_kfree(dev, probe_ent); |
1da177e4 | 477 | return 0; |
1da177e4 LT |
478 | } |
479 | ||
60bf09a3 NS |
480 | /* 0x240 is device ID for Apple K2 device |
481 | * 0x241 is device ID for Serverworks Frodo4 | |
482 | * 0x242 is device ID for Serverworks Frodo8 | |
483 | * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA | |
484 | * controller | |
485 | * */ | |
3b7d697d | 486 | static const struct pci_device_id k2_sata_pci_tbl[] = { |
c10340ac JG |
487 | { PCI_VDEVICE(SERVERWORKS, 0x0240), board_svw4 }, |
488 | { PCI_VDEVICE(SERVERWORKS, 0x0241), board_svw4 }, | |
489 | { PCI_VDEVICE(SERVERWORKS, 0x0242), board_svw8 }, | |
490 | { PCI_VDEVICE(SERVERWORKS, 0x024a), board_svw4 }, | |
491 | { PCI_VDEVICE(SERVERWORKS, 0x024b), board_svw4 }, | |
2d2744fc | 492 | |
1da177e4 LT |
493 | { } |
494 | }; | |
495 | ||
1da177e4 LT |
496 | static struct pci_driver k2_sata_pci_driver = { |
497 | .name = DRV_NAME, | |
498 | .id_table = k2_sata_pci_tbl, | |
499 | .probe = k2_sata_init_one, | |
500 | .remove = ata_pci_remove_one, | |
501 | }; | |
502 | ||
1da177e4 LT |
503 | static int __init k2_sata_init(void) |
504 | { | |
b7887196 | 505 | return pci_register_driver(&k2_sata_pci_driver); |
1da177e4 LT |
506 | } |
507 | ||
1da177e4 LT |
508 | static void __exit k2_sata_exit(void) |
509 | { | |
510 | pci_unregister_driver(&k2_sata_pci_driver); | |
511 | } | |
512 | ||
1da177e4 LT |
513 | MODULE_AUTHOR("Benjamin Herrenschmidt"); |
514 | MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); | |
515 | MODULE_LICENSE("GPL"); | |
516 | MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); | |
517 | MODULE_VERSION(DRV_VERSION); | |
518 | ||
519 | module_init(k2_sata_init); | |
520 | module_exit(k2_sata_exit); |