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4782ac80 JZ |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. | |
3 | * Author: Jason Jin<Jason.jin@freescale.com> | |
4 | * Zhang Wei<wei.zhang@freescale.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | * | |
24 | * with the reference on libata and ahci drvier in kernel | |
25 | * | |
26 | */ | |
27 | #include <common.h> | |
28 | ||
4782ac80 JZ |
29 | #include <command.h> |
30 | #include <pci.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/errno.h> | |
33 | #include <asm/io.h> | |
34 | #include <malloc.h> | |
35 | #include <scsi.h> | |
36 | #include <ata.h> | |
37 | #include <linux/ctype.h> | |
38 | #include <ahci.h> | |
39 | ||
40 | struct ahci_probe_ent *probe_ent = NULL; | |
41 | hd_driveid_t *ataid[AHCI_MAX_PORTS]; | |
42 | ||
4a7cc0f2 JL |
43 | #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) |
44 | ||
4782ac80 JZ |
45 | |
46 | static inline u32 ahci_port_base(u32 base, u32 port) | |
47 | { | |
48 | return base + 0x100 + (port * 0x80); | |
49 | } | |
50 | ||
51 | ||
52 | static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, | |
53 | unsigned int port_idx) | |
54 | { | |
55 | base = ahci_port_base(base, port_idx); | |
56 | ||
4a7cc0f2 JL |
57 | port->cmd_addr = base; |
58 | port->scr_addr = base + PORT_SCR; | |
4782ac80 JZ |
59 | } |
60 | ||
61 | ||
62 | #define msleep(a) udelay(a * 1000) | |
63 | #define ssleep(a) msleep(a * 1000) | |
4a7cc0f2 JL |
64 | |
65 | static int waiting_for_cmd_completed(volatile u8 *offset, | |
66 | int timeout_msec, | |
67 | u32 sign) | |
4782ac80 JZ |
68 | { |
69 | int i; | |
70 | u32 status; | |
4a7cc0f2 JL |
71 | |
72 | for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) | |
4782ac80 JZ |
73 | msleep(1); |
74 | ||
4a7cc0f2 | 75 | return (i < timeout_msec) ? 0 : -1; |
4782ac80 JZ |
76 | } |
77 | ||
78 | ||
79 | static int ahci_host_init(struct ahci_probe_ent *probe_ent) | |
80 | { | |
81 | pci_dev_t pdev = probe_ent->dev; | |
82 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; | |
83 | u32 tmp, cap_save; | |
84 | u16 tmp16; | |
85 | int i, j; | |
4a7cc0f2 | 86 | volatile u8 *port_mmio; |
4782ac80 JZ |
87 | unsigned short vendor; |
88 | ||
89 | cap_save = readl(mmio + HOST_CAP); | |
4a7cc0f2 | 90 | cap_save &= ((1 << 28) | (1 << 17)); |
4782ac80 JZ |
91 | cap_save |= (1 << 27); |
92 | ||
93 | /* global controller reset */ | |
94 | tmp = readl(mmio + HOST_CTL); | |
95 | if ((tmp & HOST_RESET) == 0) | |
96 | writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); | |
97 | ||
98 | /* reset must complete within 1 second, or | |
99 | * the hardware should be considered fried. | |
100 | */ | |
101 | ssleep(1); | |
102 | ||
103 | tmp = readl(mmio + HOST_CTL); | |
104 | if (tmp & HOST_RESET) { | |
105 | debug("controller reset failed (0x%x)\n", tmp); | |
106 | return -1; | |
107 | } | |
108 | ||
109 | writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); | |
110 | writel(cap_save, mmio + HOST_CAP); | |
111 | writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); | |
112 | ||
113 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); | |
114 | ||
115 | if (vendor == PCI_VENDOR_ID_INTEL) { | |
116 | u16 tmp16; | |
117 | pci_read_config_word(pdev, 0x92, &tmp16); | |
118 | tmp16 |= 0xf; | |
119 | pci_write_config_word(pdev, 0x92, tmp16); | |
120 | } | |
121 | ||
122 | probe_ent->cap = readl(mmio + HOST_CAP); | |
123 | probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); | |
124 | probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; | |
125 | ||
126 | debug("cap 0x%x port_map 0x%x n_ports %d\n", | |
4a7cc0f2 | 127 | probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); |
4782ac80 JZ |
128 | |
129 | for (i = 0; i < probe_ent->n_ports; i++) { | |
4a7cc0f2 JL |
130 | probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); |
131 | port_mmio = (u8 *) probe_ent->port[i].port_mmio; | |
132 | ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); | |
4782ac80 JZ |
133 | |
134 | /* make sure port is not active */ | |
135 | tmp = readl(port_mmio + PORT_CMD); | |
136 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
137 | PORT_CMD_FIS_RX | PORT_CMD_START)) { | |
138 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
139 | PORT_CMD_FIS_RX | PORT_CMD_START); | |
140 | writel_with_flush(tmp, port_mmio + PORT_CMD); | |
141 | ||
142 | /* spec says 500 msecs for each bit, so | |
143 | * this is slightly incorrect. | |
144 | */ | |
145 | msleep(500); | |
146 | } | |
147 | ||
148 | writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); | |
149 | ||
150 | j = 0; | |
151 | while (j < 100) { | |
152 | msleep(10); | |
153 | tmp = readl(port_mmio + PORT_SCR_STAT); | |
154 | if ((tmp & 0xf) == 0x3) | |
155 | break; | |
156 | j++; | |
157 | } | |
158 | ||
159 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
160 | debug("PORT_SCR_ERR 0x%x\n", tmp); | |
161 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
162 | ||
163 | /* ack any pending irq events for this port */ | |
164 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
165 | debug("PORT_IRQ_STAT 0x%x\n", tmp); | |
166 | if (tmp) | |
167 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
168 | ||
169 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
170 | ||
171 | /* set irq mask (enables interrupts) */ | |
172 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
173 | ||
4a7cc0f2 | 174 | /*register linkup ports */ |
4782ac80 | 175 | tmp = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
176 | debug("Port %d status: 0x%x\n", i, tmp); |
177 | if ((tmp & 0xf) == 0x03) | |
178 | probe_ent->link_port_map |= (0x01 << i); | |
4782ac80 JZ |
179 | } |
180 | ||
181 | tmp = readl(mmio + HOST_CTL); | |
182 | debug("HOST_CTL 0x%x\n", tmp); | |
183 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
184 | tmp = readl(mmio + HOST_CTL); | |
185 | debug("HOST_CTL 0x%x\n", tmp); | |
186 | ||
187 | pci_read_config_word(pdev, PCI_COMMAND, &tmp16); | |
188 | tmp |= PCI_COMMAND_MASTER; | |
189 | pci_write_config_word(pdev, PCI_COMMAND, tmp16); | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
194 | ||
195 | static void ahci_print_info(struct ahci_probe_ent *probe_ent) | |
196 | { | |
197 | pci_dev_t pdev = probe_ent->dev; | |
4a7cc0f2 | 198 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
4782ac80 JZ |
199 | u32 vers, cap, impl, speed; |
200 | const char *speed_s; | |
201 | u16 cc; | |
202 | const char *scc_s; | |
203 | ||
204 | vers = readl(mmio + HOST_VERSION); | |
205 | cap = probe_ent->cap; | |
206 | impl = probe_ent->port_map; | |
207 | ||
208 | speed = (cap >> 20) & 0xf; | |
209 | if (speed == 1) | |
210 | speed_s = "1.5"; | |
211 | else if (speed == 2) | |
212 | speed_s = "3"; | |
213 | else | |
214 | speed_s = "?"; | |
215 | ||
216 | pci_read_config_word(pdev, 0x0a, &cc); | |
217 | if (cc == 0x0101) | |
218 | scc_s = "IDE"; | |
219 | else if (cc == 0x0106) | |
220 | scc_s = "SATA"; | |
221 | else if (cc == 0x0104) | |
222 | scc_s = "RAID"; | |
223 | else | |
224 | scc_s = "unknown"; | |
225 | ||
4a7cc0f2 JL |
226 | printf("AHCI %02x%02x.%02x%02x " |
227 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", | |
228 | (vers >> 24) & 0xff, | |
229 | (vers >> 16) & 0xff, | |
230 | (vers >> 8) & 0xff, | |
231 | vers & 0xff, | |
232 | ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); | |
4782ac80 JZ |
233 | |
234 | printf("flags: " | |
4a7cc0f2 JL |
235 | "%s%s%s%s%s%s" |
236 | "%s%s%s%s%s%s%s\n", | |
237 | cap & (1 << 31) ? "64bit " : "", | |
238 | cap & (1 << 30) ? "ncq " : "", | |
239 | cap & (1 << 28) ? "ilck " : "", | |
240 | cap & (1 << 27) ? "stag " : "", | |
241 | cap & (1 << 26) ? "pm " : "", | |
242 | cap & (1 << 25) ? "led " : "", | |
243 | cap & (1 << 24) ? "clo " : "", | |
244 | cap & (1 << 19) ? "nz " : "", | |
245 | cap & (1 << 18) ? "only " : "", | |
246 | cap & (1 << 17) ? "pmp " : "", | |
247 | cap & (1 << 15) ? "pio " : "", | |
248 | cap & (1 << 14) ? "slum " : "", | |
249 | cap & (1 << 13) ? "part " : ""); | |
4782ac80 JZ |
250 | } |
251 | ||
4a7cc0f2 | 252 | static int ahci_init_one(pci_dev_t pdev) |
4782ac80 | 253 | { |
63cec581 ES |
254 | u32 iobase; |
255 | u16 vendor; | |
4782ac80 JZ |
256 | int rc; |
257 | ||
4a7cc0f2 | 258 | memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); |
4782ac80 | 259 | |
594e7983 ES |
260 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
261 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); | |
4782ac80 JZ |
262 | probe_ent->dev = pdev; |
263 | ||
264 | pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); | |
265 | iobase &= ~0xf; | |
266 | ||
4a7cc0f2 JL |
267 | probe_ent->host_flags = ATA_FLAG_SATA |
268 | | ATA_FLAG_NO_LEGACY | |
269 | | ATA_FLAG_MMIO | |
270 | | ATA_FLAG_PIO_DMA | |
271 | | ATA_FLAG_NO_ATAPI; | |
272 | probe_ent->pio_mask = 0x1f; | |
273 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
4782ac80 | 274 | |
4a7cc0f2 | 275 | probe_ent->mmio_base = iobase; |
4782ac80 JZ |
276 | |
277 | /* Take from kernel: | |
278 | * JMicron-specific fixup: | |
279 | * make sure we're in AHCI mode | |
280 | */ | |
281 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); | |
4a7cc0f2 | 282 | if (vendor == 0x197b) |
4782ac80 JZ |
283 | pci_write_config_byte(pdev, 0x41, 0xa1); |
284 | ||
285 | /* initialize adapter */ | |
286 | rc = ahci_host_init(probe_ent); | |
287 | if (rc) | |
288 | goto err_out; | |
289 | ||
290 | ahci_print_info(probe_ent); | |
291 | ||
292 | return 0; | |
293 | ||
4a7cc0f2 | 294 | err_out: |
4782ac80 JZ |
295 | return rc; |
296 | } | |
297 | ||
298 | ||
299 | #define MAX_DATA_BYTE_COUNT (4*1024*1024) | |
4a7cc0f2 | 300 | |
4782ac80 JZ |
301 | static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) |
302 | { | |
4782ac80 JZ |
303 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
304 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; | |
305 | u32 sg_count; | |
306 | int i; | |
307 | ||
308 | sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; | |
4a7cc0f2 | 309 | if (sg_count > AHCI_MAX_SG) { |
4782ac80 JZ |
310 | printf("Error:Too much sg!\n"); |
311 | return -1; | |
312 | } | |
313 | ||
4a7cc0f2 JL |
314 | for (i = 0; i < sg_count; i++) { |
315 | ahci_sg->addr = | |
316 | cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); | |
4782ac80 | 317 | ahci_sg->addr_hi = 0; |
4a7cc0f2 JL |
318 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & |
319 | (buf_len < MAX_DATA_BYTE_COUNT | |
320 | ? (buf_len - 1) | |
321 | : (MAX_DATA_BYTE_COUNT - 1))); | |
4782ac80 JZ |
322 | ahci_sg++; |
323 | buf_len -= MAX_DATA_BYTE_COUNT; | |
324 | } | |
325 | ||
326 | return sg_count; | |
327 | } | |
328 | ||
329 | ||
330 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) | |
331 | { | |
332 | pp->cmd_slot->opts = cpu_to_le32(opts); | |
333 | pp->cmd_slot->status = 0; | |
334 | pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); | |
335 | pp->cmd_slot->tbl_addr_hi = 0; | |
336 | } | |
337 | ||
338 | ||
339 | static void ahci_set_feature(u8 port) | |
340 | { | |
4782ac80 | 341 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 JL |
342 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
343 | u32 cmd_fis_len = 5; /* five dwords */ | |
4782ac80 JZ |
344 | u8 fis[20]; |
345 | ||
4a7cc0f2 JL |
346 | /*set feature */ |
347 | memset(fis, 0, 20); | |
4782ac80 JZ |
348 | fis[0] = 0x27; |
349 | fis[1] = 1 << 7; | |
350 | fis[2] = ATA_CMD_SETF; | |
351 | fis[3] = SETFEATURES_XFER; | |
352 | fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; | |
353 | ||
4a7cc0f2 | 354 | memcpy((unsigned char *)pp->cmd_tbl, fis, 20); |
4782ac80 JZ |
355 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
356 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
357 | readl(port_mmio + PORT_CMD_ISSUE); | |
358 | ||
4a7cc0f2 | 359 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { |
4782ac80 JZ |
360 | printf("set feature error!\n"); |
361 | } | |
362 | } | |
363 | ||
364 | ||
365 | static int ahci_port_start(u8 port) | |
366 | { | |
4782ac80 | 367 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 | 368 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
4782ac80 JZ |
369 | u32 port_status; |
370 | u32 mem; | |
371 | ||
4a7cc0f2 | 372 | debug("Enter start port: %d\n", port); |
4782ac80 | 373 | port_status = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
374 | debug("Port %d status: %x\n", port, port_status); |
375 | if ((port_status & 0xf) != 0x03) { | |
4782ac80 JZ |
376 | printf("No Link on this port!\n"); |
377 | return -1; | |
378 | } | |
379 | ||
4a7cc0f2 | 380 | mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); |
4782ac80 JZ |
381 | if (!mem) { |
382 | free(pp); | |
383 | printf("No mem for table!\n"); | |
384 | return -ENOMEM; | |
385 | } | |
386 | ||
4a7cc0f2 JL |
387 | mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ |
388 | memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
4782ac80 | 389 | |
4782ac80 JZ |
390 | /* |
391 | * First item in chunk of DMA memory: 32-slot command table, | |
392 | * 32 bytes each in size | |
393 | */ | |
394 | pp->cmd_slot = (struct ahci_cmd_hdr *)mem; | |
4a7cc0f2 | 395 | debug("cmd_slot = 0x%x\n", pp->cmd_slot); |
4782ac80 | 396 | mem += (AHCI_CMD_SLOT_SZ + 224); |
4a7cc0f2 | 397 | |
4782ac80 JZ |
398 | /* |
399 | * Second item: Received-FIS area | |
400 | */ | |
401 | pp->rx_fis = mem; | |
4782ac80 | 402 | mem += AHCI_RX_FIS_SZ; |
4a7cc0f2 | 403 | |
4782ac80 JZ |
404 | /* |
405 | * Third item: data area for storing a single command | |
406 | * and its scatter-gather table | |
407 | */ | |
408 | pp->cmd_tbl = mem; | |
4a7cc0f2 | 409 | debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); |
4782ac80 JZ |
410 | |
411 | mem += AHCI_CMD_TBL_HDR; | |
412 | pp->cmd_tbl_sg = (struct ahci_sg *)mem; | |
413 | ||
4a7cc0f2 | 414 | writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); |
4782ac80 JZ |
415 | |
416 | writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); | |
417 | ||
418 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | | |
4a7cc0f2 JL |
419 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
420 | PORT_CMD_START, port_mmio + PORT_CMD); | |
4782ac80 | 421 | |
4a7cc0f2 | 422 | debug("Exit start port %d\n", port); |
4782ac80 JZ |
423 | |
424 | return 0; | |
425 | } | |
426 | ||
427 | ||
4a7cc0f2 JL |
428 | static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, |
429 | int buf_len) | |
4782ac80 JZ |
430 | { |
431 | ||
4a7cc0f2 JL |
432 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
433 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; | |
4782ac80 JZ |
434 | u32 opts; |
435 | u32 port_status; | |
436 | int sg_count; | |
437 | ||
4a7cc0f2 | 438 | debug("Enter get_ahci_device_data: for port %d\n", port); |
4782ac80 | 439 | |
4a7cc0f2 | 440 | if (port > probe_ent->n_ports) { |
4782ac80 JZ |
441 | printf("Invaild port number %d\n", port); |
442 | return -1; | |
443 | } | |
444 | ||
445 | port_status = readl(port_mmio + PORT_SCR_STAT); | |
4a7cc0f2 JL |
446 | if ((port_status & 0xf) != 0x03) { |
447 | debug("No Link on port %d!\n", port); | |
4782ac80 JZ |
448 | return -1; |
449 | } | |
450 | ||
451 | memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); | |
452 | ||
4a7cc0f2 JL |
453 | sg_count = ahci_fill_sg(port, buf, buf_len); |
454 | opts = (fis_len >> 2) | (sg_count << 16); | |
4782ac80 JZ |
455 | ahci_fill_cmd_slot(pp, opts); |
456 | ||
457 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); | |
458 | ||
459 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { | |
460 | printf("timeout exit!\n"); | |
461 | return -1; | |
462 | } | |
463 | debug("get_ahci_device_data: %d byte transferred.\n", | |
4a7cc0f2 | 464 | pp->cmd_slot->status); |
4782ac80 JZ |
465 | |
466 | return 0; | |
467 | } | |
468 | ||
469 | ||
470 | static char *ata_id_strcpy(u16 *target, u16 *src, int len) | |
471 | { | |
472 | int i; | |
4a7cc0f2 | 473 | for (i = 0; i < len / 2; i++) |
4782ac80 JZ |
474 | target[i] = le16_to_cpu(src[i]); |
475 | return (char *)target; | |
476 | } | |
477 | ||
478 | ||
479 | static void dump_ataid(hd_driveid_t *ataid) | |
480 | { | |
481 | debug("(49)ataid->capability = 0x%x\n", ataid->capability); | |
482 | debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); | |
483 | debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); | |
484 | debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); | |
485 | debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); | |
486 | debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); | |
487 | debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); | |
488 | debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); | |
489 | debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); | |
490 | debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); | |
491 | debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); | |
492 | debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); | |
493 | debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); | |
494 | debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); | |
495 | debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); | |
496 | } | |
497 | ||
4a7cc0f2 | 498 | |
4782ac80 JZ |
499 | /* |
500 | * SCSI INQUIRY command operation. | |
501 | */ | |
502 | static int ata_scsiop_inquiry(ccb *pccb) | |
503 | { | |
504 | u8 hdr[] = { | |
505 | 0, | |
506 | 0, | |
4a7cc0f2 | 507 | 0x5, /* claim SPC-3 version compatibility */ |
4782ac80 JZ |
508 | 2, |
509 | 95 - 4, | |
510 | }; | |
511 | u8 fis[20]; | |
512 | u8 *tmpid; | |
513 | u8 port; | |
514 | ||
515 | /* Clean ccb data buffer */ | |
516 | memset(pccb->pdata, 0, pccb->datalen); | |
517 | ||
518 | memcpy(pccb->pdata, hdr, sizeof(hdr)); | |
519 | ||
4a7cc0f2 | 520 | if (pccb->datalen <= 35) |
4782ac80 JZ |
521 | return 0; |
522 | ||
523 | memset(fis, 0, 20); | |
524 | /* Construct the FIS */ | |
4a7cc0f2 JL |
525 | fis[0] = 0x27; /* Host to device FIS. */ |
526 | fis[1] = 1 << 7; /* Command FIS. */ | |
527 | fis[2] = ATA_CMD_IDENT; /* Command byte. */ | |
4782ac80 JZ |
528 | |
529 | /* Read id from sata */ | |
530 | port = pccb->target; | |
4a7cc0f2 | 531 | if (!(tmpid = malloc(sizeof(hd_driveid_t)))) |
4782ac80 JZ |
532 | return -ENOMEM; |
533 | ||
4a7cc0f2 JL |
534 | if (get_ahci_device_data(port, (u8 *) & fis, 20, |
535 | tmpid, sizeof(hd_driveid_t))) { | |
4782ac80 JZ |
536 | debug("scsi_ahci: SCSI inquiry command failure.\n"); |
537 | return -EIO; | |
538 | } | |
539 | ||
4a7cc0f2 | 540 | if (ataid[port]) |
4782ac80 | 541 | free(ataid[port]); |
4a7cc0f2 | 542 | ataid[port] = (hd_driveid_t *) tmpid; |
4782ac80 JZ |
543 | |
544 | memcpy(&pccb->pdata[8], "ATA ", 8); | |
4a7cc0f2 JL |
545 | ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); |
546 | ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); | |
4782ac80 JZ |
547 | |
548 | dump_ataid(ataid[port]); | |
549 | return 0; | |
550 | } | |
551 | ||
552 | ||
553 | /* | |
554 | * SCSI READ10 command operation. | |
555 | */ | |
4a7cc0f2 | 556 | static int ata_scsiop_read10(ccb * pccb) |
4782ac80 JZ |
557 | { |
558 | u64 lba = 0; | |
559 | u32 len = 0; | |
560 | u8 fis[20]; | |
561 | ||
4a7cc0f2 JL |
562 | lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16) |
563 | | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]); | |
564 | len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]); | |
4782ac80 JZ |
565 | |
566 | /* For 10-byte and 16-byte SCSI R/W commands, transfer | |
567 | * length 0 means transfer 0 block of data. | |
568 | * However, for ATA R/W commands, sector count 0 means | |
569 | * 256 or 65536 sectors, not 0 sectors as in SCSI. | |
570 | * | |
571 | * WARNING: one or two older ATA drives treat 0 as 0... | |
572 | */ | |
4a7cc0f2 JL |
573 | if (!len) |
574 | return 0; | |
4782ac80 JZ |
575 | memset(fis, 0, 20); |
576 | ||
577 | /* Construct the FIS */ | |
4a7cc0f2 JL |
578 | fis[0] = 0x27; /* Host to device FIS. */ |
579 | fis[1] = 1 << 7; /* Command FIS. */ | |
4782ac80 JZ |
580 | fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ |
581 | ||
4a7cc0f2 | 582 | /* LBA address, only support LBA28 in this driver */ |
4782ac80 JZ |
583 | fis[4] = pccb->cmd[5]; |
584 | fis[5] = pccb->cmd[4]; | |
585 | fis[6] = pccb->cmd[3]; | |
586 | fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; | |
587 | ||
588 | /* Sector Count */ | |
589 | fis[12] = pccb->cmd[8]; | |
590 | fis[13] = pccb->cmd[7]; | |
591 | ||
592 | /* Read from ahci */ | |
4a7cc0f2 JL |
593 | if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20, |
594 | pccb->pdata, pccb->datalen)) { | |
4782ac80 JZ |
595 | debug("scsi_ahci: SCSI READ10 command failure.\n"); |
596 | return -EIO; | |
597 | } | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | ||
603 | /* | |
604 | * SCSI READ CAPACITY10 command operation. | |
605 | */ | |
606 | static int ata_scsiop_read_capacity10(ccb *pccb) | |
607 | { | |
608 | u8 buf[8]; | |
609 | ||
4a7cc0f2 | 610 | if (!ataid[pccb->target]) { |
4782ac80 | 611 | printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " |
4a7cc0f2 JL |
612 | "\tNo ATA info!\n" |
613 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); | |
4782ac80 JZ |
614 | return -EPERM; |
615 | } | |
616 | ||
617 | memset(buf, 0, 8); | |
618 | ||
4a7cc0f2 | 619 | *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); |
4782ac80 JZ |
620 | |
621 | buf[6] = 512 >> 8; | |
622 | buf[7] = 512 & 0xff; | |
623 | ||
624 | memcpy(pccb->pdata, buf, 8); | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | ||
630 | /* | |
631 | * SCSI TEST UNIT READY command operation. | |
632 | */ | |
633 | static int ata_scsiop_test_unit_ready(ccb *pccb) | |
634 | { | |
635 | return (ataid[pccb->target]) ? 0 : -EPERM; | |
636 | } | |
637 | ||
4a7cc0f2 | 638 | |
4782ac80 JZ |
639 | int scsi_exec(ccb *pccb) |
640 | { | |
641 | int ret; | |
642 | ||
4a7cc0f2 | 643 | switch (pccb->cmd[0]) { |
4782ac80 JZ |
644 | case SCSI_READ10: |
645 | ret = ata_scsiop_read10(pccb); | |
646 | break; | |
647 | case SCSI_RD_CAPAC: | |
648 | ret = ata_scsiop_read_capacity10(pccb); | |
649 | break; | |
650 | case SCSI_TST_U_RDY: | |
651 | ret = ata_scsiop_test_unit_ready(pccb); | |
652 | break; | |
653 | case SCSI_INQUIRY: | |
654 | ret = ata_scsiop_inquiry(pccb); | |
655 | break; | |
656 | default: | |
657 | printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); | |
658 | return FALSE; | |
659 | } | |
660 | ||
4a7cc0f2 JL |
661 | if (ret) { |
662 | debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); | |
4782ac80 JZ |
663 | return FALSE; |
664 | } | |
665 | return TRUE; | |
666 | ||
667 | } | |
668 | ||
669 | ||
670 | void scsi_low_level_init(int busdevfunc) | |
671 | { | |
672 | int i; | |
673 | u32 linkmap; | |
674 | ||
675 | ahci_init_one(busdevfunc); | |
676 | ||
677 | linkmap = probe_ent->link_port_map; | |
678 | ||
6d0f6bcf | 679 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { |
4a7cc0f2 JL |
680 | if (((linkmap >> i) & 0x01)) { |
681 | if (ahci_port_start((u8) i)) { | |
682 | printf("Can not start port %d\n", i); | |
4782ac80 JZ |
683 | continue; |
684 | } | |
4a7cc0f2 | 685 | ahci_set_feature((u8) i); |
4782ac80 JZ |
686 | } |
687 | } | |
688 | } | |
689 | ||
690 | ||
691 | void scsi_bus_reset(void) | |
692 | { | |
4a7cc0f2 | 693 | /*Not implement*/ |
4782ac80 JZ |
694 | } |
695 | ||
696 | ||
4a7cc0f2 | 697 | void scsi_print_error(ccb * pccb) |
4782ac80 | 698 | { |
4a7cc0f2 | 699 | /*The ahci error info can be read in the ahci driver*/ |
4782ac80 | 700 | } |