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4782ac80 | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
4782ac80 JZ |
3 | * Author: Jason Jin<Jason.jin@freescale.com> |
4 | * Zhang Wei<wei.zhang@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
4782ac80 JZ |
7 | * |
8 | * with the reference on libata and ahci drvier in kernel | |
4782ac80 JZ |
9 | */ |
10 | #include <common.h> | |
11 | ||
4782ac80 JZ |
12 | #include <command.h> |
13 | #include <pci.h> | |
14 | #include <asm/processor.h> | |
15 | #include <asm/errno.h> | |
16 | #include <asm/io.h> | |
17 | #include <malloc.h> | |
18 | #include <scsi.h> | |
344ca0b4 | 19 | #include <libata.h> |
4782ac80 JZ |
20 | #include <linux/ctype.h> |
21 | #include <ahci.h> | |
22 | ||
766b16fe MJ |
23 | static int ata_io_flush(u8 port); |
24 | ||
4782ac80 | 25 | struct ahci_probe_ent *probe_ent = NULL; |
344ca0b4 | 26 | u16 *ataid[AHCI_MAX_PORTS]; |
4782ac80 | 27 | |
4a7cc0f2 JL |
28 | #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) |
29 | ||
284231e4 | 30 | /* |
b7a21b70 HTL |
31 | * Some controllers limit number of blocks they can read/write at once. |
32 | * Contemporary SSD devices work much faster if the read/write size is aligned | |
33 | * to a power of 2. Let's set default to 128 and allowing to be overwritten if | |
34 | * needed. | |
284231e4 | 35 | */ |
b7a21b70 HTL |
36 | #ifndef MAX_SATA_BLOCKS_READ_WRITE |
37 | #define MAX_SATA_BLOCKS_READ_WRITE 0x80 | |
284231e4 | 38 | #endif |
4782ac80 | 39 | |
57847660 | 40 | /* Maximum timeouts for each event */ |
7610b41d | 41 | #define WAIT_MS_SPINUP 20000 |
57847660 | 42 | #define WAIT_MS_DATAIO 5000 |
766b16fe | 43 | #define WAIT_MS_FLUSH 5000 |
e0ddcf93 | 44 | #define WAIT_MS_LINKUP 200 |
57847660 | 45 | |
4782ac80 JZ |
46 | static inline u32 ahci_port_base(u32 base, u32 port) |
47 | { | |
48 | return base + 0x100 + (port * 0x80); | |
49 | } | |
50 | ||
51 | ||
52 | static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, | |
53 | unsigned int port_idx) | |
54 | { | |
55 | base = ahci_port_base(base, port_idx); | |
56 | ||
4a7cc0f2 JL |
57 | port->cmd_addr = base; |
58 | port->scr_addr = base + PORT_SCR; | |
4782ac80 JZ |
59 | } |
60 | ||
61 | ||
62 | #define msleep(a) udelay(a * 1000) | |
4a7cc0f2 | 63 | |
90b276f6 TH |
64 | static void ahci_dcache_flush_range(unsigned begin, unsigned len) |
65 | { | |
66 | const unsigned long start = begin; | |
67 | const unsigned long end = start + len; | |
68 | ||
69 | debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); | |
70 | flush_dcache_range(start, end); | |
71 | } | |
72 | ||
73 | /* | |
74 | * SATA controller DMAs to physical RAM. Ensure data from the | |
75 | * controller is invalidated from dcache; next access comes from | |
76 | * physical RAM. | |
77 | */ | |
78 | static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) | |
79 | { | |
80 | const unsigned long start = begin; | |
81 | const unsigned long end = start + len; | |
82 | ||
83 | debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); | |
84 | invalidate_dcache_range(start, end); | |
85 | } | |
86 | ||
87 | /* | |
88 | * Ensure data for SATA controller is flushed out of dcache and | |
89 | * written to physical memory. | |
90 | */ | |
91 | static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) | |
92 | { | |
93 | ahci_dcache_flush_range((unsigned long)pp->cmd_slot, | |
94 | AHCI_PORT_PRIV_DMA_SZ); | |
95 | } | |
96 | ||
4a7cc0f2 JL |
97 | static int waiting_for_cmd_completed(volatile u8 *offset, |
98 | int timeout_msec, | |
99 | u32 sign) | |
4782ac80 JZ |
100 | { |
101 | int i; | |
102 | u32 status; | |
4a7cc0f2 JL |
103 | |
104 | for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) | |
4782ac80 JZ |
105 | msleep(1); |
106 | ||
4a7cc0f2 | 107 | return (i < timeout_msec) ? 0 : -1; |
4782ac80 JZ |
108 | } |
109 | ||
124e9fa1 RH |
110 | int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) |
111 | { | |
112 | u32 tmp; | |
113 | int j = 0; | |
114 | u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; | |
115 | ||
3765b3e7 | 116 | /* |
124e9fa1 RH |
117 | * Bring up SATA link. |
118 | * SATA link bringup time is usually less than 1 ms; only very | |
119 | * rarely has it taken between 1-2 ms. Never seen it above 2 ms. | |
120 | */ | |
121 | while (j < WAIT_MS_LINKUP) { | |
122 | tmp = readl(port_mmio + PORT_SCR_STAT); | |
123 | tmp &= PORT_SCR_STAT_DET_MASK; | |
124 | if (tmp == PORT_SCR_STAT_DET_PHYRDY) | |
125 | return 0; | |
126 | udelay(1000); | |
127 | j++; | |
128 | } | |
129 | return 1; | |
130 | } | |
4782ac80 | 131 | |
a6e50a88 IC |
132 | #ifdef CONFIG_SUNXI_AHCI |
133 | /* The sunxi AHCI controller requires this undocumented setup */ | |
134 | static void sunxi_dma_init(volatile u8 *port_mmio) | |
135 | { | |
136 | clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); | |
137 | } | |
138 | #endif | |
139 | ||
4782ac80 JZ |
140 | static int ahci_host_init(struct ahci_probe_ent *probe_ent) |
141 | { | |
942e3143 | 142 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 143 | pci_dev_t pdev = probe_ent->dev; |
942e3143 RH |
144 | u16 tmp16; |
145 | unsigned short vendor; | |
146 | #endif | |
4782ac80 | 147 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
2a0c61d4 | 148 | u32 tmp, cap_save, cmd; |
124e9fa1 | 149 | int i, j, ret; |
4a7cc0f2 | 150 | volatile u8 *port_mmio; |
2915a022 | 151 | u32 port_map; |
4782ac80 | 152 | |
284231e4 VB |
153 | debug("ahci_host_init: start\n"); |
154 | ||
4782ac80 | 155 | cap_save = readl(mmio + HOST_CAP); |
4a7cc0f2 | 156 | cap_save &= ((1 << 28) | (1 << 17)); |
2a0c61d4 | 157 | cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ |
4782ac80 JZ |
158 | |
159 | /* global controller reset */ | |
160 | tmp = readl(mmio + HOST_CTL); | |
161 | if ((tmp & HOST_RESET) == 0) | |
162 | writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); | |
163 | ||
164 | /* reset must complete within 1 second, or | |
165 | * the hardware should be considered fried. | |
166 | */ | |
9a65b875 SR |
167 | i = 1000; |
168 | do { | |
169 | udelay(1000); | |
170 | tmp = readl(mmio + HOST_CTL); | |
171 | if (!i--) { | |
172 | debug("controller reset failed (0x%x)\n", tmp); | |
173 | return -1; | |
174 | } | |
175 | } while (tmp & HOST_RESET); | |
4782ac80 JZ |
176 | |
177 | writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); | |
178 | writel(cap_save, mmio + HOST_CAP); | |
179 | writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); | |
180 | ||
942e3143 | 181 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 JZ |
182 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
183 | ||
184 | if (vendor == PCI_VENDOR_ID_INTEL) { | |
185 | u16 tmp16; | |
186 | pci_read_config_word(pdev, 0x92, &tmp16); | |
187 | tmp16 |= 0xf; | |
188 | pci_write_config_word(pdev, 0x92, tmp16); | |
189 | } | |
942e3143 | 190 | #endif |
4782ac80 JZ |
191 | probe_ent->cap = readl(mmio + HOST_CAP); |
192 | probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); | |
2915a022 | 193 | port_map = probe_ent->port_map; |
4782ac80 JZ |
194 | probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; |
195 | ||
196 | debug("cap 0x%x port_map 0x%x n_ports %d\n", | |
4a7cc0f2 | 197 | probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); |
4782ac80 | 198 | |
284231e4 VB |
199 | if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) |
200 | probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; | |
201 | ||
4782ac80 | 202 | for (i = 0; i < probe_ent->n_ports; i++) { |
2915a022 RG |
203 | if (!(port_map & (1 << i))) |
204 | continue; | |
4a7cc0f2 JL |
205 | probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); |
206 | port_mmio = (u8 *) probe_ent->port[i].port_mmio; | |
207 | ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); | |
4782ac80 JZ |
208 | |
209 | /* make sure port is not active */ | |
210 | tmp = readl(port_mmio + PORT_CMD); | |
211 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
212 | PORT_CMD_FIS_RX | PORT_CMD_START)) { | |
7ba7917c | 213 | debug("Port %d is active. Deactivating.\n", i); |
4782ac80 JZ |
214 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
215 | PORT_CMD_FIS_RX | PORT_CMD_START); | |
216 | writel_with_flush(tmp, port_mmio + PORT_CMD); | |
217 | ||
218 | /* spec says 500 msecs for each bit, so | |
219 | * this is slightly incorrect. | |
220 | */ | |
221 | msleep(500); | |
222 | } | |
223 | ||
a6e50a88 IC |
224 | #ifdef CONFIG_SUNXI_AHCI |
225 | sunxi_dma_init(port_mmio); | |
226 | #endif | |
227 | ||
2a0c61d4 MJ |
228 | /* Add the spinup command to whatever mode bits may |
229 | * already be on in the command register. | |
230 | */ | |
231 | cmd = readl(port_mmio + PORT_CMD); | |
2a0c61d4 MJ |
232 | cmd |= PORT_CMD_SPIN_UP; |
233 | writel_with_flush(cmd, port_mmio + PORT_CMD); | |
234 | ||
124e9fa1 RH |
235 | /* Bring up SATA link. */ |
236 | ret = ahci_link_up(probe_ent, i); | |
237 | if (ret) { | |
2a0c61d4 MJ |
238 | printf("SATA link %d timeout.\n", i); |
239 | continue; | |
240 | } else { | |
241 | debug("SATA link ok.\n"); | |
242 | } | |
243 | ||
244 | /* Clear error status */ | |
245 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
246 | if (tmp) | |
247 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
248 | ||
249 | debug("Spinning up device on SATA port %d... ", i); | |
250 | ||
251 | j = 0; | |
252 | while (j < WAIT_MS_SPINUP) { | |
253 | tmp = readl(port_mmio + PORT_TFDATA); | |
344ca0b4 | 254 | if (!(tmp & (ATA_BUSY | ATA_DRQ))) |
2a0c61d4 MJ |
255 | break; |
256 | udelay(1000); | |
17821084 RH |
257 | tmp = readl(port_mmio + PORT_SCR_STAT); |
258 | tmp &= PORT_SCR_STAT_DET_MASK; | |
259 | if (tmp == PORT_SCR_STAT_DET_PHYRDY) | |
260 | break; | |
2a0c61d4 MJ |
261 | j++; |
262 | } | |
17821084 RH |
263 | |
264 | tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; | |
265 | if (tmp == PORT_SCR_STAT_DET_COMINIT) { | |
266 | debug("SATA link %d down (COMINIT received), retrying...\n", i); | |
267 | i--; | |
268 | continue; | |
269 | } | |
270 | ||
2a0c61d4 MJ |
271 | printf("Target spinup took %d ms.\n", j); |
272 | if (j == WAIT_MS_SPINUP) | |
9a65b875 SR |
273 | debug("timeout.\n"); |
274 | else | |
275 | debug("ok.\n"); | |
4782ac80 JZ |
276 | |
277 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
278 | debug("PORT_SCR_ERR 0x%x\n", tmp); | |
279 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
280 | ||
281 | /* ack any pending irq events for this port */ | |
282 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
283 | debug("PORT_IRQ_STAT 0x%x\n", tmp); | |
284 | if (tmp) | |
285 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
286 | ||
287 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
288 | ||
289 | /* set irq mask (enables interrupts) */ | |
290 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
291 | ||
4e422bce | 292 | /* register linkup ports */ |
4782ac80 | 293 | tmp = readl(port_mmio + PORT_SCR_STAT); |
766b16fe | 294 | debug("SATA port %d status: 0x%x\n", i, tmp); |
2bdb10db | 295 | if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) |
4a7cc0f2 | 296 | probe_ent->link_port_map |= (0x01 << i); |
4782ac80 JZ |
297 | } |
298 | ||
299 | tmp = readl(mmio + HOST_CTL); | |
300 | debug("HOST_CTL 0x%x\n", tmp); | |
301 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
302 | tmp = readl(mmio + HOST_CTL); | |
303 | debug("HOST_CTL 0x%x\n", tmp); | |
942e3143 | 304 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 JZ |
305 | pci_read_config_word(pdev, PCI_COMMAND, &tmp16); |
306 | tmp |= PCI_COMMAND_MASTER; | |
307 | pci_write_config_word(pdev, PCI_COMMAND, tmp16); | |
942e3143 | 308 | #endif |
4782ac80 JZ |
309 | return 0; |
310 | } | |
311 | ||
312 | ||
313 | static void ahci_print_info(struct ahci_probe_ent *probe_ent) | |
314 | { | |
942e3143 | 315 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 316 | pci_dev_t pdev = probe_ent->dev; |
942e3143 RH |
317 | u16 cc; |
318 | #endif | |
4a7cc0f2 | 319 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
4e422bce | 320 | u32 vers, cap, cap2, impl, speed; |
4782ac80 | 321 | const char *speed_s; |
4782ac80 JZ |
322 | const char *scc_s; |
323 | ||
324 | vers = readl(mmio + HOST_VERSION); | |
325 | cap = probe_ent->cap; | |
4e422bce | 326 | cap2 = readl(mmio + HOST_CAP2); |
4782ac80 JZ |
327 | impl = probe_ent->port_map; |
328 | ||
329 | speed = (cap >> 20) & 0xf; | |
330 | if (speed == 1) | |
331 | speed_s = "1.5"; | |
332 | else if (speed == 2) | |
333 | speed_s = "3"; | |
4e422bce SR |
334 | else if (speed == 3) |
335 | speed_s = "6"; | |
4782ac80 JZ |
336 | else |
337 | speed_s = "?"; | |
338 | ||
942e3143 RH |
339 | #ifdef CONFIG_SCSI_AHCI_PLAT |
340 | scc_s = "SATA"; | |
341 | #else | |
4782ac80 JZ |
342 | pci_read_config_word(pdev, 0x0a, &cc); |
343 | if (cc == 0x0101) | |
344 | scc_s = "IDE"; | |
345 | else if (cc == 0x0106) | |
346 | scc_s = "SATA"; | |
347 | else if (cc == 0x0104) | |
348 | scc_s = "RAID"; | |
349 | else | |
350 | scc_s = "unknown"; | |
942e3143 | 351 | #endif |
4a7cc0f2 JL |
352 | printf("AHCI %02x%02x.%02x%02x " |
353 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", | |
354 | (vers >> 24) & 0xff, | |
355 | (vers >> 16) & 0xff, | |
356 | (vers >> 8) & 0xff, | |
357 | vers & 0xff, | |
358 | ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); | |
4782ac80 JZ |
359 | |
360 | printf("flags: " | |
4e422bce SR |
361 | "%s%s%s%s%s%s%s" |
362 | "%s%s%s%s%s%s%s" | |
363 | "%s%s%s%s%s%s\n", | |
4a7cc0f2 JL |
364 | cap & (1 << 31) ? "64bit " : "", |
365 | cap & (1 << 30) ? "ncq " : "", | |
366 | cap & (1 << 28) ? "ilck " : "", | |
367 | cap & (1 << 27) ? "stag " : "", | |
368 | cap & (1 << 26) ? "pm " : "", | |
369 | cap & (1 << 25) ? "led " : "", | |
370 | cap & (1 << 24) ? "clo " : "", | |
371 | cap & (1 << 19) ? "nz " : "", | |
372 | cap & (1 << 18) ? "only " : "", | |
373 | cap & (1 << 17) ? "pmp " : "", | |
4e422bce | 374 | cap & (1 << 16) ? "fbss " : "", |
4a7cc0f2 JL |
375 | cap & (1 << 15) ? "pio " : "", |
376 | cap & (1 << 14) ? "slum " : "", | |
4e422bce SR |
377 | cap & (1 << 13) ? "part " : "", |
378 | cap & (1 << 7) ? "ccc " : "", | |
379 | cap & (1 << 6) ? "ems " : "", | |
380 | cap & (1 << 5) ? "sxs " : "", | |
381 | cap2 & (1 << 2) ? "apst " : "", | |
382 | cap2 & (1 << 1) ? "nvmp " : "", | |
383 | cap2 & (1 << 0) ? "boh " : ""); | |
4782ac80 JZ |
384 | } |
385 | ||
942e3143 | 386 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4a7cc0f2 | 387 | static int ahci_init_one(pci_dev_t pdev) |
4782ac80 | 388 | { |
63cec581 | 389 | u16 vendor; |
4782ac80 JZ |
390 | int rc; |
391 | ||
594e7983 | 392 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
d73763a4 RQ |
393 | if (!probe_ent) { |
394 | printf("%s: No memory for probe_ent\n", __func__); | |
395 | return -ENOMEM; | |
396 | } | |
397 | ||
594e7983 | 398 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); |
4782ac80 JZ |
399 | probe_ent->dev = pdev; |
400 | ||
4a7cc0f2 JL |
401 | probe_ent->host_flags = ATA_FLAG_SATA |
402 | | ATA_FLAG_NO_LEGACY | |
403 | | ATA_FLAG_MMIO | |
404 | | ATA_FLAG_PIO_DMA | |
405 | | ATA_FLAG_NO_ATAPI; | |
406 | probe_ent->pio_mask = 0x1f; | |
407 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
4782ac80 | 408 | |
284231e4 VB |
409 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base); |
410 | debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base); | |
4782ac80 JZ |
411 | |
412 | /* Take from kernel: | |
413 | * JMicron-specific fixup: | |
414 | * make sure we're in AHCI mode | |
415 | */ | |
416 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); | |
4a7cc0f2 | 417 | if (vendor == 0x197b) |
4782ac80 JZ |
418 | pci_write_config_byte(pdev, 0x41, 0xa1); |
419 | ||
420 | /* initialize adapter */ | |
421 | rc = ahci_host_init(probe_ent); | |
422 | if (rc) | |
423 | goto err_out; | |
424 | ||
425 | ahci_print_info(probe_ent); | |
426 | ||
427 | return 0; | |
428 | ||
4a7cc0f2 | 429 | err_out: |
4782ac80 JZ |
430 | return rc; |
431 | } | |
942e3143 | 432 | #endif |
4782ac80 JZ |
433 | |
434 | #define MAX_DATA_BYTE_COUNT (4*1024*1024) | |
4a7cc0f2 | 435 | |
4782ac80 JZ |
436 | static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) |
437 | { | |
4782ac80 JZ |
438 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
439 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; | |
440 | u32 sg_count; | |
441 | int i; | |
442 | ||
443 | sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; | |
4a7cc0f2 | 444 | if (sg_count > AHCI_MAX_SG) { |
4782ac80 JZ |
445 | printf("Error:Too much sg!\n"); |
446 | return -1; | |
447 | } | |
448 | ||
4a7cc0f2 JL |
449 | for (i = 0; i < sg_count; i++) { |
450 | ahci_sg->addr = | |
451 | cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); | |
4782ac80 | 452 | ahci_sg->addr_hi = 0; |
4a7cc0f2 JL |
453 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & |
454 | (buf_len < MAX_DATA_BYTE_COUNT | |
455 | ? (buf_len - 1) | |
456 | : (MAX_DATA_BYTE_COUNT - 1))); | |
4782ac80 JZ |
457 | ahci_sg++; |
458 | buf_len -= MAX_DATA_BYTE_COUNT; | |
459 | } | |
460 | ||
461 | return sg_count; | |
462 | } | |
463 | ||
464 | ||
465 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) | |
466 | { | |
467 | pp->cmd_slot->opts = cpu_to_le32(opts); | |
468 | pp->cmd_slot->status = 0; | |
469 | pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); | |
470 | pp->cmd_slot->tbl_addr_hi = 0; | |
471 | } | |
472 | ||
473 | ||
e81058c0 | 474 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
4782ac80 JZ |
475 | static void ahci_set_feature(u8 port) |
476 | { | |
4782ac80 | 477 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 JL |
478 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
479 | u32 cmd_fis_len = 5; /* five dwords */ | |
4782ac80 JZ |
480 | u8 fis[20]; |
481 | ||
4e422bce | 482 | /* set feature */ |
c8731115 | 483 | memset(fis, 0, sizeof(fis)); |
4782ac80 JZ |
484 | fis[0] = 0x27; |
485 | fis[1] = 1 << 7; | |
344ca0b4 | 486 | fis[2] = ATA_CMD_SET_FEATURES; |
4782ac80 JZ |
487 | fis[3] = SETFEATURES_XFER; |
488 | fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; | |
489 | ||
c8731115 | 490 | memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis)); |
4782ac80 | 491 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
90b276f6 | 492 | ahci_dcache_flush_sata_cmd(pp); |
4782ac80 JZ |
493 | writel(1, port_mmio + PORT_CMD_ISSUE); |
494 | readl(port_mmio + PORT_CMD_ISSUE); | |
495 | ||
57847660 WM |
496 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
497 | WAIT_MS_DATAIO, 0x1)) { | |
4e422bce | 498 | printf("set feature error on port %d!\n", port); |
4782ac80 JZ |
499 | } |
500 | } | |
e81058c0 | 501 | #endif |
4782ac80 JZ |
502 | |
503 | ||
504 | static int ahci_port_start(u8 port) | |
505 | { | |
4782ac80 | 506 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 | 507 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
4782ac80 JZ |
508 | u32 port_status; |
509 | u32 mem; | |
510 | ||
4a7cc0f2 | 511 | debug("Enter start port: %d\n", port); |
4782ac80 | 512 | port_status = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
513 | debug("Port %d status: %x\n", port, port_status); |
514 | if ((port_status & 0xf) != 0x03) { | |
4782ac80 JZ |
515 | printf("No Link on this port!\n"); |
516 | return -1; | |
517 | } | |
518 | ||
4a7cc0f2 | 519 | mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); |
4782ac80 JZ |
520 | if (!mem) { |
521 | free(pp); | |
d73763a4 | 522 | printf("%s: No mem for table!\n", __func__); |
4782ac80 JZ |
523 | return -ENOMEM; |
524 | } | |
525 | ||
4a7cc0f2 JL |
526 | mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ |
527 | memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
4782ac80 | 528 | |
4782ac80 JZ |
529 | /* |
530 | * First item in chunk of DMA memory: 32-slot command table, | |
531 | * 32 bytes each in size | |
532 | */ | |
64738e8a TH |
533 | pp->cmd_slot = |
534 | (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); | |
284231e4 | 535 | debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); |
4782ac80 | 536 | mem += (AHCI_CMD_SLOT_SZ + 224); |
4a7cc0f2 | 537 | |
4782ac80 JZ |
538 | /* |
539 | * Second item: Received-FIS area | |
540 | */ | |
64738e8a | 541 | pp->rx_fis = virt_to_phys((void *)mem); |
4782ac80 | 542 | mem += AHCI_RX_FIS_SZ; |
4a7cc0f2 | 543 | |
4782ac80 JZ |
544 | /* |
545 | * Third item: data area for storing a single command | |
546 | * and its scatter-gather table | |
547 | */ | |
64738e8a | 548 | pp->cmd_tbl = virt_to_phys((void *)mem); |
4a7cc0f2 | 549 | debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); |
4782ac80 JZ |
550 | |
551 | mem += AHCI_CMD_TBL_HDR; | |
64738e8a TH |
552 | pp->cmd_tbl_sg = |
553 | (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); | |
4782ac80 | 554 | |
4a7cc0f2 | 555 | writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); |
4782ac80 JZ |
556 | |
557 | writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); | |
558 | ||
a6e50a88 IC |
559 | #ifdef CONFIG_SUNXI_AHCI |
560 | sunxi_dma_init(port_mmio); | |
561 | #endif | |
562 | ||
4782ac80 | 563 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | |
4a7cc0f2 JL |
564 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
565 | PORT_CMD_START, port_mmio + PORT_CMD); | |
4782ac80 | 566 | |
4a7cc0f2 | 567 | debug("Exit start port %d\n", port); |
4782ac80 JZ |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
572 | ||
b7a21b70 HTL |
573 | static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, |
574 | int buf_len, u8 is_write) | |
4782ac80 JZ |
575 | { |
576 | ||
4a7cc0f2 JL |
577 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
578 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; | |
4782ac80 JZ |
579 | u32 opts; |
580 | u32 port_status; | |
581 | int sg_count; | |
582 | ||
b7a21b70 | 583 | debug("Enter %s: for port %d\n", __func__, port); |
4782ac80 | 584 | |
4a7cc0f2 | 585 | if (port > probe_ent->n_ports) { |
5a2b77f4 | 586 | printf("Invalid port number %d\n", port); |
4782ac80 JZ |
587 | return -1; |
588 | } | |
589 | ||
590 | port_status = readl(port_mmio + PORT_SCR_STAT); | |
4a7cc0f2 JL |
591 | if ((port_status & 0xf) != 0x03) { |
592 | debug("No Link on port %d!\n", port); | |
4782ac80 JZ |
593 | return -1; |
594 | } | |
595 | ||
596 | memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); | |
597 | ||
4a7cc0f2 | 598 | sg_count = ahci_fill_sg(port, buf, buf_len); |
b7a21b70 | 599 | opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); |
4782ac80 JZ |
600 | ahci_fill_cmd_slot(pp, opts); |
601 | ||
90b276f6 TH |
602 | ahci_dcache_flush_sata_cmd(pp); |
603 | ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); | |
604 | ||
4782ac80 JZ |
605 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); |
606 | ||
57847660 WM |
607 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
608 | WAIT_MS_DATAIO, 0x1)) { | |
4782ac80 JZ |
609 | printf("timeout exit!\n"); |
610 | return -1; | |
611 | } | |
90b276f6 TH |
612 | |
613 | ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); | |
b7a21b70 | 614 | debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); |
4782ac80 JZ |
615 | |
616 | return 0; | |
617 | } | |
618 | ||
619 | ||
620 | static char *ata_id_strcpy(u16 *target, u16 *src, int len) | |
621 | { | |
622 | int i; | |
4a7cc0f2 | 623 | for (i = 0; i < len / 2; i++) |
e5a6c79d | 624 | target[i] = swab16(src[i]); |
4782ac80 JZ |
625 | return (char *)target; |
626 | } | |
627 | ||
4782ac80 JZ |
628 | /* |
629 | * SCSI INQUIRY command operation. | |
630 | */ | |
631 | static int ata_scsiop_inquiry(ccb *pccb) | |
632 | { | |
48c3a87c | 633 | static const u8 hdr[] = { |
4782ac80 JZ |
634 | 0, |
635 | 0, | |
4a7cc0f2 | 636 | 0x5, /* claim SPC-3 version compatibility */ |
4782ac80 JZ |
637 | 2, |
638 | 95 - 4, | |
639 | }; | |
640 | u8 fis[20]; | |
3f629711 | 641 | u16 *idbuf; |
2faf5fb8 | 642 | ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); |
4782ac80 JZ |
643 | u8 port; |
644 | ||
645 | /* Clean ccb data buffer */ | |
646 | memset(pccb->pdata, 0, pccb->datalen); | |
647 | ||
648 | memcpy(pccb->pdata, hdr, sizeof(hdr)); | |
649 | ||
4a7cc0f2 | 650 | if (pccb->datalen <= 35) |
4782ac80 JZ |
651 | return 0; |
652 | ||
c8731115 | 653 | memset(fis, 0, sizeof(fis)); |
4782ac80 | 654 | /* Construct the FIS */ |
4a7cc0f2 JL |
655 | fis[0] = 0x27; /* Host to device FIS. */ |
656 | fis[1] = 1 << 7; /* Command FIS. */ | |
344ca0b4 | 657 | fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ |
4782ac80 JZ |
658 | |
659 | /* Read id from sata */ | |
660 | port = pccb->target; | |
4782ac80 | 661 | |
344ca0b4 RH |
662 | if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, |
663 | ATA_ID_WORDS * 2, 0)) { | |
4782ac80 JZ |
664 | debug("scsi_ahci: SCSI inquiry command failure.\n"); |
665 | return -EIO; | |
666 | } | |
667 | ||
3f629711 RQ |
668 | if (!ataid[port]) { |
669 | ataid[port] = malloc(ATA_ID_WORDS * 2); | |
670 | if (!ataid[port]) { | |
671 | printf("%s: No memory for ataid[port]\n", __func__); | |
672 | return -ENOMEM; | |
673 | } | |
674 | } | |
675 | ||
676 | idbuf = ataid[port]; | |
677 | ||
678 | memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); | |
679 | ata_swap_buf_le16(idbuf, ATA_ID_WORDS); | |
4782ac80 JZ |
680 | |
681 | memcpy(&pccb->pdata[8], "ATA ", 8); | |
3f629711 RQ |
682 | ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); |
683 | ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); | |
4782ac80 | 684 | |
344ca0b4 | 685 | #ifdef DEBUG |
3f629711 | 686 | ata_dump_id(idbuf); |
344ca0b4 | 687 | #endif |
4782ac80 JZ |
688 | return 0; |
689 | } | |
690 | ||
691 | ||
692 | /* | |
b7a21b70 | 693 | * SCSI READ10/WRITE10 command operation. |
4782ac80 | 694 | */ |
b7a21b70 | 695 | static int ata_scsiop_read_write(ccb *pccb, u8 is_write) |
4782ac80 | 696 | { |
284231e4 VB |
697 | u32 lba = 0; |
698 | u16 blocks = 0; | |
4782ac80 | 699 | u8 fis[20]; |
284231e4 VB |
700 | u8 *user_buffer = pccb->pdata; |
701 | u32 user_buffer_size = pccb->datalen; | |
4782ac80 | 702 | |
284231e4 VB |
703 | /* Retrieve the base LBA number from the ccb structure. */ |
704 | memcpy(&lba, pccb->cmd + 2, sizeof(lba)); | |
705 | lba = be32_to_cpu(lba); | |
4782ac80 | 706 | |
284231e4 VB |
707 | /* |
708 | * And the number of blocks. | |
709 | * | |
710 | * For 10-byte and 16-byte SCSI R/W commands, transfer | |
4782ac80 JZ |
711 | * length 0 means transfer 0 block of data. |
712 | * However, for ATA R/W commands, sector count 0 means | |
713 | * 256 or 65536 sectors, not 0 sectors as in SCSI. | |
714 | * | |
715 | * WARNING: one or two older ATA drives treat 0 as 0... | |
716 | */ | |
284231e4 VB |
717 | blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); |
718 | ||
b7a21b70 HTL |
719 | debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n", |
720 | is_write ? "write" : "read", (unsigned)lba, blocks); | |
284231e4 VB |
721 | |
722 | /* Preset the FIS */ | |
c8731115 | 723 | memset(fis, 0, sizeof(fis)); |
284231e4 VB |
724 | fis[0] = 0x27; /* Host to device FIS. */ |
725 | fis[1] = 1 << 7; /* Command FIS. */ | |
b7a21b70 | 726 | /* Command byte (read/write). */ |
fe1f808c | 727 | fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; |
4782ac80 | 728 | |
284231e4 VB |
729 | while (blocks) { |
730 | u16 now_blocks; /* number of blocks per iteration */ | |
731 | u32 transfer_size; /* number of bytes per iteration */ | |
732 | ||
b7a21b70 | 733 | now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); |
284231e4 | 734 | |
344ca0b4 | 735 | transfer_size = ATA_SECT_SIZE * now_blocks; |
284231e4 VB |
736 | if (transfer_size > user_buffer_size) { |
737 | printf("scsi_ahci: Error: buffer too small.\n"); | |
738 | return -EIO; | |
739 | } | |
740 | ||
fe1f808c WM |
741 | /* LBA48 SATA command but only use 32bit address range within |
742 | * that. The next smaller command range (28bit) is too small. | |
743 | */ | |
284231e4 VB |
744 | fis[4] = (lba >> 0) & 0xff; |
745 | fis[5] = (lba >> 8) & 0xff; | |
746 | fis[6] = (lba >> 16) & 0xff; | |
fe1f808c WM |
747 | fis[7] = 1 << 6; /* device reg: set LBA mode */ |
748 | fis[8] = ((lba >> 24) & 0xff); | |
749 | fis[3] = 0xe0; /* features */ | |
284231e4 VB |
750 | |
751 | /* Block (sector) count */ | |
752 | fis[12] = (now_blocks >> 0) & 0xff; | |
753 | fis[13] = (now_blocks >> 8) & 0xff; | |
754 | ||
b7a21b70 HTL |
755 | /* Read/Write from ahci */ |
756 | if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), | |
757 | user_buffer, user_buffer_size, | |
758 | is_write)) { | |
759 | debug("scsi_ahci: SCSI %s10 command failure.\n", | |
760 | is_write ? "WRITE" : "READ"); | |
284231e4 VB |
761 | return -EIO; |
762 | } | |
766b16fe MJ |
763 | |
764 | /* If this transaction is a write, do a following flush. | |
765 | * Writes in u-boot are so rare, and the logic to know when is | |
766 | * the last write and do a flush only there is sufficiently | |
767 | * difficult. Just do a flush after every write. This incurs, | |
768 | * usually, one extra flush when the rare writes do happen. | |
769 | */ | |
770 | if (is_write) { | |
771 | if (-EIO == ata_io_flush(pccb->target)) | |
772 | return -EIO; | |
773 | } | |
284231e4 VB |
774 | user_buffer += transfer_size; |
775 | user_buffer_size -= transfer_size; | |
776 | blocks -= now_blocks; | |
777 | lba += now_blocks; | |
4782ac80 JZ |
778 | } |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | ||
784 | /* | |
785 | * SCSI READ CAPACITY10 command operation. | |
786 | */ | |
787 | static int ata_scsiop_read_capacity10(ccb *pccb) | |
788 | { | |
cb6d0b72 | 789 | u32 cap; |
344ca0b4 | 790 | u64 cap64; |
19d1d41e | 791 | u32 block_size; |
4782ac80 | 792 | |
4a7cc0f2 | 793 | if (!ataid[pccb->target]) { |
4782ac80 | 794 | printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " |
4a7cc0f2 JL |
795 | "\tNo ATA info!\n" |
796 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); | |
4782ac80 JZ |
797 | return -EPERM; |
798 | } | |
799 | ||
344ca0b4 RH |
800 | cap64 = ata_id_n_sectors(ataid[pccb->target]); |
801 | if (cap64 > 0x100000000ULL) | |
802 | cap64 = 0xffffffff; | |
19d1d41e | 803 | |
344ca0b4 | 804 | cap = cpu_to_be32(cap64); |
cb6d0b72 | 805 | memcpy(pccb->pdata, &cap, sizeof(cap)); |
4782ac80 | 806 | |
19d1d41e GB |
807 | block_size = cpu_to_be32((u32)512); |
808 | memcpy(&pccb->pdata[4], &block_size, 4); | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | ||
814 | /* | |
815 | * SCSI READ CAPACITY16 command operation. | |
816 | */ | |
817 | static int ata_scsiop_read_capacity16(ccb *pccb) | |
818 | { | |
819 | u64 cap; | |
820 | u64 block_size; | |
821 | ||
822 | if (!ataid[pccb->target]) { | |
823 | printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " | |
824 | "\tNo ATA info!\n" | |
825 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); | |
826 | return -EPERM; | |
827 | } | |
828 | ||
344ca0b4 | 829 | cap = ata_id_n_sectors(ataid[pccb->target]); |
19d1d41e GB |
830 | cap = cpu_to_be64(cap); |
831 | memcpy(pccb->pdata, &cap, sizeof(cap)); | |
832 | ||
833 | block_size = cpu_to_be64((u64)512); | |
834 | memcpy(&pccb->pdata[8], &block_size, 8); | |
4782ac80 JZ |
835 | |
836 | return 0; | |
837 | } | |
838 | ||
839 | ||
840 | /* | |
841 | * SCSI TEST UNIT READY command operation. | |
842 | */ | |
843 | static int ata_scsiop_test_unit_ready(ccb *pccb) | |
844 | { | |
845 | return (ataid[pccb->target]) ? 0 : -EPERM; | |
846 | } | |
847 | ||
4a7cc0f2 | 848 | |
4782ac80 JZ |
849 | int scsi_exec(ccb *pccb) |
850 | { | |
851 | int ret; | |
852 | ||
4a7cc0f2 | 853 | switch (pccb->cmd[0]) { |
4782ac80 | 854 | case SCSI_READ10: |
b7a21b70 HTL |
855 | ret = ata_scsiop_read_write(pccb, 0); |
856 | break; | |
857 | case SCSI_WRITE10: | |
858 | ret = ata_scsiop_read_write(pccb, 1); | |
4782ac80 | 859 | break; |
19d1d41e | 860 | case SCSI_RD_CAPAC10: |
4782ac80 JZ |
861 | ret = ata_scsiop_read_capacity10(pccb); |
862 | break; | |
19d1d41e GB |
863 | case SCSI_RD_CAPAC16: |
864 | ret = ata_scsiop_read_capacity16(pccb); | |
865 | break; | |
4782ac80 JZ |
866 | case SCSI_TST_U_RDY: |
867 | ret = ata_scsiop_test_unit_ready(pccb); | |
868 | break; | |
869 | case SCSI_INQUIRY: | |
870 | ret = ata_scsiop_inquiry(pccb); | |
871 | break; | |
872 | default: | |
873 | printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); | |
472d5460 | 874 | return false; |
4782ac80 JZ |
875 | } |
876 | ||
4a7cc0f2 JL |
877 | if (ret) { |
878 | debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); | |
472d5460 | 879 | return false; |
4782ac80 | 880 | } |
472d5460 | 881 | return true; |
4782ac80 JZ |
882 | |
883 | } | |
884 | ||
885 | ||
886 | void scsi_low_level_init(int busdevfunc) | |
887 | { | |
888 | int i; | |
889 | u32 linkmap; | |
890 | ||
942e3143 | 891 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 892 | ahci_init_one(busdevfunc); |
942e3143 | 893 | #endif |
4782ac80 JZ |
894 | |
895 | linkmap = probe_ent->link_port_map; | |
896 | ||
6d0f6bcf | 897 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { |
4a7cc0f2 JL |
898 | if (((linkmap >> i) & 0x01)) { |
899 | if (ahci_port_start((u8) i)) { | |
900 | printf("Can not start port %d\n", i); | |
4782ac80 JZ |
901 | continue; |
902 | } | |
e81058c0 | 903 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
4a7cc0f2 | 904 | ahci_set_feature((u8) i); |
e81058c0 | 905 | #endif |
4782ac80 JZ |
906 | } |
907 | } | |
908 | } | |
909 | ||
942e3143 RH |
910 | #ifdef CONFIG_SCSI_AHCI_PLAT |
911 | int ahci_init(u32 base) | |
912 | { | |
913 | int i, rc = 0; | |
914 | u32 linkmap; | |
915 | ||
942e3143 | 916 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
d73763a4 RQ |
917 | if (!probe_ent) { |
918 | printf("%s: No memory for probe_ent\n", __func__); | |
919 | return -ENOMEM; | |
920 | } | |
921 | ||
942e3143 RH |
922 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); |
923 | ||
924 | probe_ent->host_flags = ATA_FLAG_SATA | |
925 | | ATA_FLAG_NO_LEGACY | |
926 | | ATA_FLAG_MMIO | |
927 | | ATA_FLAG_PIO_DMA | |
928 | | ATA_FLAG_NO_ATAPI; | |
929 | probe_ent->pio_mask = 0x1f; | |
930 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
931 | ||
932 | probe_ent->mmio_base = base; | |
933 | ||
934 | /* initialize adapter */ | |
935 | rc = ahci_host_init(probe_ent); | |
936 | if (rc) | |
937 | goto err_out; | |
938 | ||
939 | ahci_print_info(probe_ent); | |
940 | ||
941 | linkmap = probe_ent->link_port_map; | |
942 | ||
943 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { | |
944 | if (((linkmap >> i) & 0x01)) { | |
945 | if (ahci_port_start((u8) i)) { | |
946 | printf("Can not start port %d\n", i); | |
947 | continue; | |
948 | } | |
e81058c0 | 949 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
942e3143 | 950 | ahci_set_feature((u8) i); |
e81058c0 | 951 | #endif |
942e3143 RH |
952 | } |
953 | } | |
954 | err_out: | |
955 | return rc; | |
956 | } | |
c6f3d50b IC |
957 | |
958 | void __weak scsi_init(void) | |
959 | { | |
960 | } | |
961 | ||
942e3143 | 962 | #endif |
4782ac80 | 963 | |
766b16fe MJ |
964 | /* |
965 | * In the general case of generic rotating media it makes sense to have a | |
966 | * flush capability. It probably even makes sense in the case of SSDs because | |
967 | * one cannot always know for sure what kind of internal cache/flush mechanism | |
968 | * is embodied therein. At first it was planned to invoke this after the last | |
969 | * write to disk and before rebooting. In practice, knowing, a priori, which | |
970 | * is the last write is difficult. Because writing to the disk in u-boot is | |
971 | * very rare, this flush command will be invoked after every block write. | |
972 | */ | |
973 | static int ata_io_flush(u8 port) | |
974 | { | |
975 | u8 fis[20]; | |
976 | struct ahci_ioports *pp = &(probe_ent->port[port]); | |
977 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; | |
978 | u32 cmd_fis_len = 5; /* five dwords */ | |
979 | ||
980 | /* Preset the FIS */ | |
981 | memset(fis, 0, 20); | |
982 | fis[0] = 0x27; /* Host to device FIS. */ | |
983 | fis[1] = 1 << 7; /* Command FIS. */ | |
fe1f808c | 984 | fis[2] = ATA_CMD_FLUSH_EXT; |
766b16fe MJ |
985 | |
986 | memcpy((unsigned char *)pp->cmd_tbl, fis, 20); | |
987 | ahci_fill_cmd_slot(pp, cmd_fis_len); | |
988 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); | |
989 | ||
990 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, | |
991 | WAIT_MS_FLUSH, 0x1)) { | |
992 | debug("scsi_ahci: flush command timeout on port %d.\n", port); | |
993 | return -EIO; | |
994 | } | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
999 | ||
4782ac80 JZ |
1000 | void scsi_bus_reset(void) |
1001 | { | |
4a7cc0f2 | 1002 | /*Not implement*/ |
4782ac80 JZ |
1003 | } |
1004 | ||
1005 | ||
4a7cc0f2 | 1006 | void scsi_print_error(ccb * pccb) |
4782ac80 | 1007 | { |
4a7cc0f2 | 1008 | /*The ahci error info can be read in the ahci driver*/ |
4782ac80 | 1009 | } |