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4782ac80 | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
4782ac80 JZ |
3 | * Author: Jason Jin<Jason.jin@freescale.com> |
4 | * Zhang Wei<wei.zhang@freescale.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | * | |
24 | * with the reference on libata and ahci drvier in kernel | |
25 | * | |
26 | */ | |
27 | #include <common.h> | |
28 | ||
4782ac80 JZ |
29 | #include <command.h> |
30 | #include <pci.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/errno.h> | |
33 | #include <asm/io.h> | |
34 | #include <malloc.h> | |
35 | #include <scsi.h> | |
36 | #include <ata.h> | |
37 | #include <linux/ctype.h> | |
38 | #include <ahci.h> | |
39 | ||
40 | struct ahci_probe_ent *probe_ent = NULL; | |
41 | hd_driveid_t *ataid[AHCI_MAX_PORTS]; | |
42 | ||
4a7cc0f2 JL |
43 | #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) |
44 | ||
284231e4 VB |
45 | /* |
46 | * Some controllers limit number of blocks they can read at once. Contemporary | |
47 | * SSD devices work much faster if the read size is aligned to a power of 2. | |
48 | * Let's set default to 128 and allowing to be overwritten if needed. | |
49 | */ | |
50 | #ifndef MAX_SATA_BLOCKS_READ | |
51 | #define MAX_SATA_BLOCKS_READ 0x80 | |
52 | #endif | |
4782ac80 JZ |
53 | |
54 | static inline u32 ahci_port_base(u32 base, u32 port) | |
55 | { | |
56 | return base + 0x100 + (port * 0x80); | |
57 | } | |
58 | ||
59 | ||
60 | static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, | |
61 | unsigned int port_idx) | |
62 | { | |
63 | base = ahci_port_base(base, port_idx); | |
64 | ||
4a7cc0f2 JL |
65 | port->cmd_addr = base; |
66 | port->scr_addr = base + PORT_SCR; | |
4782ac80 JZ |
67 | } |
68 | ||
69 | ||
70 | #define msleep(a) udelay(a * 1000) | |
4a7cc0f2 JL |
71 | |
72 | static int waiting_for_cmd_completed(volatile u8 *offset, | |
73 | int timeout_msec, | |
74 | u32 sign) | |
4782ac80 JZ |
75 | { |
76 | int i; | |
77 | u32 status; | |
4a7cc0f2 JL |
78 | |
79 | for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) | |
4782ac80 JZ |
80 | msleep(1); |
81 | ||
4a7cc0f2 | 82 | return (i < timeout_msec) ? 0 : -1; |
4782ac80 JZ |
83 | } |
84 | ||
85 | ||
86 | static int ahci_host_init(struct ahci_probe_ent *probe_ent) | |
87 | { | |
942e3143 | 88 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 89 | pci_dev_t pdev = probe_ent->dev; |
942e3143 RH |
90 | u16 tmp16; |
91 | unsigned short vendor; | |
92 | #endif | |
4782ac80 JZ |
93 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
94 | u32 tmp, cap_save; | |
4782ac80 | 95 | int i, j; |
4a7cc0f2 | 96 | volatile u8 *port_mmio; |
4782ac80 | 97 | |
284231e4 VB |
98 | debug("ahci_host_init: start\n"); |
99 | ||
4782ac80 | 100 | cap_save = readl(mmio + HOST_CAP); |
4a7cc0f2 | 101 | cap_save &= ((1 << 28) | (1 << 17)); |
4782ac80 JZ |
102 | cap_save |= (1 << 27); |
103 | ||
104 | /* global controller reset */ | |
105 | tmp = readl(mmio + HOST_CTL); | |
106 | if ((tmp & HOST_RESET) == 0) | |
107 | writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); | |
108 | ||
109 | /* reset must complete within 1 second, or | |
110 | * the hardware should be considered fried. | |
111 | */ | |
9a65b875 SR |
112 | i = 1000; |
113 | do { | |
114 | udelay(1000); | |
115 | tmp = readl(mmio + HOST_CTL); | |
116 | if (!i--) { | |
117 | debug("controller reset failed (0x%x)\n", tmp); | |
118 | return -1; | |
119 | } | |
120 | } while (tmp & HOST_RESET); | |
4782ac80 JZ |
121 | |
122 | writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); | |
123 | writel(cap_save, mmio + HOST_CAP); | |
124 | writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); | |
125 | ||
942e3143 | 126 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 JZ |
127 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
128 | ||
129 | if (vendor == PCI_VENDOR_ID_INTEL) { | |
130 | u16 tmp16; | |
131 | pci_read_config_word(pdev, 0x92, &tmp16); | |
132 | tmp16 |= 0xf; | |
133 | pci_write_config_word(pdev, 0x92, tmp16); | |
134 | } | |
942e3143 | 135 | #endif |
4782ac80 JZ |
136 | probe_ent->cap = readl(mmio + HOST_CAP); |
137 | probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); | |
138 | probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; | |
139 | ||
140 | debug("cap 0x%x port_map 0x%x n_ports %d\n", | |
4a7cc0f2 | 141 | probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); |
4782ac80 | 142 | |
284231e4 VB |
143 | if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) |
144 | probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; | |
145 | ||
4782ac80 | 146 | for (i = 0; i < probe_ent->n_ports; i++) { |
4a7cc0f2 JL |
147 | probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); |
148 | port_mmio = (u8 *) probe_ent->port[i].port_mmio; | |
149 | ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); | |
4782ac80 JZ |
150 | |
151 | /* make sure port is not active */ | |
152 | tmp = readl(port_mmio + PORT_CMD); | |
153 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
154 | PORT_CMD_FIS_RX | PORT_CMD_START)) { | |
7ba7917c | 155 | debug("Port %d is active. Deactivating.\n", i); |
4782ac80 JZ |
156 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
157 | PORT_CMD_FIS_RX | PORT_CMD_START); | |
158 | writel_with_flush(tmp, port_mmio + PORT_CMD); | |
159 | ||
160 | /* spec says 500 msecs for each bit, so | |
161 | * this is slightly incorrect. | |
162 | */ | |
163 | msleep(500); | |
164 | } | |
165 | ||
7ba7917c | 166 | debug("Spinning up port %d... ", i); |
4782ac80 JZ |
167 | writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); |
168 | ||
169 | j = 0; | |
9a65b875 | 170 | while (j < 1000) { |
4782ac80 JZ |
171 | tmp = readl(port_mmio + PORT_SCR_STAT); |
172 | if ((tmp & 0xf) == 0x3) | |
173 | break; | |
9a65b875 | 174 | udelay(1000); |
4782ac80 JZ |
175 | j++; |
176 | } | |
9a65b875 SR |
177 | if (j == 1000) |
178 | debug("timeout.\n"); | |
179 | else | |
180 | debug("ok.\n"); | |
4782ac80 JZ |
181 | |
182 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
183 | debug("PORT_SCR_ERR 0x%x\n", tmp); | |
184 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
185 | ||
186 | /* ack any pending irq events for this port */ | |
187 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
188 | debug("PORT_IRQ_STAT 0x%x\n", tmp); | |
189 | if (tmp) | |
190 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
191 | ||
192 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
193 | ||
194 | /* set irq mask (enables interrupts) */ | |
195 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
196 | ||
4a7cc0f2 | 197 | /*register linkup ports */ |
4782ac80 | 198 | tmp = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
199 | debug("Port %d status: 0x%x\n", i, tmp); |
200 | if ((tmp & 0xf) == 0x03) | |
201 | probe_ent->link_port_map |= (0x01 << i); | |
4782ac80 JZ |
202 | } |
203 | ||
204 | tmp = readl(mmio + HOST_CTL); | |
205 | debug("HOST_CTL 0x%x\n", tmp); | |
206 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
207 | tmp = readl(mmio + HOST_CTL); | |
208 | debug("HOST_CTL 0x%x\n", tmp); | |
942e3143 | 209 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 JZ |
210 | pci_read_config_word(pdev, PCI_COMMAND, &tmp16); |
211 | tmp |= PCI_COMMAND_MASTER; | |
212 | pci_write_config_word(pdev, PCI_COMMAND, tmp16); | |
942e3143 | 213 | #endif |
4782ac80 JZ |
214 | return 0; |
215 | } | |
216 | ||
217 | ||
218 | static void ahci_print_info(struct ahci_probe_ent *probe_ent) | |
219 | { | |
942e3143 | 220 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 221 | pci_dev_t pdev = probe_ent->dev; |
942e3143 RH |
222 | u16 cc; |
223 | #endif | |
4a7cc0f2 | 224 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
4782ac80 JZ |
225 | u32 vers, cap, impl, speed; |
226 | const char *speed_s; | |
4782ac80 JZ |
227 | const char *scc_s; |
228 | ||
229 | vers = readl(mmio + HOST_VERSION); | |
230 | cap = probe_ent->cap; | |
231 | impl = probe_ent->port_map; | |
232 | ||
233 | speed = (cap >> 20) & 0xf; | |
234 | if (speed == 1) | |
235 | speed_s = "1.5"; | |
236 | else if (speed == 2) | |
237 | speed_s = "3"; | |
238 | else | |
239 | speed_s = "?"; | |
240 | ||
942e3143 RH |
241 | #ifdef CONFIG_SCSI_AHCI_PLAT |
242 | scc_s = "SATA"; | |
243 | #else | |
4782ac80 JZ |
244 | pci_read_config_word(pdev, 0x0a, &cc); |
245 | if (cc == 0x0101) | |
246 | scc_s = "IDE"; | |
247 | else if (cc == 0x0106) | |
248 | scc_s = "SATA"; | |
249 | else if (cc == 0x0104) | |
250 | scc_s = "RAID"; | |
251 | else | |
252 | scc_s = "unknown"; | |
942e3143 | 253 | #endif |
4a7cc0f2 JL |
254 | printf("AHCI %02x%02x.%02x%02x " |
255 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", | |
256 | (vers >> 24) & 0xff, | |
257 | (vers >> 16) & 0xff, | |
258 | (vers >> 8) & 0xff, | |
259 | vers & 0xff, | |
260 | ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); | |
4782ac80 JZ |
261 | |
262 | printf("flags: " | |
4a7cc0f2 JL |
263 | "%s%s%s%s%s%s" |
264 | "%s%s%s%s%s%s%s\n", | |
265 | cap & (1 << 31) ? "64bit " : "", | |
266 | cap & (1 << 30) ? "ncq " : "", | |
267 | cap & (1 << 28) ? "ilck " : "", | |
268 | cap & (1 << 27) ? "stag " : "", | |
269 | cap & (1 << 26) ? "pm " : "", | |
270 | cap & (1 << 25) ? "led " : "", | |
271 | cap & (1 << 24) ? "clo " : "", | |
272 | cap & (1 << 19) ? "nz " : "", | |
273 | cap & (1 << 18) ? "only " : "", | |
274 | cap & (1 << 17) ? "pmp " : "", | |
275 | cap & (1 << 15) ? "pio " : "", | |
276 | cap & (1 << 14) ? "slum " : "", | |
277 | cap & (1 << 13) ? "part " : ""); | |
4782ac80 JZ |
278 | } |
279 | ||
942e3143 | 280 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4a7cc0f2 | 281 | static int ahci_init_one(pci_dev_t pdev) |
4782ac80 | 282 | { |
63cec581 | 283 | u16 vendor; |
4782ac80 JZ |
284 | int rc; |
285 | ||
4a7cc0f2 | 286 | memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); |
4782ac80 | 287 | |
594e7983 ES |
288 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
289 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); | |
4782ac80 JZ |
290 | probe_ent->dev = pdev; |
291 | ||
4a7cc0f2 JL |
292 | probe_ent->host_flags = ATA_FLAG_SATA |
293 | | ATA_FLAG_NO_LEGACY | |
294 | | ATA_FLAG_MMIO | |
295 | | ATA_FLAG_PIO_DMA | |
296 | | ATA_FLAG_NO_ATAPI; | |
297 | probe_ent->pio_mask = 0x1f; | |
298 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
4782ac80 | 299 | |
284231e4 VB |
300 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base); |
301 | debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base); | |
4782ac80 JZ |
302 | |
303 | /* Take from kernel: | |
304 | * JMicron-specific fixup: | |
305 | * make sure we're in AHCI mode | |
306 | */ | |
307 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); | |
4a7cc0f2 | 308 | if (vendor == 0x197b) |
4782ac80 JZ |
309 | pci_write_config_byte(pdev, 0x41, 0xa1); |
310 | ||
311 | /* initialize adapter */ | |
312 | rc = ahci_host_init(probe_ent); | |
313 | if (rc) | |
314 | goto err_out; | |
315 | ||
316 | ahci_print_info(probe_ent); | |
317 | ||
318 | return 0; | |
319 | ||
4a7cc0f2 | 320 | err_out: |
4782ac80 JZ |
321 | return rc; |
322 | } | |
942e3143 | 323 | #endif |
4782ac80 JZ |
324 | |
325 | #define MAX_DATA_BYTE_COUNT (4*1024*1024) | |
4a7cc0f2 | 326 | |
4782ac80 JZ |
327 | static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) |
328 | { | |
4782ac80 JZ |
329 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
330 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; | |
331 | u32 sg_count; | |
332 | int i; | |
333 | ||
334 | sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; | |
4a7cc0f2 | 335 | if (sg_count > AHCI_MAX_SG) { |
4782ac80 JZ |
336 | printf("Error:Too much sg!\n"); |
337 | return -1; | |
338 | } | |
339 | ||
4a7cc0f2 JL |
340 | for (i = 0; i < sg_count; i++) { |
341 | ahci_sg->addr = | |
342 | cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); | |
4782ac80 | 343 | ahci_sg->addr_hi = 0; |
4a7cc0f2 JL |
344 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & |
345 | (buf_len < MAX_DATA_BYTE_COUNT | |
346 | ? (buf_len - 1) | |
347 | : (MAX_DATA_BYTE_COUNT - 1))); | |
4782ac80 JZ |
348 | ahci_sg++; |
349 | buf_len -= MAX_DATA_BYTE_COUNT; | |
350 | } | |
351 | ||
352 | return sg_count; | |
353 | } | |
354 | ||
355 | ||
356 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) | |
357 | { | |
358 | pp->cmd_slot->opts = cpu_to_le32(opts); | |
359 | pp->cmd_slot->status = 0; | |
360 | pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); | |
361 | pp->cmd_slot->tbl_addr_hi = 0; | |
362 | } | |
363 | ||
364 | ||
365 | static void ahci_set_feature(u8 port) | |
366 | { | |
4782ac80 | 367 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 JL |
368 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
369 | u32 cmd_fis_len = 5; /* five dwords */ | |
4782ac80 JZ |
370 | u8 fis[20]; |
371 | ||
4a7cc0f2 JL |
372 | /*set feature */ |
373 | memset(fis, 0, 20); | |
4782ac80 JZ |
374 | fis[0] = 0x27; |
375 | fis[1] = 1 << 7; | |
376 | fis[2] = ATA_CMD_SETF; | |
377 | fis[3] = SETFEATURES_XFER; | |
378 | fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; | |
379 | ||
4a7cc0f2 | 380 | memcpy((unsigned char *)pp->cmd_tbl, fis, 20); |
4782ac80 JZ |
381 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
382 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
383 | readl(port_mmio + PORT_CMD_ISSUE); | |
384 | ||
4a7cc0f2 | 385 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { |
4782ac80 JZ |
386 | printf("set feature error!\n"); |
387 | } | |
388 | } | |
389 | ||
390 | ||
391 | static int ahci_port_start(u8 port) | |
392 | { | |
4782ac80 | 393 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 | 394 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
4782ac80 JZ |
395 | u32 port_status; |
396 | u32 mem; | |
397 | ||
4a7cc0f2 | 398 | debug("Enter start port: %d\n", port); |
4782ac80 | 399 | port_status = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
400 | debug("Port %d status: %x\n", port, port_status); |
401 | if ((port_status & 0xf) != 0x03) { | |
4782ac80 JZ |
402 | printf("No Link on this port!\n"); |
403 | return -1; | |
404 | } | |
405 | ||
4a7cc0f2 | 406 | mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); |
4782ac80 JZ |
407 | if (!mem) { |
408 | free(pp); | |
409 | printf("No mem for table!\n"); | |
410 | return -ENOMEM; | |
411 | } | |
412 | ||
4a7cc0f2 JL |
413 | mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ |
414 | memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
4782ac80 | 415 | |
4782ac80 JZ |
416 | /* |
417 | * First item in chunk of DMA memory: 32-slot command table, | |
418 | * 32 bytes each in size | |
419 | */ | |
420 | pp->cmd_slot = (struct ahci_cmd_hdr *)mem; | |
284231e4 | 421 | debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); |
4782ac80 | 422 | mem += (AHCI_CMD_SLOT_SZ + 224); |
4a7cc0f2 | 423 | |
4782ac80 JZ |
424 | /* |
425 | * Second item: Received-FIS area | |
426 | */ | |
427 | pp->rx_fis = mem; | |
4782ac80 | 428 | mem += AHCI_RX_FIS_SZ; |
4a7cc0f2 | 429 | |
4782ac80 JZ |
430 | /* |
431 | * Third item: data area for storing a single command | |
432 | * and its scatter-gather table | |
433 | */ | |
434 | pp->cmd_tbl = mem; | |
4a7cc0f2 | 435 | debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); |
4782ac80 JZ |
436 | |
437 | mem += AHCI_CMD_TBL_HDR; | |
438 | pp->cmd_tbl_sg = (struct ahci_sg *)mem; | |
439 | ||
4a7cc0f2 | 440 | writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); |
4782ac80 JZ |
441 | |
442 | writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); | |
443 | ||
444 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | | |
4a7cc0f2 JL |
445 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
446 | PORT_CMD_START, port_mmio + PORT_CMD); | |
4782ac80 | 447 | |
4a7cc0f2 | 448 | debug("Exit start port %d\n", port); |
4782ac80 JZ |
449 | |
450 | return 0; | |
451 | } | |
452 | ||
453 | ||
4a7cc0f2 JL |
454 | static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, |
455 | int buf_len) | |
4782ac80 JZ |
456 | { |
457 | ||
4a7cc0f2 JL |
458 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
459 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; | |
4782ac80 JZ |
460 | u32 opts; |
461 | u32 port_status; | |
462 | int sg_count; | |
463 | ||
4a7cc0f2 | 464 | debug("Enter get_ahci_device_data: for port %d\n", port); |
4782ac80 | 465 | |
4a7cc0f2 | 466 | if (port > probe_ent->n_ports) { |
4782ac80 JZ |
467 | printf("Invaild port number %d\n", port); |
468 | return -1; | |
469 | } | |
470 | ||
471 | port_status = readl(port_mmio + PORT_SCR_STAT); | |
4a7cc0f2 JL |
472 | if ((port_status & 0xf) != 0x03) { |
473 | debug("No Link on port %d!\n", port); | |
4782ac80 JZ |
474 | return -1; |
475 | } | |
476 | ||
477 | memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); | |
478 | ||
4a7cc0f2 JL |
479 | sg_count = ahci_fill_sg(port, buf, buf_len); |
480 | opts = (fis_len >> 2) | (sg_count << 16); | |
4782ac80 JZ |
481 | ahci_fill_cmd_slot(pp, opts); |
482 | ||
483 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); | |
484 | ||
485 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { | |
486 | printf("timeout exit!\n"); | |
487 | return -1; | |
488 | } | |
489 | debug("get_ahci_device_data: %d byte transferred.\n", | |
4a7cc0f2 | 490 | pp->cmd_slot->status); |
4782ac80 JZ |
491 | |
492 | return 0; | |
493 | } | |
494 | ||
495 | ||
496 | static char *ata_id_strcpy(u16 *target, u16 *src, int len) | |
497 | { | |
498 | int i; | |
4a7cc0f2 | 499 | for (i = 0; i < len / 2; i++) |
e5a6c79d | 500 | target[i] = swab16(src[i]); |
4782ac80 JZ |
501 | return (char *)target; |
502 | } | |
503 | ||
504 | ||
505 | static void dump_ataid(hd_driveid_t *ataid) | |
506 | { | |
507 | debug("(49)ataid->capability = 0x%x\n", ataid->capability); | |
508 | debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); | |
509 | debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); | |
510 | debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); | |
511 | debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); | |
512 | debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); | |
513 | debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); | |
514 | debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); | |
515 | debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); | |
516 | debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); | |
517 | debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); | |
518 | debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); | |
519 | debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); | |
520 | debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); | |
521 | debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); | |
522 | } | |
523 | ||
4a7cc0f2 | 524 | |
4782ac80 JZ |
525 | /* |
526 | * SCSI INQUIRY command operation. | |
527 | */ | |
528 | static int ata_scsiop_inquiry(ccb *pccb) | |
529 | { | |
530 | u8 hdr[] = { | |
531 | 0, | |
532 | 0, | |
4a7cc0f2 | 533 | 0x5, /* claim SPC-3 version compatibility */ |
4782ac80 JZ |
534 | 2, |
535 | 95 - 4, | |
536 | }; | |
537 | u8 fis[20]; | |
538 | u8 *tmpid; | |
539 | u8 port; | |
540 | ||
541 | /* Clean ccb data buffer */ | |
542 | memset(pccb->pdata, 0, pccb->datalen); | |
543 | ||
544 | memcpy(pccb->pdata, hdr, sizeof(hdr)); | |
545 | ||
4a7cc0f2 | 546 | if (pccb->datalen <= 35) |
4782ac80 JZ |
547 | return 0; |
548 | ||
549 | memset(fis, 0, 20); | |
550 | /* Construct the FIS */ | |
4a7cc0f2 JL |
551 | fis[0] = 0x27; /* Host to device FIS. */ |
552 | fis[1] = 1 << 7; /* Command FIS. */ | |
553 | fis[2] = ATA_CMD_IDENT; /* Command byte. */ | |
4782ac80 JZ |
554 | |
555 | /* Read id from sata */ | |
556 | port = pccb->target; | |
4a7cc0f2 | 557 | if (!(tmpid = malloc(sizeof(hd_driveid_t)))) |
4782ac80 JZ |
558 | return -ENOMEM; |
559 | ||
4a7cc0f2 JL |
560 | if (get_ahci_device_data(port, (u8 *) & fis, 20, |
561 | tmpid, sizeof(hd_driveid_t))) { | |
4782ac80 JZ |
562 | debug("scsi_ahci: SCSI inquiry command failure.\n"); |
563 | return -EIO; | |
564 | } | |
565 | ||
4a7cc0f2 | 566 | if (ataid[port]) |
4782ac80 | 567 | free(ataid[port]); |
4a7cc0f2 | 568 | ataid[port] = (hd_driveid_t *) tmpid; |
4782ac80 JZ |
569 | |
570 | memcpy(&pccb->pdata[8], "ATA ", 8); | |
4a7cc0f2 JL |
571 | ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); |
572 | ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); | |
4782ac80 JZ |
573 | |
574 | dump_ataid(ataid[port]); | |
575 | return 0; | |
576 | } | |
577 | ||
578 | ||
579 | /* | |
580 | * SCSI READ10 command operation. | |
581 | */ | |
4a7cc0f2 | 582 | static int ata_scsiop_read10(ccb * pccb) |
4782ac80 | 583 | { |
284231e4 VB |
584 | u32 lba = 0; |
585 | u16 blocks = 0; | |
4782ac80 | 586 | u8 fis[20]; |
284231e4 VB |
587 | u8 *user_buffer = pccb->pdata; |
588 | u32 user_buffer_size = pccb->datalen; | |
4782ac80 | 589 | |
284231e4 VB |
590 | /* Retrieve the base LBA number from the ccb structure. */ |
591 | memcpy(&lba, pccb->cmd + 2, sizeof(lba)); | |
592 | lba = be32_to_cpu(lba); | |
4782ac80 | 593 | |
284231e4 VB |
594 | /* |
595 | * And the number of blocks. | |
596 | * | |
597 | * For 10-byte and 16-byte SCSI R/W commands, transfer | |
4782ac80 JZ |
598 | * length 0 means transfer 0 block of data. |
599 | * However, for ATA R/W commands, sector count 0 means | |
600 | * 256 or 65536 sectors, not 0 sectors as in SCSI. | |
601 | * | |
602 | * WARNING: one or two older ATA drives treat 0 as 0... | |
603 | */ | |
284231e4 VB |
604 | blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); |
605 | ||
606 | debug("scsi_ahci: read %d blocks starting from lba 0x%x\n", | |
607 | (unsigned)lba, blocks); | |
608 | ||
609 | /* Preset the FIS */ | |
4782ac80 | 610 | memset(fis, 0, 20); |
284231e4 VB |
611 | fis[0] = 0x27; /* Host to device FIS. */ |
612 | fis[1] = 1 << 7; /* Command FIS. */ | |
613 | fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ | |
4782ac80 | 614 | |
284231e4 VB |
615 | while (blocks) { |
616 | u16 now_blocks; /* number of blocks per iteration */ | |
617 | u32 transfer_size; /* number of bytes per iteration */ | |
618 | ||
619 | now_blocks = min(MAX_SATA_BLOCKS_READ, blocks); | |
620 | ||
621 | transfer_size = ATA_BLOCKSIZE * now_blocks; | |
622 | if (transfer_size > user_buffer_size) { | |
623 | printf("scsi_ahci: Error: buffer too small.\n"); | |
624 | return -EIO; | |
625 | } | |
626 | ||
627 | /* LBA address, only support LBA28 in this driver */ | |
628 | fis[4] = (lba >> 0) & 0xff; | |
629 | fis[5] = (lba >> 8) & 0xff; | |
630 | fis[6] = (lba >> 16) & 0xff; | |
631 | fis[7] = ((lba >> 24) & 0xf) | 0xe0; | |
632 | ||
633 | /* Block (sector) count */ | |
634 | fis[12] = (now_blocks >> 0) & 0xff; | |
635 | fis[13] = (now_blocks >> 8) & 0xff; | |
636 | ||
637 | /* Read from ahci */ | |
638 | if (get_ahci_device_data(pccb->target, (u8 *) &fis, sizeof(fis), | |
639 | user_buffer, user_buffer_size)) { | |
640 | debug("scsi_ahci: SCSI READ10 command failure.\n"); | |
641 | return -EIO; | |
642 | } | |
643 | user_buffer += transfer_size; | |
644 | user_buffer_size -= transfer_size; | |
645 | blocks -= now_blocks; | |
646 | lba += now_blocks; | |
4782ac80 JZ |
647 | } |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
652 | ||
653 | /* | |
654 | * SCSI READ CAPACITY10 command operation. | |
655 | */ | |
656 | static int ata_scsiop_read_capacity10(ccb *pccb) | |
657 | { | |
cb6d0b72 | 658 | u32 cap; |
4782ac80 | 659 | |
4a7cc0f2 | 660 | if (!ataid[pccb->target]) { |
4782ac80 | 661 | printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " |
4a7cc0f2 JL |
662 | "\tNo ATA info!\n" |
663 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); | |
4782ac80 JZ |
664 | return -EPERM; |
665 | } | |
666 | ||
284231e4 | 667 | cap = be32_to_cpu(ataid[pccb->target]->lba_capacity); |
cb6d0b72 | 668 | memcpy(pccb->pdata, &cap, sizeof(cap)); |
4782ac80 | 669 | |
cb6d0b72 KG |
670 | pccb->pdata[4] = pccb->pdata[5] = 0; |
671 | pccb->pdata[6] = 512 >> 8; | |
672 | pccb->pdata[7] = 512 & 0xff; | |
4782ac80 JZ |
673 | |
674 | return 0; | |
675 | } | |
676 | ||
677 | ||
678 | /* | |
679 | * SCSI TEST UNIT READY command operation. | |
680 | */ | |
681 | static int ata_scsiop_test_unit_ready(ccb *pccb) | |
682 | { | |
683 | return (ataid[pccb->target]) ? 0 : -EPERM; | |
684 | } | |
685 | ||
4a7cc0f2 | 686 | |
4782ac80 JZ |
687 | int scsi_exec(ccb *pccb) |
688 | { | |
689 | int ret; | |
690 | ||
4a7cc0f2 | 691 | switch (pccb->cmd[0]) { |
4782ac80 JZ |
692 | case SCSI_READ10: |
693 | ret = ata_scsiop_read10(pccb); | |
694 | break; | |
695 | case SCSI_RD_CAPAC: | |
696 | ret = ata_scsiop_read_capacity10(pccb); | |
697 | break; | |
698 | case SCSI_TST_U_RDY: | |
699 | ret = ata_scsiop_test_unit_ready(pccb); | |
700 | break; | |
701 | case SCSI_INQUIRY: | |
702 | ret = ata_scsiop_inquiry(pccb); | |
703 | break; | |
704 | default: | |
705 | printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); | |
706 | return FALSE; | |
707 | } | |
708 | ||
4a7cc0f2 JL |
709 | if (ret) { |
710 | debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); | |
4782ac80 JZ |
711 | return FALSE; |
712 | } | |
713 | return TRUE; | |
714 | ||
715 | } | |
716 | ||
717 | ||
718 | void scsi_low_level_init(int busdevfunc) | |
719 | { | |
720 | int i; | |
721 | u32 linkmap; | |
722 | ||
942e3143 | 723 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 724 | ahci_init_one(busdevfunc); |
942e3143 | 725 | #endif |
4782ac80 JZ |
726 | |
727 | linkmap = probe_ent->link_port_map; | |
728 | ||
6d0f6bcf | 729 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { |
4a7cc0f2 JL |
730 | if (((linkmap >> i) & 0x01)) { |
731 | if (ahci_port_start((u8) i)) { | |
732 | printf("Can not start port %d\n", i); | |
4782ac80 JZ |
733 | continue; |
734 | } | |
4a7cc0f2 | 735 | ahci_set_feature((u8) i); |
4782ac80 JZ |
736 | } |
737 | } | |
738 | } | |
739 | ||
942e3143 RH |
740 | #ifdef CONFIG_SCSI_AHCI_PLAT |
741 | int ahci_init(u32 base) | |
742 | { | |
743 | int i, rc = 0; | |
744 | u32 linkmap; | |
745 | ||
746 | memset(ataid, 0, sizeof(ataid)); | |
747 | ||
748 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); | |
749 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); | |
750 | ||
751 | probe_ent->host_flags = ATA_FLAG_SATA | |
752 | | ATA_FLAG_NO_LEGACY | |
753 | | ATA_FLAG_MMIO | |
754 | | ATA_FLAG_PIO_DMA | |
755 | | ATA_FLAG_NO_ATAPI; | |
756 | probe_ent->pio_mask = 0x1f; | |
757 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
758 | ||
759 | probe_ent->mmio_base = base; | |
760 | ||
761 | /* initialize adapter */ | |
762 | rc = ahci_host_init(probe_ent); | |
763 | if (rc) | |
764 | goto err_out; | |
765 | ||
766 | ahci_print_info(probe_ent); | |
767 | ||
768 | linkmap = probe_ent->link_port_map; | |
769 | ||
770 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { | |
771 | if (((linkmap >> i) & 0x01)) { | |
772 | if (ahci_port_start((u8) i)) { | |
773 | printf("Can not start port %d\n", i); | |
774 | continue; | |
775 | } | |
776 | ahci_set_feature((u8) i); | |
777 | } | |
778 | } | |
779 | err_out: | |
780 | return rc; | |
781 | } | |
782 | #endif | |
4782ac80 JZ |
783 | |
784 | void scsi_bus_reset(void) | |
785 | { | |
4a7cc0f2 | 786 | /*Not implement*/ |
4782ac80 JZ |
787 | } |
788 | ||
789 | ||
4a7cc0f2 | 790 | void scsi_print_error(ccb * pccb) |
4782ac80 | 791 | { |
4a7cc0f2 | 792 | /*The ahci error info can be read in the ahci driver*/ |
4782ac80 | 793 | } |