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4782ac80 | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
4782ac80 JZ |
3 | * Author: Jason Jin<Jason.jin@freescale.com> |
4 | * Zhang Wei<wei.zhang@freescale.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | * | |
24 | * with the reference on libata and ahci drvier in kernel | |
25 | * | |
26 | */ | |
27 | #include <common.h> | |
28 | ||
4782ac80 JZ |
29 | #include <command.h> |
30 | #include <pci.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/errno.h> | |
33 | #include <asm/io.h> | |
34 | #include <malloc.h> | |
35 | #include <scsi.h> | |
36 | #include <ata.h> | |
37 | #include <linux/ctype.h> | |
38 | #include <ahci.h> | |
39 | ||
40 | struct ahci_probe_ent *probe_ent = NULL; | |
41 | hd_driveid_t *ataid[AHCI_MAX_PORTS]; | |
42 | ||
4a7cc0f2 JL |
43 | #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) |
44 | ||
284231e4 VB |
45 | /* |
46 | * Some controllers limit number of blocks they can read at once. Contemporary | |
47 | * SSD devices work much faster if the read size is aligned to a power of 2. | |
48 | * Let's set default to 128 and allowing to be overwritten if needed. | |
49 | */ | |
50 | #ifndef MAX_SATA_BLOCKS_READ | |
51 | #define MAX_SATA_BLOCKS_READ 0x80 | |
52 | #endif | |
4782ac80 JZ |
53 | |
54 | static inline u32 ahci_port_base(u32 base, u32 port) | |
55 | { | |
56 | return base + 0x100 + (port * 0x80); | |
57 | } | |
58 | ||
59 | ||
60 | static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, | |
61 | unsigned int port_idx) | |
62 | { | |
63 | base = ahci_port_base(base, port_idx); | |
64 | ||
4a7cc0f2 JL |
65 | port->cmd_addr = base; |
66 | port->scr_addr = base + PORT_SCR; | |
4782ac80 JZ |
67 | } |
68 | ||
69 | ||
70 | #define msleep(a) udelay(a * 1000) | |
71 | #define ssleep(a) msleep(a * 1000) | |
4a7cc0f2 JL |
72 | |
73 | static int waiting_for_cmd_completed(volatile u8 *offset, | |
74 | int timeout_msec, | |
75 | u32 sign) | |
4782ac80 JZ |
76 | { |
77 | int i; | |
78 | u32 status; | |
4a7cc0f2 JL |
79 | |
80 | for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) | |
4782ac80 JZ |
81 | msleep(1); |
82 | ||
4a7cc0f2 | 83 | return (i < timeout_msec) ? 0 : -1; |
4782ac80 JZ |
84 | } |
85 | ||
86 | ||
87 | static int ahci_host_init(struct ahci_probe_ent *probe_ent) | |
88 | { | |
942e3143 | 89 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 90 | pci_dev_t pdev = probe_ent->dev; |
942e3143 RH |
91 | u16 tmp16; |
92 | unsigned short vendor; | |
93 | #endif | |
4782ac80 JZ |
94 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
95 | u32 tmp, cap_save; | |
4782ac80 | 96 | int i, j; |
4a7cc0f2 | 97 | volatile u8 *port_mmio; |
4782ac80 | 98 | |
284231e4 VB |
99 | debug("ahci_host_init: start\n"); |
100 | ||
4782ac80 | 101 | cap_save = readl(mmio + HOST_CAP); |
4a7cc0f2 | 102 | cap_save &= ((1 << 28) | (1 << 17)); |
4782ac80 JZ |
103 | cap_save |= (1 << 27); |
104 | ||
105 | /* global controller reset */ | |
106 | tmp = readl(mmio + HOST_CTL); | |
107 | if ((tmp & HOST_RESET) == 0) | |
108 | writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); | |
109 | ||
110 | /* reset must complete within 1 second, or | |
111 | * the hardware should be considered fried. | |
112 | */ | |
9a65b875 SR |
113 | i = 1000; |
114 | do { | |
115 | udelay(1000); | |
116 | tmp = readl(mmio + HOST_CTL); | |
117 | if (!i--) { | |
118 | debug("controller reset failed (0x%x)\n", tmp); | |
119 | return -1; | |
120 | } | |
121 | } while (tmp & HOST_RESET); | |
4782ac80 JZ |
122 | |
123 | writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); | |
124 | writel(cap_save, mmio + HOST_CAP); | |
125 | writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); | |
126 | ||
942e3143 | 127 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 JZ |
128 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
129 | ||
130 | if (vendor == PCI_VENDOR_ID_INTEL) { | |
131 | u16 tmp16; | |
132 | pci_read_config_word(pdev, 0x92, &tmp16); | |
133 | tmp16 |= 0xf; | |
134 | pci_write_config_word(pdev, 0x92, tmp16); | |
135 | } | |
942e3143 | 136 | #endif |
4782ac80 JZ |
137 | probe_ent->cap = readl(mmio + HOST_CAP); |
138 | probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); | |
139 | probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; | |
140 | ||
141 | debug("cap 0x%x port_map 0x%x n_ports %d\n", | |
4a7cc0f2 | 142 | probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); |
4782ac80 | 143 | |
284231e4 VB |
144 | if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) |
145 | probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; | |
146 | ||
4782ac80 | 147 | for (i = 0; i < probe_ent->n_ports; i++) { |
4a7cc0f2 JL |
148 | probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); |
149 | port_mmio = (u8 *) probe_ent->port[i].port_mmio; | |
150 | ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); | |
4782ac80 JZ |
151 | |
152 | /* make sure port is not active */ | |
153 | tmp = readl(port_mmio + PORT_CMD); | |
154 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
155 | PORT_CMD_FIS_RX | PORT_CMD_START)) { | |
156 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
157 | PORT_CMD_FIS_RX | PORT_CMD_START); | |
158 | writel_with_flush(tmp, port_mmio + PORT_CMD); | |
159 | ||
160 | /* spec says 500 msecs for each bit, so | |
161 | * this is slightly incorrect. | |
162 | */ | |
163 | msleep(500); | |
164 | } | |
165 | ||
166 | writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); | |
167 | ||
168 | j = 0; | |
9a65b875 | 169 | while (j < 1000) { |
4782ac80 JZ |
170 | tmp = readl(port_mmio + PORT_SCR_STAT); |
171 | if ((tmp & 0xf) == 0x3) | |
172 | break; | |
9a65b875 | 173 | udelay(1000); |
4782ac80 JZ |
174 | j++; |
175 | } | |
9a65b875 SR |
176 | if (j == 1000) |
177 | debug("timeout.\n"); | |
178 | else | |
179 | debug("ok.\n"); | |
4782ac80 JZ |
180 | |
181 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
182 | debug("PORT_SCR_ERR 0x%x\n", tmp); | |
183 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
184 | ||
185 | /* ack any pending irq events for this port */ | |
186 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
187 | debug("PORT_IRQ_STAT 0x%x\n", tmp); | |
188 | if (tmp) | |
189 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
190 | ||
191 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
192 | ||
193 | /* set irq mask (enables interrupts) */ | |
194 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
195 | ||
4a7cc0f2 | 196 | /*register linkup ports */ |
4782ac80 | 197 | tmp = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
198 | debug("Port %d status: 0x%x\n", i, tmp); |
199 | if ((tmp & 0xf) == 0x03) | |
200 | probe_ent->link_port_map |= (0x01 << i); | |
4782ac80 JZ |
201 | } |
202 | ||
203 | tmp = readl(mmio + HOST_CTL); | |
204 | debug("HOST_CTL 0x%x\n", tmp); | |
205 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
206 | tmp = readl(mmio + HOST_CTL); | |
207 | debug("HOST_CTL 0x%x\n", tmp); | |
942e3143 | 208 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 JZ |
209 | pci_read_config_word(pdev, PCI_COMMAND, &tmp16); |
210 | tmp |= PCI_COMMAND_MASTER; | |
211 | pci_write_config_word(pdev, PCI_COMMAND, tmp16); | |
942e3143 | 212 | #endif |
4782ac80 JZ |
213 | return 0; |
214 | } | |
215 | ||
216 | ||
217 | static void ahci_print_info(struct ahci_probe_ent *probe_ent) | |
218 | { | |
942e3143 | 219 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 220 | pci_dev_t pdev = probe_ent->dev; |
942e3143 RH |
221 | u16 cc; |
222 | #endif | |
4a7cc0f2 | 223 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
4782ac80 JZ |
224 | u32 vers, cap, impl, speed; |
225 | const char *speed_s; | |
4782ac80 JZ |
226 | const char *scc_s; |
227 | ||
228 | vers = readl(mmio + HOST_VERSION); | |
229 | cap = probe_ent->cap; | |
230 | impl = probe_ent->port_map; | |
231 | ||
232 | speed = (cap >> 20) & 0xf; | |
233 | if (speed == 1) | |
234 | speed_s = "1.5"; | |
235 | else if (speed == 2) | |
236 | speed_s = "3"; | |
237 | else | |
238 | speed_s = "?"; | |
239 | ||
942e3143 RH |
240 | #ifdef CONFIG_SCSI_AHCI_PLAT |
241 | scc_s = "SATA"; | |
242 | #else | |
4782ac80 JZ |
243 | pci_read_config_word(pdev, 0x0a, &cc); |
244 | if (cc == 0x0101) | |
245 | scc_s = "IDE"; | |
246 | else if (cc == 0x0106) | |
247 | scc_s = "SATA"; | |
248 | else if (cc == 0x0104) | |
249 | scc_s = "RAID"; | |
250 | else | |
251 | scc_s = "unknown"; | |
942e3143 | 252 | #endif |
4a7cc0f2 JL |
253 | printf("AHCI %02x%02x.%02x%02x " |
254 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", | |
255 | (vers >> 24) & 0xff, | |
256 | (vers >> 16) & 0xff, | |
257 | (vers >> 8) & 0xff, | |
258 | vers & 0xff, | |
259 | ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); | |
4782ac80 JZ |
260 | |
261 | printf("flags: " | |
4a7cc0f2 JL |
262 | "%s%s%s%s%s%s" |
263 | "%s%s%s%s%s%s%s\n", | |
264 | cap & (1 << 31) ? "64bit " : "", | |
265 | cap & (1 << 30) ? "ncq " : "", | |
266 | cap & (1 << 28) ? "ilck " : "", | |
267 | cap & (1 << 27) ? "stag " : "", | |
268 | cap & (1 << 26) ? "pm " : "", | |
269 | cap & (1 << 25) ? "led " : "", | |
270 | cap & (1 << 24) ? "clo " : "", | |
271 | cap & (1 << 19) ? "nz " : "", | |
272 | cap & (1 << 18) ? "only " : "", | |
273 | cap & (1 << 17) ? "pmp " : "", | |
274 | cap & (1 << 15) ? "pio " : "", | |
275 | cap & (1 << 14) ? "slum " : "", | |
276 | cap & (1 << 13) ? "part " : ""); | |
4782ac80 JZ |
277 | } |
278 | ||
942e3143 | 279 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4a7cc0f2 | 280 | static int ahci_init_one(pci_dev_t pdev) |
4782ac80 | 281 | { |
63cec581 | 282 | u16 vendor; |
4782ac80 JZ |
283 | int rc; |
284 | ||
4a7cc0f2 | 285 | memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); |
4782ac80 | 286 | |
594e7983 ES |
287 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
288 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); | |
4782ac80 JZ |
289 | probe_ent->dev = pdev; |
290 | ||
4a7cc0f2 JL |
291 | probe_ent->host_flags = ATA_FLAG_SATA |
292 | | ATA_FLAG_NO_LEGACY | |
293 | | ATA_FLAG_MMIO | |
294 | | ATA_FLAG_PIO_DMA | |
295 | | ATA_FLAG_NO_ATAPI; | |
296 | probe_ent->pio_mask = 0x1f; | |
297 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
4782ac80 | 298 | |
284231e4 VB |
299 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base); |
300 | debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base); | |
4782ac80 JZ |
301 | |
302 | /* Take from kernel: | |
303 | * JMicron-specific fixup: | |
304 | * make sure we're in AHCI mode | |
305 | */ | |
306 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); | |
4a7cc0f2 | 307 | if (vendor == 0x197b) |
4782ac80 JZ |
308 | pci_write_config_byte(pdev, 0x41, 0xa1); |
309 | ||
310 | /* initialize adapter */ | |
311 | rc = ahci_host_init(probe_ent); | |
312 | if (rc) | |
313 | goto err_out; | |
314 | ||
315 | ahci_print_info(probe_ent); | |
316 | ||
317 | return 0; | |
318 | ||
4a7cc0f2 | 319 | err_out: |
4782ac80 JZ |
320 | return rc; |
321 | } | |
942e3143 | 322 | #endif |
4782ac80 JZ |
323 | |
324 | #define MAX_DATA_BYTE_COUNT (4*1024*1024) | |
4a7cc0f2 | 325 | |
4782ac80 JZ |
326 | static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) |
327 | { | |
4782ac80 JZ |
328 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
329 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; | |
330 | u32 sg_count; | |
331 | int i; | |
332 | ||
333 | sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; | |
4a7cc0f2 | 334 | if (sg_count > AHCI_MAX_SG) { |
4782ac80 JZ |
335 | printf("Error:Too much sg!\n"); |
336 | return -1; | |
337 | } | |
338 | ||
4a7cc0f2 JL |
339 | for (i = 0; i < sg_count; i++) { |
340 | ahci_sg->addr = | |
341 | cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); | |
4782ac80 | 342 | ahci_sg->addr_hi = 0; |
4a7cc0f2 JL |
343 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & |
344 | (buf_len < MAX_DATA_BYTE_COUNT | |
345 | ? (buf_len - 1) | |
346 | : (MAX_DATA_BYTE_COUNT - 1))); | |
4782ac80 JZ |
347 | ahci_sg++; |
348 | buf_len -= MAX_DATA_BYTE_COUNT; | |
349 | } | |
350 | ||
351 | return sg_count; | |
352 | } | |
353 | ||
354 | ||
355 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) | |
356 | { | |
357 | pp->cmd_slot->opts = cpu_to_le32(opts); | |
358 | pp->cmd_slot->status = 0; | |
359 | pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); | |
360 | pp->cmd_slot->tbl_addr_hi = 0; | |
361 | } | |
362 | ||
363 | ||
364 | static void ahci_set_feature(u8 port) | |
365 | { | |
4782ac80 | 366 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 JL |
367 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
368 | u32 cmd_fis_len = 5; /* five dwords */ | |
4782ac80 JZ |
369 | u8 fis[20]; |
370 | ||
4a7cc0f2 JL |
371 | /*set feature */ |
372 | memset(fis, 0, 20); | |
4782ac80 JZ |
373 | fis[0] = 0x27; |
374 | fis[1] = 1 << 7; | |
375 | fis[2] = ATA_CMD_SETF; | |
376 | fis[3] = SETFEATURES_XFER; | |
377 | fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; | |
378 | ||
4a7cc0f2 | 379 | memcpy((unsigned char *)pp->cmd_tbl, fis, 20); |
4782ac80 JZ |
380 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
381 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
382 | readl(port_mmio + PORT_CMD_ISSUE); | |
383 | ||
4a7cc0f2 | 384 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { |
4782ac80 JZ |
385 | printf("set feature error!\n"); |
386 | } | |
387 | } | |
388 | ||
389 | ||
390 | static int ahci_port_start(u8 port) | |
391 | { | |
4782ac80 | 392 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
4a7cc0f2 | 393 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
4782ac80 JZ |
394 | u32 port_status; |
395 | u32 mem; | |
396 | ||
4a7cc0f2 | 397 | debug("Enter start port: %d\n", port); |
4782ac80 | 398 | port_status = readl(port_mmio + PORT_SCR_STAT); |
4a7cc0f2 JL |
399 | debug("Port %d status: %x\n", port, port_status); |
400 | if ((port_status & 0xf) != 0x03) { | |
4782ac80 JZ |
401 | printf("No Link on this port!\n"); |
402 | return -1; | |
403 | } | |
404 | ||
4a7cc0f2 | 405 | mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); |
4782ac80 JZ |
406 | if (!mem) { |
407 | free(pp); | |
408 | printf("No mem for table!\n"); | |
409 | return -ENOMEM; | |
410 | } | |
411 | ||
4a7cc0f2 JL |
412 | mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ |
413 | memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
4782ac80 | 414 | |
4782ac80 JZ |
415 | /* |
416 | * First item in chunk of DMA memory: 32-slot command table, | |
417 | * 32 bytes each in size | |
418 | */ | |
419 | pp->cmd_slot = (struct ahci_cmd_hdr *)mem; | |
284231e4 | 420 | debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); |
4782ac80 | 421 | mem += (AHCI_CMD_SLOT_SZ + 224); |
4a7cc0f2 | 422 | |
4782ac80 JZ |
423 | /* |
424 | * Second item: Received-FIS area | |
425 | */ | |
426 | pp->rx_fis = mem; | |
4782ac80 | 427 | mem += AHCI_RX_FIS_SZ; |
4a7cc0f2 | 428 | |
4782ac80 JZ |
429 | /* |
430 | * Third item: data area for storing a single command | |
431 | * and its scatter-gather table | |
432 | */ | |
433 | pp->cmd_tbl = mem; | |
4a7cc0f2 | 434 | debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); |
4782ac80 JZ |
435 | |
436 | mem += AHCI_CMD_TBL_HDR; | |
437 | pp->cmd_tbl_sg = (struct ahci_sg *)mem; | |
438 | ||
4a7cc0f2 | 439 | writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); |
4782ac80 JZ |
440 | |
441 | writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); | |
442 | ||
443 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | | |
4a7cc0f2 JL |
444 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
445 | PORT_CMD_START, port_mmio + PORT_CMD); | |
4782ac80 | 446 | |
4a7cc0f2 | 447 | debug("Exit start port %d\n", port); |
4782ac80 JZ |
448 | |
449 | return 0; | |
450 | } | |
451 | ||
452 | ||
4a7cc0f2 JL |
453 | static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, |
454 | int buf_len) | |
4782ac80 JZ |
455 | { |
456 | ||
4a7cc0f2 JL |
457 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
458 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; | |
4782ac80 JZ |
459 | u32 opts; |
460 | u32 port_status; | |
461 | int sg_count; | |
462 | ||
4a7cc0f2 | 463 | debug("Enter get_ahci_device_data: for port %d\n", port); |
4782ac80 | 464 | |
4a7cc0f2 | 465 | if (port > probe_ent->n_ports) { |
4782ac80 JZ |
466 | printf("Invaild port number %d\n", port); |
467 | return -1; | |
468 | } | |
469 | ||
470 | port_status = readl(port_mmio + PORT_SCR_STAT); | |
4a7cc0f2 JL |
471 | if ((port_status & 0xf) != 0x03) { |
472 | debug("No Link on port %d!\n", port); | |
4782ac80 JZ |
473 | return -1; |
474 | } | |
475 | ||
476 | memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); | |
477 | ||
4a7cc0f2 JL |
478 | sg_count = ahci_fill_sg(port, buf, buf_len); |
479 | opts = (fis_len >> 2) | (sg_count << 16); | |
4782ac80 JZ |
480 | ahci_fill_cmd_slot(pp, opts); |
481 | ||
482 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); | |
483 | ||
484 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { | |
485 | printf("timeout exit!\n"); | |
486 | return -1; | |
487 | } | |
488 | debug("get_ahci_device_data: %d byte transferred.\n", | |
4a7cc0f2 | 489 | pp->cmd_slot->status); |
4782ac80 JZ |
490 | |
491 | return 0; | |
492 | } | |
493 | ||
494 | ||
495 | static char *ata_id_strcpy(u16 *target, u16 *src, int len) | |
496 | { | |
497 | int i; | |
4a7cc0f2 | 498 | for (i = 0; i < len / 2; i++) |
e5a6c79d | 499 | target[i] = swab16(src[i]); |
4782ac80 JZ |
500 | return (char *)target; |
501 | } | |
502 | ||
503 | ||
504 | static void dump_ataid(hd_driveid_t *ataid) | |
505 | { | |
506 | debug("(49)ataid->capability = 0x%x\n", ataid->capability); | |
507 | debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); | |
508 | debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); | |
509 | debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); | |
510 | debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); | |
511 | debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); | |
512 | debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); | |
513 | debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); | |
514 | debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); | |
515 | debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); | |
516 | debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); | |
517 | debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); | |
518 | debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); | |
519 | debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); | |
520 | debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); | |
521 | } | |
522 | ||
4a7cc0f2 | 523 | |
4782ac80 JZ |
524 | /* |
525 | * SCSI INQUIRY command operation. | |
526 | */ | |
527 | static int ata_scsiop_inquiry(ccb *pccb) | |
528 | { | |
529 | u8 hdr[] = { | |
530 | 0, | |
531 | 0, | |
4a7cc0f2 | 532 | 0x5, /* claim SPC-3 version compatibility */ |
4782ac80 JZ |
533 | 2, |
534 | 95 - 4, | |
535 | }; | |
536 | u8 fis[20]; | |
537 | u8 *tmpid; | |
538 | u8 port; | |
539 | ||
540 | /* Clean ccb data buffer */ | |
541 | memset(pccb->pdata, 0, pccb->datalen); | |
542 | ||
543 | memcpy(pccb->pdata, hdr, sizeof(hdr)); | |
544 | ||
4a7cc0f2 | 545 | if (pccb->datalen <= 35) |
4782ac80 JZ |
546 | return 0; |
547 | ||
548 | memset(fis, 0, 20); | |
549 | /* Construct the FIS */ | |
4a7cc0f2 JL |
550 | fis[0] = 0x27; /* Host to device FIS. */ |
551 | fis[1] = 1 << 7; /* Command FIS. */ | |
552 | fis[2] = ATA_CMD_IDENT; /* Command byte. */ | |
4782ac80 JZ |
553 | |
554 | /* Read id from sata */ | |
555 | port = pccb->target; | |
4a7cc0f2 | 556 | if (!(tmpid = malloc(sizeof(hd_driveid_t)))) |
4782ac80 JZ |
557 | return -ENOMEM; |
558 | ||
4a7cc0f2 JL |
559 | if (get_ahci_device_data(port, (u8 *) & fis, 20, |
560 | tmpid, sizeof(hd_driveid_t))) { | |
4782ac80 JZ |
561 | debug("scsi_ahci: SCSI inquiry command failure.\n"); |
562 | return -EIO; | |
563 | } | |
564 | ||
4a7cc0f2 | 565 | if (ataid[port]) |
4782ac80 | 566 | free(ataid[port]); |
4a7cc0f2 | 567 | ataid[port] = (hd_driveid_t *) tmpid; |
4782ac80 JZ |
568 | |
569 | memcpy(&pccb->pdata[8], "ATA ", 8); | |
4a7cc0f2 JL |
570 | ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); |
571 | ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); | |
4782ac80 JZ |
572 | |
573 | dump_ataid(ataid[port]); | |
574 | return 0; | |
575 | } | |
576 | ||
577 | ||
578 | /* | |
579 | * SCSI READ10 command operation. | |
580 | */ | |
4a7cc0f2 | 581 | static int ata_scsiop_read10(ccb * pccb) |
4782ac80 | 582 | { |
284231e4 VB |
583 | u32 lba = 0; |
584 | u16 blocks = 0; | |
4782ac80 | 585 | u8 fis[20]; |
284231e4 VB |
586 | u8 *user_buffer = pccb->pdata; |
587 | u32 user_buffer_size = pccb->datalen; | |
4782ac80 | 588 | |
284231e4 VB |
589 | /* Retrieve the base LBA number from the ccb structure. */ |
590 | memcpy(&lba, pccb->cmd + 2, sizeof(lba)); | |
591 | lba = be32_to_cpu(lba); | |
4782ac80 | 592 | |
284231e4 VB |
593 | /* |
594 | * And the number of blocks. | |
595 | * | |
596 | * For 10-byte and 16-byte SCSI R/W commands, transfer | |
4782ac80 JZ |
597 | * length 0 means transfer 0 block of data. |
598 | * However, for ATA R/W commands, sector count 0 means | |
599 | * 256 or 65536 sectors, not 0 sectors as in SCSI. | |
600 | * | |
601 | * WARNING: one or two older ATA drives treat 0 as 0... | |
602 | */ | |
284231e4 VB |
603 | blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); |
604 | ||
605 | debug("scsi_ahci: read %d blocks starting from lba 0x%x\n", | |
606 | (unsigned)lba, blocks); | |
607 | ||
608 | /* Preset the FIS */ | |
4782ac80 | 609 | memset(fis, 0, 20); |
284231e4 VB |
610 | fis[0] = 0x27; /* Host to device FIS. */ |
611 | fis[1] = 1 << 7; /* Command FIS. */ | |
612 | fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ | |
4782ac80 | 613 | |
284231e4 VB |
614 | while (blocks) { |
615 | u16 now_blocks; /* number of blocks per iteration */ | |
616 | u32 transfer_size; /* number of bytes per iteration */ | |
617 | ||
618 | now_blocks = min(MAX_SATA_BLOCKS_READ, blocks); | |
619 | ||
620 | transfer_size = ATA_BLOCKSIZE * now_blocks; | |
621 | if (transfer_size > user_buffer_size) { | |
622 | printf("scsi_ahci: Error: buffer too small.\n"); | |
623 | return -EIO; | |
624 | } | |
625 | ||
626 | /* LBA address, only support LBA28 in this driver */ | |
627 | fis[4] = (lba >> 0) & 0xff; | |
628 | fis[5] = (lba >> 8) & 0xff; | |
629 | fis[6] = (lba >> 16) & 0xff; | |
630 | fis[7] = ((lba >> 24) & 0xf) | 0xe0; | |
631 | ||
632 | /* Block (sector) count */ | |
633 | fis[12] = (now_blocks >> 0) & 0xff; | |
634 | fis[13] = (now_blocks >> 8) & 0xff; | |
635 | ||
636 | /* Read from ahci */ | |
637 | if (get_ahci_device_data(pccb->target, (u8 *) &fis, sizeof(fis), | |
638 | user_buffer, user_buffer_size)) { | |
639 | debug("scsi_ahci: SCSI READ10 command failure.\n"); | |
640 | return -EIO; | |
641 | } | |
642 | user_buffer += transfer_size; | |
643 | user_buffer_size -= transfer_size; | |
644 | blocks -= now_blocks; | |
645 | lba += now_blocks; | |
4782ac80 JZ |
646 | } |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | ||
652 | /* | |
653 | * SCSI READ CAPACITY10 command operation. | |
654 | */ | |
655 | static int ata_scsiop_read_capacity10(ccb *pccb) | |
656 | { | |
cb6d0b72 | 657 | u32 cap; |
4782ac80 | 658 | |
4a7cc0f2 | 659 | if (!ataid[pccb->target]) { |
4782ac80 | 660 | printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " |
4a7cc0f2 JL |
661 | "\tNo ATA info!\n" |
662 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); | |
4782ac80 JZ |
663 | return -EPERM; |
664 | } | |
665 | ||
284231e4 | 666 | cap = be32_to_cpu(ataid[pccb->target]->lba_capacity); |
cb6d0b72 | 667 | memcpy(pccb->pdata, &cap, sizeof(cap)); |
4782ac80 | 668 | |
cb6d0b72 KG |
669 | pccb->pdata[4] = pccb->pdata[5] = 0; |
670 | pccb->pdata[6] = 512 >> 8; | |
671 | pccb->pdata[7] = 512 & 0xff; | |
4782ac80 JZ |
672 | |
673 | return 0; | |
674 | } | |
675 | ||
676 | ||
677 | /* | |
678 | * SCSI TEST UNIT READY command operation. | |
679 | */ | |
680 | static int ata_scsiop_test_unit_ready(ccb *pccb) | |
681 | { | |
682 | return (ataid[pccb->target]) ? 0 : -EPERM; | |
683 | } | |
684 | ||
4a7cc0f2 | 685 | |
4782ac80 JZ |
686 | int scsi_exec(ccb *pccb) |
687 | { | |
688 | int ret; | |
689 | ||
4a7cc0f2 | 690 | switch (pccb->cmd[0]) { |
4782ac80 JZ |
691 | case SCSI_READ10: |
692 | ret = ata_scsiop_read10(pccb); | |
693 | break; | |
694 | case SCSI_RD_CAPAC: | |
695 | ret = ata_scsiop_read_capacity10(pccb); | |
696 | break; | |
697 | case SCSI_TST_U_RDY: | |
698 | ret = ata_scsiop_test_unit_ready(pccb); | |
699 | break; | |
700 | case SCSI_INQUIRY: | |
701 | ret = ata_scsiop_inquiry(pccb); | |
702 | break; | |
703 | default: | |
704 | printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); | |
705 | return FALSE; | |
706 | } | |
707 | ||
4a7cc0f2 JL |
708 | if (ret) { |
709 | debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); | |
4782ac80 JZ |
710 | return FALSE; |
711 | } | |
712 | return TRUE; | |
713 | ||
714 | } | |
715 | ||
716 | ||
717 | void scsi_low_level_init(int busdevfunc) | |
718 | { | |
719 | int i; | |
720 | u32 linkmap; | |
721 | ||
942e3143 | 722 | #ifndef CONFIG_SCSI_AHCI_PLAT |
4782ac80 | 723 | ahci_init_one(busdevfunc); |
942e3143 | 724 | #endif |
4782ac80 JZ |
725 | |
726 | linkmap = probe_ent->link_port_map; | |
727 | ||
6d0f6bcf | 728 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { |
4a7cc0f2 JL |
729 | if (((linkmap >> i) & 0x01)) { |
730 | if (ahci_port_start((u8) i)) { | |
731 | printf("Can not start port %d\n", i); | |
4782ac80 JZ |
732 | continue; |
733 | } | |
4a7cc0f2 | 734 | ahci_set_feature((u8) i); |
4782ac80 JZ |
735 | } |
736 | } | |
737 | } | |
738 | ||
942e3143 RH |
739 | #ifdef CONFIG_SCSI_AHCI_PLAT |
740 | int ahci_init(u32 base) | |
741 | { | |
742 | int i, rc = 0; | |
743 | u32 linkmap; | |
744 | ||
745 | memset(ataid, 0, sizeof(ataid)); | |
746 | ||
747 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); | |
748 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); | |
749 | ||
750 | probe_ent->host_flags = ATA_FLAG_SATA | |
751 | | ATA_FLAG_NO_LEGACY | |
752 | | ATA_FLAG_MMIO | |
753 | | ATA_FLAG_PIO_DMA | |
754 | | ATA_FLAG_NO_ATAPI; | |
755 | probe_ent->pio_mask = 0x1f; | |
756 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ | |
757 | ||
758 | probe_ent->mmio_base = base; | |
759 | ||
760 | /* initialize adapter */ | |
761 | rc = ahci_host_init(probe_ent); | |
762 | if (rc) | |
763 | goto err_out; | |
764 | ||
765 | ahci_print_info(probe_ent); | |
766 | ||
767 | linkmap = probe_ent->link_port_map; | |
768 | ||
769 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { | |
770 | if (((linkmap >> i) & 0x01)) { | |
771 | if (ahci_port_start((u8) i)) { | |
772 | printf("Can not start port %d\n", i); | |
773 | continue; | |
774 | } | |
775 | ahci_set_feature((u8) i); | |
776 | } | |
777 | } | |
778 | err_out: | |
779 | return rc; | |
780 | } | |
781 | #endif | |
4782ac80 JZ |
782 | |
783 | void scsi_bus_reset(void) | |
784 | { | |
4a7cc0f2 | 785 | /*Not implement*/ |
4782ac80 JZ |
786 | } |
787 | ||
788 | ||
4a7cc0f2 | 789 | void scsi_print_error(ccb * pccb) |
4782ac80 | 790 | { |
4a7cc0f2 | 791 | /*The ahci error info can be read in the ahci driver*/ |
4782ac80 | 792 | } |