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ahci: Fix a wrong parameter pass
[people/ms/u-boot.git] / drivers / block / ata_piix.c
CommitLineData
66d9dbec 1/*
3162eb83
WD		 2 * Copyright (C) Procsys. All rights reserved.
3 * Author: Mushtaq Khan <mushtaq_k@procsys.com>
4 * <mushtaqk_921@yahoo.co.in>
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
3162eb83
WD		 7 *
8 * with the reference to ata_piix driver in kernel 2.4.32
9 */
66d9dbec 10
11/*
3162eb83
WD		 12 * This file contains SATA controller and SATA drive initialization functions
13 */
66d9dbec 14
15#include <common.h>
9eef6280 16#include <asm/io.h>
66d9dbec 17#include <pci.h>
18#include <command.h>
19#include <config.h>
20#include <asm/byteorder.h>
9eef6280 21#include <part.h>
66d9dbec 22#include <ide.h>
23#include <ata.h>
e46a4350 24#include <sata.h>
8e9bb434 25
879a57ac 26#define DEBUG_SATA 0 /* For debug prints set DEBUG_SATA to 1 */
66d9dbec 27
9eef6280 28#define SATA_DECL
879a57ac 29#define DRV_DECL /* For file specific declarations */
83c7f470 30#include "ata_piix.h"
66d9dbec 31
879a57ac 32/* Macros realted to PCI */
66d9dbec 33#define PCI_SATA_BUS 0x00
34#define PCI_SATA_DEV 0x1f
35#define PCI_SATA_FUNC 0x02
36
37#define PCI_SATA_BASE1 0x10
38#define PCI_SATA_BASE2 0x14
39#define PCI_SATA_BASE3 0x18
40#define PCI_SATA_BASE4 0x1c
41#define PCI_SATA_BASE5 0x20
42#define PCI_PMR 0x90
43#define PCI_PI 0x09
44#define PCI_PCS 0x92
45#define PCI_DMA_CTL 0x48
46
47#define PORT_PRESENT (1<<0)
48#define PORT_ENABLED (1<<4)
49
50u32 bdf;
879a57ac
TR		 51u32 iobase1; /* Primary cmd block */
52u32 iobase2; /* Primary ctl block */
53u32 iobase3; /* Sec cmd block */
54u32 iobase4; /* sec ctl block */
55u32 iobase5; /* BMDMA*/
56
57int pci_sata_init(void)
66d9dbec 58{
59 u32 bus = PCI_SATA_BUS;
60 u32 dev = PCI_SATA_DEV;
61 u32 fun = PCI_SATA_FUNC;
62 u16 cmd = 0;
63 u8 lat = 0, pcibios_max_latency = 0xff;
879a57ac
TR		 64 u8 pmr; /* Port mapping reg */
65 u8 pi; /* Prgming Interface reg */
66d9dbec 66
879a57ac
TR		 67 bdf = PCI_BDF(bus, dev, fun);
68 pci_read_config_dword(bdf, PCI_SATA_BASE1, &iobase1);
69 pci_read_config_dword(bdf, PCI_SATA_BASE2, &iobase2);
70 pci_read_config_dword(bdf, PCI_SATA_BASE3, &iobase3);
71 pci_read_config_dword(bdf, PCI_SATA_BASE4, &iobase4);
72 pci_read_config_dword(bdf, PCI_SATA_BASE5, &iobase5);
66d9dbec 73
74 if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
75 (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
76 (iobase5 == 0xFFFFFFFF)) {
879a57ac
TR		 77 /* ERROR */
78 printf("error no base addr for SATA controller\n");
66d9dbec 79 return 1;
879a57ac 80 }
66d9dbec 81
82 iobase1 &= 0xFFFFFFFE;
83 iobase2 &= 0xFFFFFFFE;
84 iobase3 &= 0xFFFFFFFE;
85 iobase4 &= 0xFFFFFFFE;
86 iobase5 &= 0xFFFFFFFE;
87
879a57ac
TR		 88 /* check for mode */
89 pci_read_config_byte(bdf, PCI_PMR, &pmr);
66d9dbec 90 if (pmr > 1) {
879a57ac 91 puts("combined mode not supported\n");
66d9dbec 92 return 1;
93 }
94
879a57ac 95 pci_read_config_byte(bdf, PCI_PI, &pi);
66d9dbec 96 if ((pi & 0x05) != 0x05) {
879a57ac 97 puts("Sata is in Legacy mode\n");
66d9dbec 98 return 1;
879a57ac
TR		 99 } else
100 puts("sata is in Native mode\n");
66d9dbec 101
879a57ac
TR		 102 /* MASTER CFG AND IO CFG */
103 pci_read_config_word(bdf, PCI_COMMAND, &cmd);
66d9dbec 104 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
879a57ac
TR		 105 pci_write_config_word(bdf, PCI_COMMAND, cmd);
106 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
66d9dbec 107
108 if (lat < 16)
109 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
110 else if (lat > pcibios_max_latency)
111 lat = pcibios_max_latency;
879a57ac 112 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
66d9dbec 113
114 return 0;
115}
116
879a57ac 117int sata_bus_probe(int port_no)
66d9dbec 118{
119 int orig_mask, mask;
120 u16 pcs;
121
122 mask = (PORT_PRESENT << port_no);
879a57ac 123 pci_read_config_word(bdf, PCI_PCS, &pcs);
66d9dbec 124 orig_mask = (int) pcs & 0xff;
125 if ((orig_mask & mask) != mask)
126 return 0;
127 else
128 return 1;
129}
130
879a57ac 131int init_sata(int dev)
66d9dbec 132{
879a57ac 133 static int done;
66d9dbec 134 u8 i, rv = 0;
135
8e9bb434
DL		 136 if (!done)
137 done = 1;
138 else
139 return 0;
66d9dbec 140
879a57ac 141 rv = pci_sata_init();
66d9dbec 142 if (rv == 1) {
879a57ac 143 puts("pci initialization failed\n");
66d9dbec 144 return 1;
145 }
146
147 port[0].port_no = 0;
148 port[0].ioaddr.cmd_addr = iobase1;
149 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
150 iobase2 | ATA_PCI_CTL_OFS;
151 port[0].ioaddr.bmdma_addr = iobase5;
152
153 port[1].port_no = 1;
154 port[1].ioaddr.cmd_addr = iobase3;
155 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
156 iobase4 | ATA_PCI_CTL_OFS;
157 port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
158
6d0f6bcf 159 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
879a57ac 160 sata_port(&port[i].ioaddr);
66d9dbec 161
6d0f6bcf 162 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
879a57ac 163 if (!(sata_bus_probe(i))) {
66d9dbec 164 port[i].port_state = 0;
879a57ac 165 printf("SATA#%d port is not present\n", i);
66d9dbec 166 } else {
879a57ac
TR		 167 printf("SATA#%d port is present\n", i);
168 if (sata_bus_softreset(i))
66d9dbec 169 port[i].port_state = 0;
879a57ac 170 else
66d9dbec 171 port[i].port_state = 1;
66d9dbec 172 }
173 }
174
6d0f6bcf 175 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
66d9dbec 176 u8 j, devno;
177
178 if (port[i].port_state == 0)
179 continue;
6d0f6bcf 180 for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
879a57ac
TR		 181 sata_identify(i, j);
182 set_Feature_cmd(i, j);
6d0f6bcf 183 devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
66d9dbec 184 if ((sata_dev_desc[devno].lba > 0) &&
185 (sata_dev_desc[devno].blksz > 0)) {
879a57ac 186 dev_print(&sata_dev_desc[devno]);
66d9dbec 187 /* initialize partition type */
879a57ac 188 init_part(&sata_dev_desc[devno]);
66d9dbec 189 }
190 }
191 }
192 return 0;
193}
9eef6280 194
10ee8eca
NK		 195int reset_sata(int dev)
196{
197 return 0;
198}
199
879a57ac 200static inline u8 sata_inb(unsigned long ioaddr)
9eef6280 201{
879a57ac 202 return inb(ioaddr);
9eef6280
DL		 203}
204
879a57ac 205static inline void sata_outb(unsigned char val, unsigned long ioaddr)
9eef6280 206{
879a57ac 207 outb(val, ioaddr);
9eef6280
DL		 208}
209
879a57ac
TR		 210static void output_data(struct sata_ioports *ioaddr, ulong * sect_buf,
211 int words)
9eef6280 212{
879a57ac 213 outsw(ioaddr->data_addr, sect_buf, words << 1);
9eef6280
DL		 214}
215
879a57ac 216static int input_data(struct sata_ioports *ioaddr, ulong * sect_buf, int words)
9eef6280 217{
879a57ac 218 insw(ioaddr->data_addr, sect_buf, words << 1);
9eef6280
DL		 219 return 0;
220}
221
879a57ac 222static void sata_cpy(unsigned char *dst, unsigned char *src, unsigned int len)
9eef6280
DL		 223{
224 unsigned char *end, *last;
225
226 last = dst;
227 end = src + len - 1;
228
229 /* reserve space for '\0' */
230 if (len < 2)
231 goto OUT;
232
233 /* skip leading white space */
234 while ((*src) && (src < end) && (*src == ' '))
235 ++src;
236
237 /* copy string, omitting trailing white space */
238 while ((*src) && (src < end)) {
239 *dst++ = *src;
240 if (*src++ != ' ')
241 last = dst;
242 }
879a57ac 243OUT:
9eef6280
DL		 244 *last = '\0';
245}
246
879a57ac 247int sata_bus_softreset(int num)
9eef6280
DL		 248{
249 u8 dev = 0, status = 0, i;
250
251 port[num].dev_mask = 0;
252
6d0f6bcf 253 for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
879a57ac
TR		 254 if (!(sata_devchk(&port[num].ioaddr, i))) {
255 debug("dev_chk failed for dev#%d\n", i);
9eef6280
DL		 256 } else {
257 port[num].dev_mask |= (1 << i);
879a57ac 258 debug("dev_chk passed for dev#%d\n", i);
9eef6280
DL		 259 }
260 }
261
262 if (!(port[num].dev_mask)) {
879a57ac 263 printf("no devices on port%d\n", num);
9eef6280
DL		 264 return 1;
265 }
266
879a57ac 267 dev_select(&port[num].ioaddr, dev);
9eef6280 268
879a57ac
TR		 269 port[num].ctl_reg = 0x08; /* Default value of control reg */
270 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
271 udelay(10);
272 sata_outb(port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
273 udelay(10);
274 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
9eef6280 275
879a57ac
TR		 276 /*
277 * spec mandates ">= 2ms" before checking status.
9eef6280
DL		 278 * We wait 150ms, because that was the magic delay used for
279 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
280 * between when the ATA command register is written, and then
281 * status is checked. Because waiting for "a while" before
282 * checking status is fine, post SRST, we perform this magic
283 * delay here as well.
284 */
879a57ac
TR		 285 mdelay(150);
286 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 300);
9eef6280 287 while ((status & ATA_BUSY)) {
879a57ac
TR		 288 mdelay(100);
289 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 3);
9eef6280
DL		 290 }
291
292 if (status & ATA_BUSY)
879a57ac 293 printf("ata%u is slow to respond,plz be patient\n", num);
9eef6280
DL		 294
295 while ((status & ATA_BUSY)) {
879a57ac
TR		 296 mdelay(100);
297 status = sata_chk_status(&port[num].ioaddr);
9eef6280
DL		 298 }
299
300 if (status & ATA_BUSY) {
879a57ac 301 printf("ata%u failed to respond : bus reset failed\n", num);
9eef6280
DL		 302 return 1;
303 }
304 return 0;
305}
306
879a57ac 307void sata_identify(int num, int dev)
9eef6280 308{
879a57ac
TR		 309 u8 cmd = 0, status = 0;
310 u8 devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
9eef6280
DL		 311 u16 iobuf[ATA_SECT_SIZE];
312 u64 n_sectors = 0;
313 u8 mask = 0;
314
879a57ac 315 memset(iobuf, 0, sizeof(iobuf));
9eef6280
DL		 316 hd_driveid_t *iop = (hd_driveid_t *) iobuf;
317
318 if (dev == 0)
319 mask = 0x01;
320 else
321 mask = 0x02;
322
323 if (!(port[num].dev_mask & mask)) {
879a57ac 324 printf("dev%d is not present on port#%d\n", dev, num);
9eef6280
DL		 325 return;
326 }
327
879a57ac 328 printf("port=%d dev=%d\n", num, dev);
9eef6280 329
879a57ac 330 dev_select(&port[num].ioaddr, dev);
9eef6280
DL		 331
332 status = 0;
879a57ac
TR		 333 cmd = ATA_CMD_IDENT; /* Device Identify Command */
334 sata_outb(cmd, port[num].ioaddr.command_addr);
335 sata_inb(port[num].ioaddr.altstatus_addr);
336 udelay(10);
9eef6280 337
879a57ac 338 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 1000);
9eef6280 339 if (status & ATA_ERR) {
879a57ac 340 puts("\ndevice not responding\n");
9eef6280
DL		 341 port[num].dev_mask &= ~mask;
342 return;
343 }
344
879a57ac 345 input_data(&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
9eef6280 346
879a57ac 347 debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
9eef6280
DL		 348 "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
349 iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
350 iobuf[87], iobuf[88]);
351
352 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
879a57ac
TR		 353 if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
354 debug("ata%u: no dma/lba\n", num);
355 ata_dump_id(iobuf);
9eef6280 356
879a57ac
TR		 357 if (ata_id_has_lba48(iobuf))
358 n_sectors = ata_id_u64(iobuf, 100);
359 else
360 n_sectors = ata_id_u32(iobuf, 60);
361 debug("no. of sectors %u\n", ata_id_u64(iobuf, 100));
362 debug("no. of sectors %u\n", ata_id_u32(iobuf, 60));
9eef6280
DL		 363
364 if (n_sectors == 0) {
365 port[num].dev_mask &= ~mask;
366 return;
367 }
368
879a57ac
TR		 369 sata_cpy((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
370 sizeof(sata_dev_desc[devno].revision));
371 sata_cpy((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
372 sizeof(sata_dev_desc[devno].vendor));
373 sata_cpy((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
374 sizeof(sata_dev_desc[devno].product));
375 strswab(sata_dev_desc[devno].revision);
376 strswab(sata_dev_desc[devno].vendor);
9eef6280 377
879a57ac 378 if ((iop->config & 0x0080) == 0x0080)
9eef6280 379 sata_dev_desc[devno].removable = 1;
879a57ac 380 else
9eef6280 381 sata_dev_desc[devno].removable = 0;
9eef6280
DL		 382
383 sata_dev_desc[devno].lba = iop->lba_capacity;
879a57ac 384 debug("lba=0x%x", sata_dev_desc[devno].lba);
9eef6280
DL		 385
386#ifdef CONFIG_LBA48
387 if (iop->command_set_2 & 0x0400) {
388 sata_dev_desc[devno].lba48 = 1;
389 lba = (unsigned long long) iop->lba48_capacity[0] |
390 ((unsigned long long) iop->lba48_capacity[1] << 16) |
391 ((unsigned long long) iop->lba48_capacity[2] << 32) |
392 ((unsigned long long) iop->lba48_capacity[3] << 48);
393 } else {
394 sata_dev_desc[devno].lba48 = 0;
395 }
396#endif
397
398 /* assuming HD */
399 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
400 sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
0472fbfd 401 sata_dev_desc[devno].log2blksz = LOG2(sata_dev_desc[devno].blksz);
9eef6280
DL		 402 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
403}
404
879a57ac 405void set_Feature_cmd(int num, int dev)
9eef6280
DL		 406{
407 u8 mask = 0x00, status = 0;
408
409 if (dev == 0)
410 mask = 0x01;
411 else
412 mask = 0x02;
413
414 if (!(port[num].dev_mask & mask)) {
879a57ac 415 debug("dev%d is not present on port#%d\n", dev, num);
9eef6280
DL		 416 return;
417 }
418
879a57ac 419 dev_select(&port[num].ioaddr, dev);
9eef6280 420
879a57ac
TR		 421 sata_outb(SETFEATURES_XFER, port[num].ioaddr.feature_addr);
422 sata_outb(XFER_PIO_4, port[num].ioaddr.nsect_addr);
423 sata_outb(0, port[num].ioaddr.lbal_addr);
424 sata_outb(0, port[num].ioaddr.lbam_addr);
425 sata_outb(0, port[num].ioaddr.lbah_addr);
9eef6280 426
879a57ac
TR		 427 sata_outb(ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
428 sata_outb(ATA_CMD_SETF, port[num].ioaddr.command_addr);
9eef6280 429
879a57ac
TR		 430 udelay(50);
431 mdelay(150);
9eef6280 432
879a57ac 433 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 5000);
9eef6280 434 if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
879a57ac 435 printf("Error : status 0x%02x\n", status);
9eef6280
DL		 436 port[num].dev_mask &= ~mask;
437 }
438}
439
879a57ac 440void sata_port(struct sata_ioports *ioport)
9eef6280
DL		 441{
442 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
443 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
444 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
445 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
446 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
447 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
448 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
449 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
450 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
451 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
452}
453
879a57ac 454int sata_devchk(struct sata_ioports *ioaddr, int dev)
9eef6280
DL		 455{
456 u8 nsect, lbal;
457
879a57ac 458 dev_select(ioaddr, dev);
9eef6280 459
879a57ac
TR		 460 sata_outb(0x55, ioaddr->nsect_addr);
461 sata_outb(0xaa, ioaddr->lbal_addr);
9eef6280 462
879a57ac
TR		 463 sata_outb(0xaa, ioaddr->nsect_addr);
464 sata_outb(0x55, ioaddr->lbal_addr);
9eef6280 465
879a57ac
TR		 466 sata_outb(0x55, ioaddr->nsect_addr);
467 sata_outb(0xaa, ioaddr->lbal_addr);
9eef6280 468
879a57ac
TR		 469 nsect = sata_inb(ioaddr->nsect_addr);
470 lbal = sata_inb(ioaddr->lbal_addr);
9eef6280
DL		 471
472 if ((nsect == 0x55) && (lbal == 0xaa))
473 return 1; /* we found a device */
474 else
475 return 0; /* nothing found */
476}
477
879a57ac 478void dev_select(struct sata_ioports *ioaddr, int dev)
9eef6280
DL		 479{
480 u8 tmp = 0;
481
482 if (dev == 0)
483 tmp = ATA_DEVICE_OBS;
484 else
485 tmp = ATA_DEVICE_OBS | ATA_DEV1;
486
879a57ac
TR		 487 sata_outb(tmp, ioaddr->device_addr);
488 sata_inb(ioaddr->altstatus_addr);
489 udelay(5);
9eef6280
DL		 490}
491
879a57ac 492u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max)
9eef6280
DL		 493{
494 u8 status;
495
496 do {
879a57ac
TR		 497 udelay(1000);
498 status = sata_chk_status(ioaddr);
9eef6280
DL		 499 max--;
500 } while ((status & bits) && (max > 0));
501
502 return status;
503}
504
879a57ac 505u8 sata_chk_status(struct sata_ioports *ioaddr)
9eef6280 506{
879a57ac 507 return sata_inb(ioaddr->status_addr);
9eef6280
DL		 508}
509
9eef6280 510
879a57ac 511ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buff)
9eef6280
DL		 512{
513 ulong n = 0, *buffer = (ulong *)buff;
514 u8 dev = 0, num = 0, mask = 0, status = 0;
515
516#ifdef CONFIG_LBA48
517 unsigned char lba48 = 0;
518
519 if (blknr & 0x0000fffff0000000) {
520 if (!sata_dev_desc[devno].lba48) {
879a57ac 521 printf("Drive doesn't support 48-bit addressing\n");
9eef6280
DL		 522 return 0;
523 }
524 /* more than 28 bits used, use 48bit mode */
525 lba48 = 1;
526 }
527#endif
879a57ac 528 /* Port Number */
6d0f6bcf 529 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
879a57ac 530 /* dev on the port */
6d0f6bcf
JCPV		 531 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
532 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
9eef6280
DL		 533 else
534 dev = device;
535
536 if (dev == 0)
537 mask = 0x01;
538 else
539 mask = 0x02;
540
541 if (!(port[num].dev_mask & mask)) {
879a57ac 542 printf("dev%d is not present on port#%d\n", dev, num);
9eef6280
DL		 543 return 0;
544 }
545
546 /* Select device */
879a57ac 547 dev_select(&port[num].ioaddr, dev);
9eef6280 548
879a57ac 549 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
9eef6280 550 if (status & ATA_BUSY) {
879a57ac 551 printf("ata%u failed to respond\n", port[num].port_no);
9eef6280
DL		 552 return n;
553 }
554 while (blkcnt-- > 0) {
879a57ac 555 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
9eef6280 556 if (status & ATA_BUSY) {
879a57ac 557 printf("ata%u failed to respond\n", 0);
9eef6280
DL		 558 return n;
559 }
560#ifdef CONFIG_LBA48
561 if (lba48) {
562 /* write high bits */
879a57ac
TR		 563 sata_outb(0, port[num].ioaddr.nsect_addr);
564 sata_outb((blknr >> 24) & 0xFF,
9eef6280 565 port[num].ioaddr.lbal_addr);
879a57ac 566 sata_outb((blknr >> 32) & 0xFF,
9eef6280 567 port[num].ioaddr.lbam_addr);
879a57ac 568 sata_outb((blknr >> 40) & 0xFF,
9eef6280
DL		 569 port[num].ioaddr.lbah_addr);
570 }
571#endif
879a57ac
TR		 572 sata_outb(1, port[num].ioaddr.nsect_addr);
573 sata_outb(((blknr) >> 0) & 0xFF,
9eef6280 574 port[num].ioaddr.lbal_addr);
879a57ac
TR		 575 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
576 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
9eef6280
DL		 577
578#ifdef CONFIG_LBA48
579 if (lba48) {
879a57ac
TR		 580 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
581 sata_outb(ATA_CMD_READ_EXT,
9eef6280
DL		 582 port[num].ioaddr.command_addr);
583 } else
584#endif
585 {
879a57ac 586 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
9eef6280 587 port[num].ioaddr.device_addr);
879a57ac 588 sata_outb(ATA_CMD_READ,
9eef6280
DL		 589 port[num].ioaddr.command_addr);
590 }
591
879a57ac
TR		 592 mdelay(50);
593 /* may take up to 4 sec */
594 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
9eef6280
DL		 595
596 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
597 != ATA_STAT_DRQ) {
598 u8 err = 0;
599
879a57ac 600 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
9eef6280 601 device, (ulong) blknr, status);
879a57ac
TR		 602 err = sata_inb(port[num].ioaddr.error_addr);
603 printf("Error reg = 0x%x\n", err);
604 return n;
9eef6280 605 }
879a57ac
TR		 606 input_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
607 sata_inb(port[num].ioaddr.altstatus_addr);
608 udelay(50);
9eef6280
DL		 609
610 ++n;
611 ++blknr;
612 buffer += ATA_SECTORWORDS;
613 }
614 return n;
615}
616
5048a672 617ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buff)
9eef6280
DL		 618{
619 ulong n = 0, *buffer = (ulong *)buff;
620 unsigned char status = 0, num = 0, dev = 0, mask = 0;
621
622#ifdef CONFIG_LBA48
623 unsigned char lba48 = 0;
624
625 if (blknr & 0x0000fffff0000000) {
626 if (!sata_dev_desc[devno].lba48) {
879a57ac 627 printf("Drive doesn't support 48-bit addressing\n");
9eef6280
DL		 628 return 0;
629 }
630 /* more than 28 bits used, use 48bit mode */
631 lba48 = 1;
632 }
633#endif
879a57ac 634 /* Port Number */
6d0f6bcf 635 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
879a57ac 636 /* dev on the Port */
6d0f6bcf
JCPV		 637 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
638 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
9eef6280
DL		 639 else
640 dev = device;
641
642 if (dev == 0)
643 mask = 0x01;
644 else
645 mask = 0x02;
646
647 /* Select device */
879a57ac 648 dev_select(&port[num].ioaddr, dev);
9eef6280 649
879a57ac 650 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
9eef6280 651 if (status & ATA_BUSY) {
879a57ac 652 printf("ata%u failed to respond\n", port[num].port_no);
9eef6280
DL		 653 return n;
654 }
655
656 while (blkcnt-- > 0) {
879a57ac 657 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
9eef6280 658 if (status & ATA_BUSY) {
879a57ac 659 printf("ata%u failed to respond\n",
9eef6280
DL		 660 port[num].port_no);
661 return n;
662 }
663#ifdef CONFIG_LBA48
664 if (lba48) {
665 /* write high bits */
879a57ac
TR		 666 sata_outb(0, port[num].ioaddr.nsect_addr);
667 sata_outb((blknr >> 24) & 0xFF,
9eef6280 668 port[num].ioaddr.lbal_addr);
879a57ac 669 sata_outb((blknr >> 32) & 0xFF,
9eef6280 670 port[num].ioaddr.lbam_addr);
879a57ac 671 sata_outb((blknr >> 40) & 0xFF,
9eef6280
DL		 672 port[num].ioaddr.lbah_addr);
673 }
674#endif
879a57ac
TR		 675 sata_outb(1, port[num].ioaddr.nsect_addr);
676 sata_outb((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
677 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
678 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
9eef6280
DL		 679#ifdef CONFIG_LBA48
680 if (lba48) {
879a57ac
TR		 681 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
682 sata_outb(ATA_CMD_WRITE_EXT,
9eef6280
DL		 683 port[num].ioaddr.command_addr);
684 } else
685#endif
686 {
879a57ac 687 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
9eef6280 688 port[num].ioaddr.device_addr);
879a57ac 689 sata_outb(ATA_CMD_WRITE,
9eef6280
DL		 690 port[num].ioaddr.command_addr);
691 }
692
879a57ac
TR		 693 mdelay(50);
694 /* may take up to 4 sec */
695 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
9eef6280
DL		 696 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
697 != ATA_STAT_DRQ) {
879a57ac 698 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
9eef6280 699 device, (ulong) blknr, status);
879a57ac 700 return n;
9eef6280
DL		 701 }
702
879a57ac
TR		 703 output_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
704 sata_inb(port[num].ioaddr.altstatus_addr);
705 udelay(50);
9eef6280
DL		 706
707 ++n;
708 ++blknr;
709 buffer += ATA_SECTORWORDS;
710 }
711 return n;
712}
713
8e9bb434 714int scan_sata(int dev)
9eef6280 715{
8e9bb434 716 return 0;
9eef6280 717}
"Das U-Boot" Source Tree