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sata: dwc_ahsata: implement sata_port_status
[people/ms/u-boot.git] / drivers / block / dwc_ahsata.c
CommitLineData
9f472e65
SB		 1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
9f472e65
SB		 6 */
7
8#include <libata.h>
9#include <ahci.h>
10#include <fis.h>
e46a4350 11#include <sata.h>
9f472e65
SB		 12
13#include <common.h>
14#include <malloc.h>
15#include <linux/ctype.h>
16#include <asm/errno.h>
17#include <asm/io.h>
18#include <linux/bitops.h>
19#include <asm/arch/clock.h>
ca84d72d 20#include <asm/arch/sys_proto.h>
9f472e65
SB		 21#include "dwc_ahsata.h"
22
23struct sata_port_regs {
24 u32 clb;
25 u32 clbu;
26 u32 fb;
27 u32 fbu;
28 u32 is;
29 u32 ie;
30 u32 cmd;
31 u32 res1[1];
32 u32 tfd;
33 u32 sig;
34 u32 ssts;
35 u32 sctl;
36 u32 serr;
37 u32 sact;
38 u32 ci;
39 u32 sntf;
40 u32 res2[1];
41 u32 dmacr;
42 u32 res3[1];
43 u32 phycr;
44 u32 physr;
45};
46
47struct sata_host_regs {
48 u32 cap;
49 u32 ghc;
50 u32 is;
51 u32 pi;
52 u32 vs;
53 u32 ccc_ctl;
54 u32 ccc_ports;
55 u32 res1[2];
56 u32 cap2;
57 u32 res2[30];
58 u32 bistafr;
59 u32 bistcr;
60 u32 bistfctr;
61 u32 bistsr;
62 u32 bistdecr;
63 u32 res3[2];
64 u32 oobr;
65 u32 res4[8];
66 u32 timer1ms;
67 u32 res5[1];
68 u32 gparam1r;
69 u32 gparam2r;
70 u32 pparamr;
71 u32 testr;
72 u32 versionr;
73 u32 idr;
74};
75
76#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
77#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
78
79#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
80
81static int is_ready;
82
83static inline u32 ahci_port_base(u32 base, u32 port)
84{
85 return base + 0x100 + (port * 0x80);
86}
87
88static int waiting_for_cmd_completed(u8 *offset,
89 int timeout_msec,
90 u32 sign)
91{
92 int i;
93 u32 status;
94
95 for (i = 0;
96 ((status = readl(offset)) & sign) && i < timeout_msec;
97 ++i)
98 mdelay(1);
99
100 return (i < timeout_msec) ? 0 : -1;
101}
102
103static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent,
104 int clk)
105{
106 struct sata_host_regs *host_mmio =
107 (struct sata_host_regs *)probe_ent->mmio_base;
108
109 writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr));
110 writel(0x02060b14, &(host_mmio->oobr));
111
112 return 0;
113}
114
115static int ahci_host_init(struct ahci_probe_ent *probe_ent)
116{
117 u32 tmp, cap_save, num_ports;
118 int i, j, timeout = 1000;
119 struct sata_port_regs *port_mmio = NULL;
120 struct sata_host_regs *host_mmio =
121 (struct sata_host_regs *)probe_ent->mmio_base;
122 int clk = mxc_get_clock(MXC_SATA_CLK);
123
124 cap_save = readl(&(host_mmio->cap));
125 cap_save |= SATA_HOST_CAP_SSS;
126
127 /* global controller reset */
128 tmp = readl(&(host_mmio->ghc));
129 if ((tmp & SATA_HOST_GHC_HR) == 0)
130 writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc));
131
132 while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR)
133 && --timeout)
134 ;
135
136 if (timeout <= 0) {
137 debug("controller reset failed (0x%x)\n", tmp);
138 return -1;
139 }
140
141 /* Set timer 1ms */
142 writel(clk / 1000, &(host_mmio->timer1ms));
143
144 ahci_setup_oobr(probe_ent, 0);
145
146 writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc));
147 writel(cap_save, &(host_mmio->cap));
148 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
149 writel_with_flush((1 << num_ports) - 1,
150 &(host_mmio->pi));
151
152 /*
153 * Determine which Ports are implemented by the DWC_ahsata,
154 * by reading the PI register. This bit map value aids the
155 * software to determine how many Ports are available and
156 * which Port registers need to be initialized.
157 */
158 probe_ent->cap = readl(&(host_mmio->cap));
159 probe_ent->port_map = readl(&(host_mmio->pi));
160
161 /* Determine how many command slots the HBA supports */
162 probe_ent->n_ports =
163 (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1;
164
165 debug("cap 0x%x port_map 0x%x n_ports %d\n",
166 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
167
168 for (i = 0; i < probe_ent->n_ports; i++) {
169 probe_ent->port[i].port_mmio =
170 ahci_port_base((u32)host_mmio, i);
171 port_mmio =
172 (struct sata_port_regs *)probe_ent->port[i].port_mmio;
173
174 /* Ensure that the DWC_ahsata is in idle state */
175 tmp = readl(&(port_mmio->cmd));
176
177 /*
178 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
179 * are all cleared, the Port is in an idle state.
180 */
181 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
182 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
183
184 /*
185 * System software places a Port into the idle state by
186 * clearing P#CMD.ST and waiting for P#CMD.CR to return
187 * 0 when read.
188 */
189 tmp &= ~SATA_PORT_CMD_ST;
190 writel_with_flush(tmp, &(port_mmio->cmd));
191
192 /*
193 * spec says 500 msecs for each bit, so
194 * this is slightly incorrect.
195 */
196 mdelay(500);
197
198 timeout = 1000;
199 while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR)
200 && --timeout)
201 ;
202
203 if (timeout <= 0) {
204 debug("port reset failed (0x%x)\n", tmp);
205 return -1;
206 }
207 }
208
209 /* Spin-up device */
210 tmp = readl(&(port_mmio->cmd));
211 writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd));
212
213 /* Wait for spin-up to finish */
214 timeout = 1000;
215 while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD)
216 && --timeout)
217 ;
218 if (timeout <= 0) {
219 debug("Spin-Up can't finish!\n");
220 return -1;
221 }
222
223 for (j = 0; j < 100; ++j) {
224 mdelay(10);
225 tmp = readl(&(port_mmio->ssts));
226 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
227 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
228 break;
229 }
230
231 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
232 timeout = 1000;
233 while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X)
234 && --timeout)
235 ;
236 if (timeout <= 0) {
237 debug("Can't find DIAG_X set!\n");
238 return -1;
239 }
240
241 /*
242 * For each implemented Port, clear the P#SERR
243 * register, by writing ones to each implemented\
244 * bit location.
245 */
246 tmp = readl(&(port_mmio->serr));
247 debug("P#SERR 0x%x\n",
248 tmp);
249 writel(tmp, &(port_mmio->serr));
250
251 /* Ack any pending irq events for this port */
252 tmp = readl(&(host_mmio->is));
253 debug("IS 0x%x\n", tmp);
254 if (tmp)
255 writel(tmp, &(host_mmio->is));
256
257 writel(1 << i, &(host_mmio->is));
258
259 /* set irq mask (enables interrupts) */
260 writel(DEF_PORT_IRQ, &(port_mmio->ie));
261
262 /* register linkup ports */
263 tmp = readl(&(port_mmio->ssts));
264 debug("Port %d status: 0x%x\n", i, tmp);
265 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
266 probe_ent->link_port_map |= (0x01 << i);
267 }
268
269 tmp = readl(&(host_mmio->ghc));
270 debug("GHC 0x%x\n", tmp);
271 writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc));
272 tmp = readl(&(host_mmio->ghc));
273 debug("GHC 0x%x\n", tmp);
274
275 return 0;
276}
277
278static void ahci_print_info(struct ahci_probe_ent *probe_ent)
279{
280 struct sata_host_regs *host_mmio =
281 (struct sata_host_regs *)probe_ent->mmio_base;
282 u32 vers, cap, impl, speed;
283 const char *speed_s;
284 const char *scc_s;
285
286 vers = readl(&(host_mmio->vs));
287 cap = probe_ent->cap;
288 impl = probe_ent->port_map;
289
290 speed = (cap & SATA_HOST_CAP_ISS_MASK)
291 >> SATA_HOST_CAP_ISS_OFFSET;
292 if (speed == 1)
293 speed_s = "1.5";
294 else if (speed == 2)
295 speed_s = "3";
296 else
297 speed_s = "?";
298
299 scc_s = "SATA";
300
301 printf("AHCI %02x%02x.%02x%02x "
302 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
303 (vers >> 24) & 0xff,
304 (vers >> 16) & 0xff,
305 (vers >> 8) & 0xff,
306 vers & 0xff,
307 ((cap >> 8) & 0x1f) + 1,
308 (cap & 0x1f) + 1,
309 speed_s,
310 impl,
311 scc_s);
312
313 printf("flags: "
314 "%s%s%s%s%s%s"
315 "%s%s%s%s%s%s%s\n",
316 cap & (1 << 31) ? "64bit " : "",
317 cap & (1 << 30) ? "ncq " : "",
318 cap & (1 << 28) ? "ilck " : "",
319 cap & (1 << 27) ? "stag " : "",
320 cap & (1 << 26) ? "pm " : "",
321 cap & (1 << 25) ? "led " : "",
322 cap & (1 << 24) ? "clo " : "",
323 cap & (1 << 19) ? "nz " : "",
324 cap & (1 << 18) ? "only " : "",
325 cap & (1 << 17) ? "pmp " : "",
326 cap & (1 << 15) ? "pio " : "",
327 cap & (1 << 14) ? "slum " : "",
328 cap & (1 << 13) ? "part " : "");
329}
330
331static int ahci_init_one(int pdev)
332{
333 int rc;
334 struct ahci_probe_ent *probe_ent = NULL;
335
336 probe_ent = malloc(sizeof(struct ahci_probe_ent));
337 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
338 probe_ent->dev = pdev;
339
340 probe_ent->host_flags = ATA_FLAG_SATA
341 | ATA_FLAG_NO_LEGACY
342 | ATA_FLAG_MMIO
343 | ATA_FLAG_PIO_DMA
344 | ATA_FLAG_NO_ATAPI;
345
346 probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
347
348 /* initialize adapter */
349 rc = ahci_host_init(probe_ent);
350 if (rc)
351 goto err_out;
352
353 ahci_print_info(probe_ent);
354
355 /* Save the private struct to block device struct */
356 sata_dev_desc[pdev].priv = (void *)probe_ent;
357
358 return 0;
359
360err_out:
361 return rc;
362}
363
364static int ahci_fill_sg(struct ahci_probe_ent *probe_ent,
365 u8 port, unsigned char *buf, int buf_len)
366{
367 struct ahci_ioports *pp = &(probe_ent->port[port]);
368 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
369 u32 sg_count, max_bytes;
370 int i;
371
372 max_bytes = MAX_DATA_BYTES_PER_SG;
373 sg_count = ((buf_len - 1) / max_bytes) + 1;
374 if (sg_count > AHCI_MAX_SG) {
375 printf("Error:Too much sg!\n");
376 return -1;
377 }
378
379 for (i = 0; i < sg_count; i++) {
380 ahci_sg->addr =
381 cpu_to_le32((u32)buf + i * max_bytes);
382 ahci_sg->addr_hi = 0;
383 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
384 (buf_len < max_bytes
385 ? (buf_len - 1)
386 : (max_bytes - 1)));
387 ahci_sg++;
388 buf_len -= max_bytes;
389 }
390
391 return sg_count;
392}
393
394static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
395{
396 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
397 AHCI_CMD_SLOT_SZ * cmd_slot);
398
399 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
400 cmd_hdr->opts = cpu_to_le32(opts);
401 cmd_hdr->status = 0;
402 cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
403 cmd_hdr->tbl_addr_hi = 0;
404}
405
406#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
407
408static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
409 u8 port, struct sata_fis_h2d *cfis,
410 u8 *buf, u32 buf_len, s32 is_write)
411{
412 struct ahci_ioports *pp = &(probe_ent->port[port]);
413 struct sata_port_regs *port_mmio =
414 (struct sata_port_regs *)pp->port_mmio;
415 u32 opts;
416 int sg_count = 0, cmd_slot = 0;
417
418 cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci)));
419 if (32 == cmd_slot) {
420 printf("Can't find empty command slot!\n");
421 return 0;
422 }
423
424 /* Check xfer length */
425 if (buf_len > MAX_BYTES_PER_TRANS) {
426 printf("Max transfer length is %dB\n\r",
427 MAX_BYTES_PER_TRANS);
428 return 0;
429 }
430
431 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
432 if (buf && buf_len)
433 sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
434 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
2dbe64ca 435 if (is_write) {
9f472e65 436 opts |= 0x40;
2dbe64ca
EN		 437 flush_cache((ulong)buf, buf_len);
438 }
9f472e65
SB		 439 ahci_fill_cmd_slot(pp, cmd_slot, opts);
440
2dbe64ca 441 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
9f472e65
SB		 442 writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
443
444 if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
445 10000, 0x1 << cmd_slot)) {
446 printf("timeout exit!\n");
447 return -1;
448 }
2dbe64ca
EN		 449 invalidate_dcache_range((int)(pp->cmd_slot),
450 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
9f472e65
SB		 451 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
452 pp->cmd_slot->status);
2dbe64ca
EN		 453 if (!is_write)
454 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
9f472e65
SB		 455
456 return buf_len;
457}
458
459static void ahci_set_feature(u8 dev, u8 port)
460{
461 struct ahci_probe_ent *probe_ent =
462 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 463 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
464 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 465
466 memset(cfis, 0, sizeof(struct sata_fis_h2d));
467 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
468 cfis->pm_port_c = 1 << 7;
469 cfis->command = ATA_CMD_SET_FEATURES;
470 cfis->features = SETFEATURES_XFER;
471 cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e;
472
473 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD);
474}
475
476static int ahci_port_start(struct ahci_probe_ent *probe_ent,
477 u8 port)
478{
479 struct ahci_ioports *pp = &(probe_ent->port[port]);
480 struct sata_port_regs *port_mmio =
481 (struct sata_port_regs *)pp->port_mmio;
482 u32 port_status;
483 u32 mem;
484 int timeout = 10000000;
485
486 debug("Enter start port: %d\n", port);
487 port_status = readl(&(port_mmio->ssts));
488 debug("Port %d status: %x\n", port, port_status);
489 if ((port_status & 0xf) != 0x03) {
490 printf("No Link on this port!\n");
491 return -1;
492 }
493
494 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
495 if (!mem) {
496 free(pp);
497 printf("No mem for table!\n");
498 return -ENOMEM;
499 }
500
501 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
502 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
503
504 /*
505 * First item in chunk of DMA memory: 32-slot command table,
506 * 32 bytes each in size
507 */
508 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
509 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
510 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
511
512 /*
513 * Second item: Received-FIS area, 256-Byte aligned
514 */
515 pp->rx_fis = mem;
516 mem += AHCI_RX_FIS_SZ;
517
518 /*
519 * Third item: data area for storing a single command
520 * and its scatter-gather table
521 */
522 pp->cmd_tbl = mem;
523 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
524
525 mem += AHCI_CMD_TBL_HDR;
526
527 writel_with_flush(0x00004444, &(port_mmio->dmacr));
528 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
529 writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb));
530 writel_with_flush(pp->rx_fis, &(port_mmio->fb));
531
532 /* Enable FRE */
533 writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))),
534 &(port_mmio->cmd));
535
536 /* Wait device ready */
537 while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR |
538 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
539 && --timeout)
540 ;
541 if (timeout <= 0) {
542 debug("Device not ready for BSY, DRQ and"
543 "ERR in TFD!\n");
544 return -1;
545 }
546
547 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
548 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
549 PORT_CMD_START, &(port_mmio->cmd));
550
551 debug("Exit start port %d\n", port);
552
553 return 0;
554}
555
556int init_sata(int dev)
557{
558 int i;
559 u32 linkmap;
560 struct ahci_probe_ent *probe_ent = NULL;
561
ca84d72d
TH		 562#if defined(CONFIG_MX6)
563 if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
564 return 1;
565#endif
9f472e65
SB		 566 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
567 printf("The sata index %d is out of ranges\n\r", dev);
568 return -1;
569 }
570
571 ahci_init_one(dev);
572
573 probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
574 linkmap = probe_ent->link_port_map;
575
576 if (0 == linkmap) {
577 printf("No port device detected!\n");
578 return 1;
579 }
580
581 for (i = 0; i < probe_ent->n_ports; i++) {
582 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
583 if (ahci_port_start(probe_ent, (u8)i)) {
584 printf("Can not start port %d\n", i);
585 return 1;
586 }
587 probe_ent->hard_port_no = i;
588 break;
589 }
590 }
591
592 return 0;
593}
594
595static void dwc_ahsata_print_info(int dev)
596{
597 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
598
599 printf("SATA Device Info:\n\r");
600#ifdef CONFIG_SYS_64BIT_LBA
601 printf("S/N: %s\n\rProduct model number: %s\n\r"
602 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
603 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
604#else
605 printf("S/N: %s\n\rProduct model number: %s\n\r"
606 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
607 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
608#endif
609}
610
611static void dwc_ahsata_identify(int dev, u16 *id)
612{
613 struct ahci_probe_ent *probe_ent =
614 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 615 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
616 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 617 u8 port = probe_ent->hard_port_no;
618
619 memset(cfis, 0, sizeof(struct sata_fis_h2d));
620
621 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
622 cfis->pm_port_c = 0x80; /* is command */
623 cfis->command = ATA_CMD_ID_ATA;
624
625 ahci_exec_ata_cmd(probe_ent, port, cfis,
626 (u8 *)id, ATA_ID_WORDS * 2, READ_CMD);
627 ata_swap_buf_le16(id, ATA_ID_WORDS);
628}
629
630static void dwc_ahsata_xfer_mode(int dev, u16 *id)
631{
632 struct ahci_probe_ent *probe_ent =
633 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
634
635 probe_ent->pio_mask = id[ATA_ID_PIO_MODES];
636 probe_ent->udma_mask = id[ATA_ID_UDMA_MODES];
637 debug("pio %04x, udma %04x\n\r",
638 probe_ent->pio_mask, probe_ent->udma_mask);
639}
640
641static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
642 u8 *buffer, int is_write)
643{
644 struct ahci_probe_ent *probe_ent =
645 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 646 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
647 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 648 u8 port = probe_ent->hard_port_no;
649 u32 block;
650
651 block = start;
652
653 memset(cfis, 0, sizeof(struct sata_fis_h2d));
654
655 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
656 cfis->pm_port_c = 0x80; /* is command */
657 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
658 cfis->device = ATA_LBA;
659
660 cfis->device |= (block >> 24) & 0xf;
661 cfis->lba_high = (block >> 16) & 0xff;
662 cfis->lba_mid = (block >> 8) & 0xff;
663 cfis->lba_low = block & 0xff;
664 cfis->sector_count = (u8)(blkcnt & 0xff);
665
666 if (ahci_exec_ata_cmd(probe_ent, port, cfis,
667 buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0)
668 return blkcnt;
669 else
670 return 0;
671}
672
673void dwc_ahsata_flush_cache(int dev)
674{
675 struct ahci_probe_ent *probe_ent =
676 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 677 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
678 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 679 u8 port = probe_ent->hard_port_no;
680
681 memset(cfis, 0, sizeof(struct sata_fis_h2d));
682
683 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
684 cfis->pm_port_c = 0x80; /* is command */
685 cfis->command = ATA_CMD_FLUSH;
686
687 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
688}
689
690static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
691 u8 *buffer, int is_write)
692{
693 struct ahci_probe_ent *probe_ent =
694 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 695 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
696 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 697 u8 port = probe_ent->hard_port_no;
698 u64 block;
699
700 block = (u64)start;
701
702 memset(cfis, 0, sizeof(struct sata_fis_h2d));
703
704 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
705 cfis->pm_port_c = 0x80; /* is command */
706
707 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
708 : ATA_CMD_READ_EXT;
709
710 cfis->lba_high_exp = (block >> 40) & 0xff;
711 cfis->lba_mid_exp = (block >> 32) & 0xff;
712 cfis->lba_low_exp = (block >> 24) & 0xff;
713 cfis->lba_high = (block >> 16) & 0xff;
714 cfis->lba_mid = (block >> 8) & 0xff;
715 cfis->lba_low = block & 0xff;
716 cfis->device = ATA_LBA;
717 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
718 cfis->sector_count = blkcnt & 0xff;
719
720 if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer,
721 ATA_SECT_SIZE * blkcnt, is_write) > 0)
722 return blkcnt;
723 else
724 return 0;
725}
726
727u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
728 u8 *buffer, int is_write)
729{
730 struct ahci_probe_ent *probe_ent =
731 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 732 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
733 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 734 u8 port = probe_ent->hard_port_no;
735 u64 block;
736
737 if (sata_dev_desc[dev].lba48 != 1) {
738 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
739 return -1;
740 }
741
742 block = (u64)start;
743
744 memset(cfis, 0, sizeof(struct sata_fis_h2d));
745
746 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
747 cfis->pm_port_c = 0x80; /* is command */
748
749 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
750 : ATA_CMD_FPDMA_READ;
751
752 cfis->lba_high_exp = (block >> 40) & 0xff;
753 cfis->lba_mid_exp = (block >> 32) & 0xff;
754 cfis->lba_low_exp = (block >> 24) & 0xff;
755 cfis->lba_high = (block >> 16) & 0xff;
756 cfis->lba_mid = (block >> 8) & 0xff;
757 cfis->lba_low = block & 0xff;
758
759 cfis->device = ATA_LBA;
760 cfis->features_exp = (blkcnt >> 8) & 0xff;
761 cfis->features = blkcnt & 0xff;
762
763 /* Use the latest queue */
764 ahci_exec_ata_cmd(probe_ent, port, cfis,
765 buffer, ATA_SECT_SIZE * blkcnt, is_write);
766
767 return blkcnt;
768}
769
770void dwc_ahsata_flush_cache_ext(int dev)
771{
772 struct ahci_probe_ent *probe_ent =
773 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 774 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
775 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 776 u8 port = probe_ent->hard_port_no;
777
778 memset(cfis, 0, sizeof(struct sata_fis_h2d));
779
780 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
781 cfis->pm_port_c = 0x80; /* is command */
782 cfis->command = ATA_CMD_FLUSH_EXT;
783
784 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
785}
786
787static void dwc_ahsata_init_wcache(int dev, u16 *id)
788{
789 struct ahci_probe_ent *probe_ent =
790 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
791
792 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
793 probe_ent->flags |= SATA_FLAG_WCACHE;
794 if (ata_id_has_flush(id))
795 probe_ent->flags |= SATA_FLAG_FLUSH;
796 if (ata_id_has_flush_ext(id))
797 probe_ent->flags |= SATA_FLAG_FLUSH_EXT;
798}
799
800u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
dac87571 801 const void *buffer, int is_write)
9f472e65
SB		 802{
803 u32 start, blks;
804 u8 *addr;
805 int max_blks;
806
807 start = blknr;
808 blks = blkcnt;
809 addr = (u8 *)buffer;
810
811 max_blks = ATA_MAX_SECTORS_LBA48;
812
813 do {
814 if (blks > max_blks) {
815 if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start,
816 max_blks, addr, is_write))
817 return 0;
818 start += max_blks;
819 blks -= max_blks;
820 addr += ATA_SECT_SIZE * max_blks;
821 } else {
822 if (blks != dwc_ahsata_rw_cmd_ext(dev, start,
823 blks, addr, is_write))
824 return 0;
825 start += blks;
826 blks = 0;
827 addr += ATA_SECT_SIZE * blks;
828 }
829 } while (blks != 0);
830
831 return blkcnt;
832}
833
834u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
dac87571 835 const void *buffer, int is_write)
9f472e65
SB		 836{
837 u32 start, blks;
838 u8 *addr;
839 int max_blks;
840
841 start = blknr;
842 blks = blkcnt;
843 addr = (u8 *)buffer;
844
845 max_blks = ATA_MAX_SECTORS;
846 do {
847 if (blks > max_blks) {
848 if (max_blks != dwc_ahsata_rw_cmd(dev, start,
849 max_blks, addr, is_write))
850 return 0;
851 start += max_blks;
852 blks -= max_blks;
853 addr += ATA_SECT_SIZE * max_blks;
854 } else {
855 if (blks != dwc_ahsata_rw_cmd(dev, start,
856 blks, addr, is_write))
857 return 0;
858 start += blks;
859 blks = 0;
860 addr += ATA_SECT_SIZE * blks;
861 }
862 } while (blks != 0);
863
864 return blkcnt;
865}
866
dc383dd5
NK		 867int sata_port_status(int dev, int port)
868{
869 struct sata_port_regs *port_mmio;
870 struct ahci_probe_ent *probe_ent = NULL;
871
872 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
873 return -EINVAL;
874
875 if (sata_dev_desc[dev].priv == NULL)
876 return -ENODEV;
877
878 probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
879 port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
880
881 return readl(&(port_mmio->ssts)) && SATA_PORT_SSTS_DET_MASK;
882}
883
9f472e65
SB		 884/*
885 * SATA interface between low level driver and command layer
886 */
dac87571 887ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
9f472e65
SB		 888{
889 u32 rc;
890
891 if (sata_dev_desc[dev].lba48)
892 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
893 buffer, READ_CMD);
894 else
895 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
896 buffer, READ_CMD);
897 return rc;
898}
899
dac87571 900ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
9f472e65
SB		 901{
902 u32 rc;
903 struct ahci_probe_ent *probe_ent =
904 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
905 u32 flags = probe_ent->flags;
906
907 if (sata_dev_desc[dev].lba48) {
908 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
909 buffer, WRITE_CMD);
910 if ((flags & SATA_FLAG_WCACHE) &&
911 (flags & SATA_FLAG_FLUSH_EXT))
912 dwc_ahsata_flush_cache_ext(dev);
913 } else {
914 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
915 buffer, WRITE_CMD);
916 if ((flags & SATA_FLAG_WCACHE) &&
917 (flags & SATA_FLAG_FLUSH))
918 dwc_ahsata_flush_cache(dev);
919 }
920 return rc;
921}
922
923int scan_sata(int dev)
924{
925 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
926 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
927 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
928 u16 *id;
929 u64 n_sectors;
930 struct ahci_probe_ent *probe_ent =
931 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
932 u8 port = probe_ent->hard_port_no;
933 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
934
2dbe64ca
EN		 935 id = (u16 *)memalign(ARCH_DMA_MINALIGN,
936 roundup(ARCH_DMA_MINALIGN,
937 (ATA_ID_WORDS * 2)));
9f472e65
SB		 938 if (!id) {
939 printf("id malloc failed\n\r");
940 return -1;
941 }
942
943 /* Identify device to get information */
944 dwc_ahsata_identify(dev, id);
945
946 /* Serial number */
947 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
948 memcpy(pdev->product, serial, sizeof(serial));
949
950 /* Firmware version */
951 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
952 memcpy(pdev->revision, firmware, sizeof(firmware));
953
954 /* Product model */
955 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
956 memcpy(pdev->vendor, product, sizeof(product));
957
958 /* Totoal sectors */
959 n_sectors = ata_id_n_sectors(id);
960 pdev->lba = (u32)n_sectors;
961
962 pdev->type = DEV_TYPE_HARDDISK;
963 pdev->blksz = ATA_SECT_SIZE;
964 pdev->lun = 0 ;
965
966 /* Check if support LBA48 */
967 if (ata_id_has_lba48(id)) {
968 pdev->lba48 = 1;
969 debug("Device support LBA48\n\r");
970 }
971
972 /* Get the NCQ queue depth from device */
973 probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK);
974 probe_ent->flags |= ata_id_queue_depth(id);
975
976 /* Get the xfer mode from device */
977 dwc_ahsata_xfer_mode(dev, id);
978
979 /* Get the write cache status from device */
980 dwc_ahsata_init_wcache(dev, id);
981
982 /* Set the xfer mode to highest speed */
983 ahci_set_feature(dev, port);
984
985 free((void *)id);
986
987 dwc_ahsata_print_info(dev);
988
989 is_ready = 1;
990
991 return 0;
992}
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