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fd0b1fe3 DL |
1 | /* |
2 | * Copyright (C) 2008 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <common.h> | |
22 | #include <command.h> | |
23 | #include <asm/io.h> | |
24 | #include <malloc.h> | |
25 | #include <libata.h> | |
26 | #include <fis.h> | |
27 | #include "fsl_sata.h" | |
28 | ||
6d0f6bcf | 29 | extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; |
fd0b1fe3 | 30 | |
6d0f6bcf JCPV |
31 | #ifndef CONFIG_SYS_SATA1_FLAGS |
32 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
fd0b1fe3 | 33 | #endif |
6d0f6bcf JCPV |
34 | #ifndef CONFIG_SYS_SATA2_FLAGS |
35 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
fd0b1fe3 DL |
36 | #endif |
37 | ||
38 | static struct fsl_sata_info fsl_sata_info[] = { | |
39 | #ifdef CONFIG_SATA1 | |
6d0f6bcf | 40 | {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS}, |
fd0b1fe3 DL |
41 | #else |
42 | {0, 0}, | |
43 | #endif | |
44 | #ifdef CONFIG_SATA2 | |
6d0f6bcf | 45 | {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS}, |
fd0b1fe3 DL |
46 | #else |
47 | {0, 0}, | |
48 | #endif | |
49 | }; | |
50 | ||
51 | static inline void mdelay(unsigned long msec) | |
52 | { | |
53 | unsigned long i; | |
54 | for (i = 0; i < msec; i++) | |
55 | udelay(1000); | |
56 | } | |
57 | ||
58 | static inline void sdelay(unsigned long sec) | |
59 | { | |
60 | unsigned long i; | |
61 | for (i = 0; i < sec; i++) | |
62 | mdelay(1000); | |
63 | } | |
64 | ||
65 | void dprint_buffer(unsigned char *buf, int len) | |
66 | { | |
67 | int i, j; | |
68 | ||
69 | i = 0; | |
70 | j = 0; | |
71 | printf("\n\r"); | |
72 | ||
73 | for (i = 0; i < len; i++) { | |
74 | printf("%02x ", *buf++); | |
75 | j++; | |
76 | if (j == 16) { | |
77 | printf("\n\r"); | |
78 | j = 0; | |
79 | } | |
80 | } | |
81 | printf("\n\r"); | |
82 | } | |
83 | ||
84 | static void fsl_sata_dump_sfis(struct sfis *s) | |
85 | { | |
86 | printf("Status FIS dump:\n\r"); | |
87 | printf("fis_type: %02x\n\r", s->fis_type); | |
88 | printf("pm_port_i: %02x\n\r", s->pm_port_i); | |
89 | printf("status: %02x\n\r", s->status); | |
90 | printf("error: %02x\n\r", s->error); | |
91 | printf("lba_low: %02x\n\r", s->lba_low); | |
92 | printf("lba_mid: %02x\n\r", s->lba_mid); | |
93 | printf("lba_high: %02x\n\r", s->lba_high); | |
94 | printf("device: %02x\n\r", s->device); | |
95 | printf("lba_low_exp: %02x\n\r", s->lba_low_exp); | |
96 | printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp); | |
97 | printf("lba_high_exp: %02x\n\r", s->lba_high_exp); | |
98 | printf("res1: %02x\n\r", s->res1); | |
99 | printf("sector_count: %02x\n\r", s->sector_count); | |
100 | printf("sector_count_exp: %02x\n\r", s->sector_count_exp); | |
101 | } | |
102 | ||
103 | static int ata_wait_register(volatile unsigned *addr, u32 mask, | |
104 | u32 val, u32 timeout_msec) | |
105 | { | |
106 | int i; | |
107 | u32 temp; | |
108 | ||
109 | for (i = 0; (((temp = in_le32(addr)) & mask) != val) | |
110 | && i < timeout_msec; i++) | |
111 | mdelay(1); | |
112 | return (i < timeout_msec) ? 0 : -1; | |
113 | } | |
114 | ||
115 | int init_sata(int dev) | |
116 | { | |
117 | u32 length, align; | |
118 | cmd_hdr_tbl_t *cmd_hdr; | |
119 | u32 cda; | |
120 | u32 val32; | |
121 | fsl_sata_reg_t *reg; | |
122 | u32 sig; | |
123 | int i; | |
124 | fsl_sata_t *sata; | |
125 | ||
6d0f6bcf | 126 | if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { |
fd0b1fe3 DL |
127 | printf("the sata index %d is out of ranges\n\r", dev); |
128 | return -1; | |
129 | } | |
130 | ||
131 | /* Allocate SATA device driver struct */ | |
132 | sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t)); | |
133 | if (!sata) { | |
134 | printf("alloc the sata device struct failed\n\r"); | |
135 | return -1; | |
136 | } | |
137 | /* Zero all of the device driver struct */ | |
138 | memset((void *)sata, 0, sizeof(fsl_sata_t)); | |
139 | ||
140 | /* Save the private struct to block device struct */ | |
141 | sata_dev_desc[dev].priv = (void *)sata; | |
142 | ||
143 | sprintf(sata->name, "SATA%d", dev); | |
144 | ||
145 | /* Set the controller register base address to device struct */ | |
146 | reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base); | |
147 | sata->reg_base = reg; | |
148 | ||
149 | /* Allocate the command header table, 4 bytes aligned */ | |
150 | length = sizeof(struct cmd_hdr_tbl); | |
151 | align = SATA_HC_CMD_HDR_TBL_ALIGN; | |
152 | sata->cmd_hdr_tbl_offset = (void *)malloc(length + align); | |
153 | if (!sata) { | |
154 | printf("alloc the command header failed\n\r"); | |
155 | return -1; | |
156 | } | |
157 | ||
158 | cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align) | |
159 | & ~(align - 1)); | |
160 | sata->cmd_hdr = cmd_hdr; | |
161 | ||
162 | /* Zero all of the command header table */ | |
163 | memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align); | |
164 | ||
165 | /* Allocate command descriptor for all command */ | |
166 | length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD; | |
167 | align = SATA_HC_CMD_DESC_ALIGN; | |
168 | sata->cmd_desc_offset = (void *)malloc(length + align); | |
169 | if (!sata->cmd_desc_offset) { | |
170 | printf("alloc the command descriptor failed\n\r"); | |
171 | return -1; | |
172 | } | |
173 | sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align) | |
174 | & ~(align - 1)); | |
175 | /* Zero all of command descriptor */ | |
176 | memset((void *)sata->cmd_desc_offset, 0, length + align); | |
177 | ||
178 | /* Link the command descriptor to command header */ | |
179 | for (i = 0; i < SATA_HC_MAX_CMD; i++) { | |
180 | cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i) | |
181 | & ~(CMD_HDR_CDA_ALIGN - 1); | |
182 | cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda); | |
183 | } | |
184 | ||
185 | /* To have safe state, force the controller offline */ | |
186 | val32 = in_le32(®->hcontrol); | |
187 | val32 &= ~HCONTROL_ONOFF; | |
188 | val32 |= HCONTROL_FORCE_OFFLINE; | |
189 | out_le32(®->hcontrol, val32); | |
190 | ||
191 | /* Wait the controller offline */ | |
192 | ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000); | |
193 | ||
194 | /* Set the command header base address to CHBA register to tell DMA */ | |
195 | out_le32(®->chba, (u32)cmd_hdr & ~0x3); | |
196 | ||
197 | /* Snoop for the command header */ | |
198 | val32 = in_le32(®->hcontrol); | |
199 | val32 |= HCONTROL_HDR_SNOOP; | |
200 | out_le32(®->hcontrol, val32); | |
201 | ||
202 | /* Disable all of interrupts */ | |
203 | val32 = in_le32(®->hcontrol); | |
204 | val32 &= ~HCONTROL_INT_EN_ALL; | |
205 | out_le32(®->hcontrol, val32); | |
206 | ||
207 | /* Clear all of interrupts */ | |
208 | val32 = in_le32(®->hstatus); | |
209 | out_le32(®->hstatus, val32); | |
210 | ||
211 | /* Set the ICC, no interrupt coalescing */ | |
212 | out_le32(®->icc, 0x01000000); | |
213 | ||
214 | /* No PM attatched, the SATA device direct connect */ | |
215 | out_le32(®->cqpmp, 0); | |
216 | ||
217 | /* Clear SError register */ | |
218 | val32 = in_le32(®->serror); | |
219 | out_le32(®->serror, val32); | |
220 | ||
221 | /* Clear CER register */ | |
222 | val32 = in_le32(®->cer); | |
223 | out_le32(®->cer, val32); | |
224 | ||
225 | /* Clear DER register */ | |
226 | val32 = in_le32(®->der); | |
227 | out_le32(®->der, val32); | |
228 | ||
229 | /* No device detection or initialization action requested */ | |
230 | out_le32(®->scontrol, 0x00000300); | |
231 | ||
232 | /* Configure the transport layer, default value */ | |
233 | out_le32(®->transcfg, 0x08000016); | |
234 | ||
235 | /* Configure the link layer, default value */ | |
236 | out_le32(®->linkcfg, 0x0000ff34); | |
237 | ||
238 | /* Bring the controller online */ | |
239 | val32 = in_le32(®->hcontrol); | |
240 | val32 |= HCONTROL_ONOFF; | |
241 | out_le32(®->hcontrol, val32); | |
242 | ||
243 | mdelay(100); | |
244 | ||
245 | /* print sata device name */ | |
246 | if (!dev) | |
247 | printf("%s ", sata->name); | |
248 | else | |
249 | printf(" %s ", sata->name); | |
250 | ||
9810263a DL |
251 | /* Wait PHY RDY signal changed for 500ms */ |
252 | ata_wait_register(®->hstatus, HSTATUS_PHY_RDY, | |
253 | HSTATUS_PHY_RDY, 500); | |
254 | ||
fd0b1fe3 DL |
255 | /* Check PHYRDY */ |
256 | val32 = in_le32(®->hstatus); | |
257 | if (val32 & HSTATUS_PHY_RDY) { | |
258 | sata->link = 1; | |
259 | } else { | |
260 | sata->link = 0; | |
261 | printf("(No RDY)\n\r"); | |
262 | return -1; | |
263 | } | |
264 | ||
9810263a DL |
265 | /* Wait for signature updated, which is 1st D2H */ |
266 | ata_wait_register(®->hstatus, HSTATUS_SIGNATURE, | |
267 | HSTATUS_SIGNATURE, 10000); | |
268 | ||
fd0b1fe3 DL |
269 | if (val32 & HSTATUS_SIGNATURE) { |
270 | sig = in_le32(®->sig); | |
271 | debug("Signature updated, the sig =%08x\n\r", sig); | |
272 | sata->ata_device_type = ata_dev_classify(sig); | |
273 | } | |
274 | ||
275 | /* Check the speed */ | |
276 | val32 = in_le32(®->sstatus); | |
277 | if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1) | |
278 | printf("(1.5 Gbps)\n\r"); | |
279 | else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2) | |
280 | printf("(3 Gbps)\n\r"); | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
285 | /* Hardware reset, like Power-on and COMRESET */ | |
286 | void fsl_sata_hardware_reset(u32 reg_base) | |
287 | { | |
288 | fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base; | |
289 | u32 scontrol; | |
290 | ||
291 | /* Disable the SATA interface and put PHY offline */ | |
292 | scontrol = in_le32(®->scontrol); | |
293 | scontrol = (scontrol & 0x0f0) | 0x304; | |
294 | out_le32(®->scontrol, scontrol); | |
295 | ||
296 | /* No speed strict */ | |
297 | scontrol = in_le32(®->scontrol); | |
298 | scontrol = scontrol & ~0x0f0; | |
299 | out_le32(®->scontrol, scontrol); | |
300 | ||
301 | /* Issue PHY wake/reset, Hardware_reset_asserted */ | |
302 | scontrol = in_le32(®->scontrol); | |
303 | scontrol = (scontrol & 0x0f0) | 0x301; | |
304 | out_le32(®->scontrol, scontrol); | |
305 | ||
306 | mdelay(100); | |
307 | ||
308 | /* Resume PHY, COMRESET negated, the device initialize hardware | |
309 | * and execute diagnostics, send good status-signature to host, | |
310 | * which is D2H register FIS, and then the device enter idle state. | |
311 | */ | |
312 | scontrol = in_le32(®->scontrol); | |
313 | scontrol = (scontrol & 0x0f0) | 0x300; | |
314 | out_le32(®->scontrol, scontrol); | |
315 | ||
316 | mdelay(100); | |
317 | return; | |
318 | } | |
319 | ||
320 | static void fsl_sata_dump_regs(fsl_sata_reg_t *reg) | |
321 | { | |
322 | printf("\n\rSATA: %08x\n\r", (u32)reg); | |
323 | printf("CQR: %08x\n\r", in_le32(®->cqr)); | |
324 | printf("CAR: %08x\n\r", in_le32(®->car)); | |
325 | printf("CCR: %08x\n\r", in_le32(®->ccr)); | |
326 | printf("CER: %08x\n\r", in_le32(®->cer)); | |
327 | printf("CQR: %08x\n\r", in_le32(®->cqr)); | |
328 | printf("DER: %08x\n\r", in_le32(®->der)); | |
329 | printf("CHBA: %08x\n\r", in_le32(®->chba)); | |
330 | printf("HStatus: %08x\n\r", in_le32(®->hstatus)); | |
331 | printf("HControl: %08x\n\r", in_le32(®->hcontrol)); | |
332 | printf("CQPMP: %08x\n\r", in_le32(®->cqpmp)); | |
333 | printf("SIG: %08x\n\r", in_le32(®->sig)); | |
334 | printf("ICC: %08x\n\r", in_le32(®->icc)); | |
335 | printf("SStatus: %08x\n\r", in_le32(®->sstatus)); | |
336 | printf("SError: %08x\n\r", in_le32(®->serror)); | |
337 | printf("SControl: %08x\n\r", in_le32(®->scontrol)); | |
338 | printf("SNotification: %08x\n\r", in_le32(®->snotification)); | |
339 | printf("TransCfg: %08x\n\r", in_le32(®->transcfg)); | |
340 | printf("TransStatus: %08x\n\r", in_le32(®->transstatus)); | |
341 | printf("LinkCfg: %08x\n\r", in_le32(®->linkcfg)); | |
342 | printf("LinkCfg1: %08x\n\r", in_le32(®->linkcfg1)); | |
343 | printf("LinkCfg2: %08x\n\r", in_le32(®->linkcfg2)); | |
344 | printf("LinkStatus: %08x\n\r", in_le32(®->linkstatus)); | |
345 | printf("LinkStatus1: %08x\n\r", in_le32(®->linkstatus1)); | |
346 | printf("PhyCtrlCfg: %08x\n\r", in_le32(®->phyctrlcfg)); | |
347 | printf("SYSPR: %08x\n\r", in_be32(®->syspr)); | |
348 | } | |
349 | ||
350 | static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct cfis *cfis, | |
351 | int is_ncq, int tag, u8 *buffer, u32 len) | |
352 | { | |
353 | cmd_hdr_entry_t *cmd_hdr; | |
354 | cmd_desc_t *cmd_desc; | |
355 | sata_fis_h2d_t *h2d; | |
356 | prd_entry_t *prde; | |
357 | u32 ext_c_ddc; | |
358 | u32 prde_count; | |
359 | u32 val32; | |
360 | u32 ttl; | |
361 | fsl_sata_reg_t *reg = sata->reg_base; | |
362 | int i; | |
363 | ||
364 | /* Check xfer length */ | |
365 | if (len > SATA_HC_MAX_XFER_LEN) { | |
366 | printf("max transfer length is 64MB\n\r"); | |
367 | return 0; | |
368 | } | |
369 | ||
370 | /* Setup the command descriptor */ | |
371 | cmd_desc = sata->cmd_desc + tag; | |
372 | ||
373 | /* Get the pointer cfis of command descriptor */ | |
374 | h2d = (sata_fis_h2d_t *)cmd_desc->cfis; | |
375 | ||
376 | /* Zero the cfis of command descriptor */ | |
377 | memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE); | |
378 | ||
379 | /* Copy the cfis from user to command descriptor */ | |
380 | h2d->fis_type = cfis->fis_type; | |
381 | h2d->pm_port_c = cfis->pm_port_c; | |
382 | h2d->command = cfis->command; | |
383 | ||
384 | h2d->features = cfis->features; | |
385 | h2d->features_exp = cfis->features_exp; | |
386 | ||
387 | h2d->lba_low = cfis->lba_low; | |
388 | h2d->lba_mid = cfis->lba_mid; | |
389 | h2d->lba_high = cfis->lba_high; | |
390 | h2d->lba_low_exp = cfis->lba_low_exp; | |
391 | h2d->lba_mid_exp = cfis->lba_mid_exp; | |
392 | h2d->lba_high_exp = cfis->lba_high_exp; | |
393 | ||
394 | if (!is_ncq) { | |
395 | h2d->sector_count = cfis->sector_count; | |
396 | h2d->sector_count_exp = cfis->sector_count_exp; | |
397 | } else { /* NCQ */ | |
398 | h2d->sector_count = (u8)(tag << 3); | |
399 | } | |
400 | ||
401 | h2d->device = cfis->device; | |
402 | h2d->control = cfis->control; | |
403 | ||
404 | /* Setup the PRD table */ | |
405 | prde = (prd_entry_t *)cmd_desc->prdt; | |
406 | memset((void *)prde, 0, sizeof(struct prdt)); | |
407 | ||
408 | prde_count = 0; | |
409 | ttl = len; | |
410 | for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) { | |
411 | if (!len) | |
412 | break; | |
413 | prde->dba = cpu_to_le32((u32)buffer & ~0x3); | |
414 | debug("dba = %08x\n\r", (u32)buffer); | |
415 | ||
416 | if (len < PRD_ENTRY_MAX_XFER_SZ) { | |
417 | ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len; | |
418 | debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len); | |
419 | prde->ext_c_ddc = cpu_to_le32(ext_c_ddc); | |
420 | prde_count++; | |
421 | prde++; | |
422 | break; | |
423 | } else { | |
424 | ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */ | |
425 | debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len); | |
426 | prde->ext_c_ddc = cpu_to_le32(ext_c_ddc); | |
427 | buffer += PRD_ENTRY_MAX_XFER_SZ; | |
428 | len -= PRD_ENTRY_MAX_XFER_SZ; | |
429 | prde_count++; | |
430 | prde++; | |
431 | } | |
432 | } | |
433 | ||
434 | /* Setup the command slot of cmd hdr */ | |
435 | cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag]; | |
436 | ||
437 | cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3); | |
438 | ||
439 | val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT; | |
440 | val32 |= sizeof(sata_fis_h2d_t); | |
441 | cmd_hdr->prde_fis_len = cpu_to_le32(val32); | |
442 | ||
443 | cmd_hdr->ttl = cpu_to_le32(ttl); | |
444 | ||
445 | if (!is_ncq) { | |
446 | val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP; | |
447 | } else { | |
448 | val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA; | |
449 | } | |
450 | ||
451 | tag &= CMD_HDR_ATTR_TAG; | |
452 | val32 |= tag; | |
453 | ||
454 | debug("attribute = %08x\n\r", val32); | |
455 | cmd_hdr->attribute = cpu_to_le32(val32); | |
456 | ||
457 | /* Make sure cmd desc and cmd slot valid before commmand issue */ | |
458 | sync(); | |
459 | ||
460 | /* PMP*/ | |
461 | val32 = (u32)(h2d->pm_port_c & 0x0f); | |
462 | out_le32(®->cqpmp, val32); | |
463 | ||
464 | /* Wait no active */ | |
465 | if (ata_wait_register(®->car, (1 << tag), 0, 10000)) | |
466 | printf("Wait no active time out\n\r"); | |
467 | ||
468 | /* Issue command */ | |
469 | if (!(in_le32(®->cqr) & (1 << tag))) { | |
470 | val32 = 1 << tag; | |
471 | out_le32(®->cqr, val32); | |
472 | } | |
473 | ||
474 | /* Wait command completed for 10s */ | |
475 | if (ata_wait_register(®->ccr, (1 << tag), (1 << tag), 10000)) { | |
476 | if (!is_ncq) | |
477 | printf("Non-NCQ command time out\n\r"); | |
478 | else | |
479 | printf("NCQ command time out\n\r"); | |
480 | } | |
481 | ||
482 | val32 = in_le32(®->cer); | |
483 | ||
484 | if (val32) { | |
485 | u32 der; | |
486 | fsl_sata_dump_sfis((struct sfis *)cmd_desc->sfis); | |
487 | printf("CE at device\n\r"); | |
488 | fsl_sata_dump_regs(reg); | |
489 | der = in_le32(®->der); | |
490 | out_le32(®->cer, val32); | |
491 | out_le32(®->der, der); | |
492 | } | |
493 | ||
494 | /* Clear complete flags */ | |
495 | val32 = in_le32(®->ccr); | |
496 | out_le32(®->ccr, val32); | |
497 | ||
498 | return len; | |
499 | } | |
500 | ||
501 | static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct cfis *cfis, | |
502 | int tag, u8 *buffer, u32 len) | |
503 | { | |
504 | return 0; | |
505 | } | |
506 | ||
507 | static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct cfis *cfis, | |
508 | enum cmd_type command_type, int tag, u8 *buffer, u32 len) | |
509 | { | |
510 | int rc; | |
511 | ||
512 | if (tag > SATA_HC_MAX_CMD || tag < 0) { | |
4109df6f | 513 | printf("tag is out of range, tag=%d\n\r", tag); |
fd0b1fe3 DL |
514 | return -1; |
515 | } | |
516 | ||
517 | switch (command_type) { | |
518 | case CMD_ATA: | |
519 | rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len); | |
520 | return rc; | |
521 | case CMD_RESET: | |
522 | rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len); | |
523 | return rc; | |
524 | case CMD_NCQ: | |
525 | rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len); | |
526 | return rc; | |
527 | case CMD_ATAPI: | |
528 | case CMD_VENDOR_BIST: | |
529 | case CMD_BIST: | |
530 | printf("not support now\n\r"); | |
531 | return -1; | |
532 | default: | |
533 | break; | |
534 | } | |
535 | ||
536 | return -1; | |
537 | } | |
538 | ||
539 | static void fsl_sata_identify(int dev, u16 *id) | |
540 | { | |
541 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
542 | struct sata_fis_h2d h2d; | |
543 | struct cfis *cfis; | |
544 | ||
545 | cfis = (struct cfis *)&h2d; | |
546 | memset((void *)cfis, 0, sizeof(struct cfis)); | |
547 | ||
548 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
549 | cfis->pm_port_c = 0x80; /* is command */ | |
550 | cfis->command = ATA_CMD_ID_ATA; | |
551 | ||
552 | fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2); | |
553 | ata_swap_buf_le16(id, ATA_ID_WORDS); | |
554 | } | |
555 | ||
556 | static void fsl_sata_xfer_mode(int dev, u16 *id) | |
557 | { | |
558 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
559 | ||
560 | sata->pio = id[ATA_ID_PIO_MODES]; | |
561 | sata->mwdma = id[ATA_ID_MWDMA_MODES]; | |
562 | sata->udma = id[ATA_ID_UDMA_MODES]; | |
563 | debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma); | |
564 | } | |
565 | ||
566 | static void fsl_sata_set_features(int dev) | |
567 | { | |
568 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
569 | struct sata_fis_h2d h2d; | |
570 | struct cfis *cfis; | |
571 | u8 udma_cap; | |
572 | ||
573 | cfis = (struct cfis *)&h2d; | |
574 | memset((void *)cfis, 0, sizeof(struct cfis)); | |
575 | ||
576 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
577 | cfis->pm_port_c = 0x80; /* is command */ | |
578 | cfis->command = ATA_CMD_SET_FEATURES; | |
579 | cfis->features = SETFEATURES_XFER; | |
580 | ||
581 | /* First check the device capablity */ | |
582 | udma_cap = (u8)(sata->udma & 0xff); | |
583 | debug("udma_cap %02x\n\r", udma_cap); | |
584 | ||
585 | if (udma_cap == ATA_UDMA6) | |
586 | cfis->sector_count = XFER_UDMA_6; | |
587 | if (udma_cap == ATA_UDMA5) | |
588 | cfis->sector_count = XFER_UDMA_5; | |
589 | if (udma_cap == ATA_UDMA4) | |
590 | cfis->sector_count = XFER_UDMA_4; | |
591 | if (udma_cap == ATA_UDMA3) | |
592 | cfis->sector_count = XFER_UDMA_3; | |
593 | ||
594 | fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0); | |
595 | } | |
596 | ||
597 | static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write) | |
598 | { | |
599 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
600 | struct sata_fis_h2d h2d; | |
601 | struct cfis *cfis; | |
602 | u32 block; | |
603 | ||
604 | block = start; | |
605 | cfis = (struct cfis *)&h2d; | |
606 | ||
607 | memset((void *)cfis, 0, sizeof(struct cfis)); | |
608 | ||
609 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
610 | cfis->pm_port_c = 0x80; /* is command */ | |
24b44844 | 611 | cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; |
fd0b1fe3 DL |
612 | cfis->device = ATA_LBA; |
613 | ||
614 | cfis->device |= (block >> 24) & 0xf; | |
615 | cfis->lba_high = (block >> 16) & 0xff; | |
616 | cfis->lba_mid = (block >> 8) & 0xff; | |
617 | cfis->lba_low = block & 0xff; | |
618 | cfis->sector_count = (u8)(blkcnt & 0xff); | |
619 | ||
620 | fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt); | |
621 | return blkcnt; | |
622 | } | |
623 | ||
624 | void fsl_sata_flush_cache(int dev) | |
625 | { | |
626 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
627 | struct sata_fis_h2d h2d; | |
628 | struct cfis *cfis; | |
629 | ||
630 | cfis = (struct cfis *)&h2d; | |
631 | ||
632 | memset((void *)cfis, 0, sizeof(struct cfis)); | |
633 | ||
634 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
635 | cfis->pm_port_c = 0x80; /* is command */ | |
24b44844 | 636 | cfis->command = ATA_CMD_FLUSH; |
fd0b1fe3 DL |
637 | |
638 | fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0); | |
639 | } | |
640 | ||
641 | static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write) | |
642 | { | |
643 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
644 | struct sata_fis_h2d h2d; | |
645 | struct cfis *cfis; | |
646 | u64 block; | |
647 | ||
648 | block = (u64)start; | |
649 | cfis = (struct cfis *)&h2d; | |
650 | ||
651 | memset((void *)cfis, 0, sizeof(struct cfis)); | |
652 | ||
653 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
654 | cfis->pm_port_c = 0x80; /* is command */ | |
655 | ||
24b44844 DL |
656 | cfis->command = (is_write) ? ATA_CMD_WRITE_EXT |
657 | : ATA_CMD_READ_EXT; | |
fd0b1fe3 DL |
658 | |
659 | cfis->lba_high_exp = (block >> 40) & 0xff; | |
660 | cfis->lba_mid_exp = (block >> 32) & 0xff; | |
661 | cfis->lba_low_exp = (block >> 24) & 0xff; | |
662 | cfis->lba_high = (block >> 16) & 0xff; | |
663 | cfis->lba_mid = (block >> 8) & 0xff; | |
664 | cfis->lba_low = block & 0xff; | |
665 | cfis->device = ATA_LBA; | |
666 | cfis->sector_count_exp = (blkcnt >> 8) & 0xff; | |
667 | cfis->sector_count = blkcnt & 0xff; | |
668 | ||
669 | fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt); | |
670 | return blkcnt; | |
671 | } | |
672 | ||
673 | u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write) | |
674 | { | |
675 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
676 | struct sata_fis_h2d h2d; | |
677 | struct cfis *cfis; | |
678 | int ncq_channel; | |
679 | u64 block; | |
680 | ||
681 | if (sata_dev_desc[dev].lba48 != 1) { | |
682 | printf("execute FPDMA command on non-LBA48 hard disk\n\r"); | |
683 | return -1; | |
684 | } | |
685 | ||
686 | block = (u64)start; | |
687 | cfis = (struct cfis *)&h2d; | |
688 | ||
689 | memset((void *)cfis, 0, sizeof(struct cfis)); | |
690 | ||
691 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
692 | cfis->pm_port_c = 0x80; /* is command */ | |
693 | ||
24b44844 DL |
694 | cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE |
695 | : ATA_CMD_FPDMA_READ; | |
fd0b1fe3 DL |
696 | |
697 | cfis->lba_high_exp = (block >> 40) & 0xff; | |
698 | cfis->lba_mid_exp = (block >> 32) & 0xff; | |
699 | cfis->lba_low_exp = (block >> 24) & 0xff; | |
700 | cfis->lba_high = (block >> 16) & 0xff; | |
701 | cfis->lba_mid = (block >> 8) & 0xff; | |
702 | cfis->lba_low = block & 0xff; | |
703 | ||
704 | cfis->device = ATA_LBA; | |
705 | cfis->features_exp = (blkcnt >> 8) & 0xff; | |
706 | cfis->features = blkcnt & 0xff; | |
707 | ||
708 | if (sata->queue_depth >= SATA_HC_MAX_CMD) | |
709 | ncq_channel = SATA_HC_MAX_CMD - 1; | |
710 | else | |
711 | ncq_channel = sata->queue_depth - 1; | |
712 | ||
713 | /* Use the latest queue */ | |
714 | fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt); | |
715 | return blkcnt; | |
716 | } | |
717 | ||
718 | void fsl_sata_flush_cache_ext(int dev) | |
719 | { | |
720 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
721 | struct sata_fis_h2d h2d; | |
722 | struct cfis *cfis; | |
723 | ||
724 | cfis = (struct cfis *)&h2d; | |
725 | ||
726 | memset((void *)cfis, 0, sizeof(struct cfis)); | |
727 | ||
728 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
729 | cfis->pm_port_c = 0x80; /* is command */ | |
24b44844 | 730 | cfis->command = ATA_CMD_FLUSH_EXT; |
fd0b1fe3 DL |
731 | |
732 | fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0); | |
733 | } | |
734 | ||
735 | /* Software reset, set SRST of the Device Control register */ | |
736 | void fsl_sata_software_reset(int dev) | |
737 | { | |
738 | return; | |
739 | } | |
740 | ||
741 | static void fsl_sata_init_wcache(int dev, u16 *id) | |
742 | { | |
743 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
744 | ||
745 | if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) | |
746 | sata->wcache = 1; | |
747 | if (ata_id_has_flush(id)) | |
748 | sata->flush = 1; | |
749 | if (ata_id_has_flush_ext(id)) | |
750 | sata->flush_ext = 1; | |
751 | } | |
752 | ||
753 | static int fsl_sata_get_wcache(int dev) | |
754 | { | |
755 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
756 | return sata->wcache; | |
757 | } | |
758 | ||
759 | static int fsl_sata_get_flush(int dev) | |
760 | { | |
761 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
762 | return sata->flush; | |
763 | } | |
764 | ||
765 | static int fsl_sata_get_flush_ext(int dev) | |
766 | { | |
767 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
768 | return sata->flush_ext; | |
769 | } | |
770 | ||
771 | u32 ata_low_level_rw_lba48(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write) | |
772 | { | |
773 | u32 start, blks; | |
774 | u8 *addr; | |
775 | int max_blks; | |
776 | ||
777 | start = blknr; | |
778 | blks = blkcnt; | |
779 | addr = (u8 *)buffer; | |
780 | ||
781 | max_blks = ATA_MAX_SECTORS_LBA48; | |
782 | do { | |
783 | if (blks > max_blks) { | |
784 | if (fsl_sata_info[dev].flags != FLAGS_FPDMA) | |
785 | fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write); | |
786 | else | |
787 | fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write); | |
788 | start += max_blks; | |
789 | blks -= max_blks; | |
790 | addr += ATA_SECT_SIZE * max_blks; | |
791 | } else { | |
792 | if (fsl_sata_info[dev].flags != FLAGS_FPDMA) | |
793 | fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write); | |
794 | else | |
795 | fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write); | |
796 | start += blks; | |
797 | blks = 0; | |
798 | addr += ATA_SECT_SIZE * blks; | |
799 | } | |
800 | } while (blks != 0); | |
801 | ||
802 | return blkcnt; | |
803 | } | |
804 | ||
805 | u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write) | |
806 | { | |
807 | u32 start, blks; | |
808 | u8 *addr; | |
809 | int max_blks; | |
810 | ||
811 | start = blknr; | |
812 | blks = blkcnt; | |
813 | addr = (u8 *)buffer; | |
814 | ||
815 | max_blks = ATA_MAX_SECTORS; | |
816 | do { | |
817 | if (blks > max_blks) { | |
818 | fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write); | |
819 | start += max_blks; | |
820 | blks -= max_blks; | |
821 | addr += ATA_SECT_SIZE * max_blks; | |
822 | } else { | |
823 | fsl_sata_rw_cmd(dev, start, blks, addr, is_write); | |
824 | start += blks; | |
825 | blks = 0; | |
826 | addr += ATA_SECT_SIZE * blks; | |
827 | } | |
828 | } while (blks != 0); | |
829 | ||
830 | return blkcnt; | |
831 | } | |
832 | ||
833 | /* | |
834 | * SATA interface between low level driver and command layer | |
835 | */ | |
836 | ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer) | |
837 | { | |
838 | u32 rc; | |
839 | ||
840 | if (sata_dev_desc[dev].lba48) | |
841 | rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD); | |
842 | else | |
843 | rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD); | |
844 | return rc; | |
845 | } | |
846 | ||
847 | ulong sata_write(int dev, u32 blknr, u32 blkcnt, void *buffer) | |
848 | { | |
849 | u32 rc; | |
850 | ||
851 | if (sata_dev_desc[dev].lba48) { | |
852 | rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD); | |
853 | if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev)) | |
854 | fsl_sata_flush_cache_ext(dev); | |
855 | } else { | |
856 | rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD); | |
857 | if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev)) | |
858 | fsl_sata_flush_cache(dev); | |
859 | } | |
860 | return rc; | |
861 | } | |
862 | ||
863 | int scan_sata(int dev) | |
864 | { | |
865 | fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; | |
866 | unsigned char serial[ATA_ID_SERNO_LEN + 1]; | |
867 | unsigned char firmware[ATA_ID_FW_REV_LEN + 1]; | |
868 | unsigned char product[ATA_ID_PROD_LEN + 1]; | |
869 | u16 *id; | |
870 | u64 n_sectors; | |
871 | ||
872 | /* if no detected link */ | |
873 | if (!sata->link) | |
874 | return -1; | |
875 | ||
876 | id = (u16 *)malloc(ATA_ID_WORDS * 2); | |
877 | if (!id) { | |
878 | printf("id malloc failed\n\r"); | |
879 | return -1; | |
880 | } | |
881 | ||
882 | /* Identify device to get information */ | |
883 | fsl_sata_identify(dev, id); | |
884 | ||
885 | /* Serial number */ | |
886 | ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); | |
887 | memcpy(sata_dev_desc[dev].product, serial, sizeof(serial)); | |
888 | ||
889 | /* Firmware version */ | |
890 | ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); | |
891 | memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware)); | |
892 | ||
893 | /* Product model */ | |
894 | ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); | |
895 | memcpy(sata_dev_desc[dev].vendor, product, sizeof(product)); | |
896 | ||
897 | /* Totoal sectors */ | |
898 | n_sectors = ata_id_n_sectors(id); | |
899 | sata_dev_desc[dev].lba = (u32)n_sectors; | |
900 | ||
901 | /* Check if support LBA48 */ | |
902 | if (ata_id_has_lba48(id)) { | |
903 | sata_dev_desc[dev].lba48 = 1; | |
904 | debug("Device support LBA48\n\r"); | |
905 | } | |
906 | ||
907 | /* Get the NCQ queue depth from device */ | |
908 | sata->queue_depth = ata_id_queue_depth(id); | |
909 | ||
910 | /* Get the xfer mode from device */ | |
911 | fsl_sata_xfer_mode(dev, id); | |
912 | ||
913 | /* Get the write cache status from device */ | |
914 | fsl_sata_init_wcache(dev, id); | |
915 | ||
916 | /* Set the xfer mode to highest speed */ | |
917 | fsl_sata_set_features(dev); | |
918 | #ifdef DEBUG | |
919 | fsl_sata_identify(dev, id); | |
920 | ata_dump_id(id); | |
921 | #endif | |
922 | free((void *)id); | |
923 | return 0; | |
924 | } |