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dm355 evm support
[people/ms/u-boot.git] / drivers / block / pata_bfin.c
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8a6b2725
SZ		 1/*
2 * Driver for Blackfin on-chip ATAPI controller.
3 *
4 * Enter bugs at http://blackfin.uclinux.org/
5 *
6 * Copyright (c) 2008 Analog Devices Inc.
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#include <common.h>
12#include <command.h>
13#include <config.h>
14#include <asm/byteorder.h>
15#include <asm/io.h>
16#include <asm/errno.h>
17#include <asm/mach-common/bits/pata.h>
18#include <ata.h>
19#include <libata.h>
20#include "pata_bfin.h"
21
22static struct ata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
23
24/**
25 * PIO Mode - Frequency compatibility
26 */
27/* mode: 0 1 2 3 4 */
28static const u32 pio_fsclk[] =
29{ 33333333, 33333333, 33333333, 33333333, 33333333 };
30
31/**
32 * MDMA Mode - Frequency compatibility
33 */
34/* mode: 0 1 2 */
35static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
36
37/**
38 * UDMA Mode - Frequency compatibility
39 *
40 * UDMA5 - 100 MB/s - SCLK = 133 MHz
41 * UDMA4 - 66 MB/s - SCLK >= 80 MHz
42 * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz
43 * UDMA2 - 33 MB/s - SCLK >= 40 MHz
44 */
45/* mode: 0 1 2 3 4 5 */
46static const u32 udma_fsclk[] =
47{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
48
49/**
50 * Register transfer timing table
51 */
52/* mode: 0 1 2 3 4 */
53/* Cycle Time */
54static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 };
55/* DIOR/DIOW to end cycle */
56static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 };
57/* DIOR/DIOW asserted pulse width */
58static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 };
59
60/**
61 * PIO timing table
62 */
63/* mode: 0 1 2 3 4 */
64/* Cycle Time */
65static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 };
66/* Address valid to DIOR/DIORW */
67static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 };
68/* DIOR/DIOW to end cycle */
69static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 };
70/* DIOR/DIOW asserted pulse width */
71static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 };
72/* DIOW data hold */
73static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 };
74
75/* ******************************************************************
76 * Multiword DMA timing table
77 * ******************************************************************
78 */
79/* mode: 0 1 2 */
80/* Cycle Time */
81static const u32 mdma_t0min[] = { 480, 150, 120 };
82/* DIOR/DIOW asserted pulse width */
83static const u32 mdma_tdmin[] = { 215, 80, 70 };
84/* DMACK to read data released */
85static const u32 mdma_thmin[] = { 20, 15, 10 };
86/* DIOR/DIOW to DMACK hold */
87static const u32 mdma_tjmin[] = { 20, 5, 5 };
88/* DIOR negated pulse width */
89static const u32 mdma_tkrmin[] = { 50, 50, 25 };
90/* DIOR negated pulse width */
91static const u32 mdma_tkwmin[] = { 215, 50, 25 };
92/* CS[1:0] valid to DIOR/DIOW */
93static const u32 mdma_tmmin[] = { 50, 30, 25 };
94/* DMACK to read data released */
95static const u32 mdma_tzmax[] = { 20, 25, 25 };
96
97/**
98 * Ultra DMA timing table
99 */
100/* mode: 0 1 2 3 4 5 */
101static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 };
102static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 };
103static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 };
104static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 };
105static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 };
106
107
108static const u32 udma_tmlimin = 20;
109static const u32 udma_tzahmin = 20;
110static const u32 udma_tenvmin = 20;
111static const u32 udma_tackmin = 20;
112static const u32 udma_tssmin = 50;
113
114static void msleep(int count)
115{
116 int i;
117
118 for (i = 0; i < count; i++)
119 udelay(1000);
120}
121
122/**
123 *
124 * Function: num_clocks_min
125 *
126 * Description:
127 * calculate number of SCLK cycles to meet minimum timing
128 */
129static unsigned short num_clocks_min(unsigned long tmin,
130 unsigned long fsclk)
131{
132 unsigned long tmp ;
133 unsigned short result;
134
135 tmp = tmin * (fsclk/1000/1000) / 1000;
136 result = (unsigned short)tmp;
137 if ((tmp*1000*1000) < (tmin*(fsclk/1000)))
138 result++;
139
140 return result;
141}
142
143/**
144 * bfin_set_piomode - Initialize host controller PATA PIO timings
145 * @ap: Port whose timings we are configuring
146 * @pio_mode: mode
147 *
148 * Set PIO mode for device.
149 *
150 * LOCKING:
151 * None (inherited from caller).
152 */
153
154static void bfin_set_piomode(struct ata_port *ap, int pio_mode)
155{
156 int mode = pio_mode - XFER_PIO_0;
157 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
158 unsigned int fsclk = get_sclk();
159 unsigned short teoc_reg, t2_reg, teoc_pio;
160 unsigned short t4_reg, t2_pio, t1_reg;
161 unsigned short n0, n6, t6min = 5;
162
163 /* the most restrictive timing value is t6 and tc, the DIOW - data hold
164 * If one SCLK pulse is longer than this minimum value then register
165 * transfers cannot be supported at this frequency.
166 */
167 n6 = num_clocks_min(t6min, fsclk);
168 if (mode >= 0 && mode <= 4 && n6 >= 1) {
169 debug("set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
170 /* calculate the timing values for register transfers. */
171 while (mode > 0 && pio_fsclk[mode] > fsclk)
172 mode--;
173
174 /* DIOR/DIOW to end cycle time */
175 t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
176 /* DIOR/DIOW asserted pulse width */
177 teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
178 /* Cycle Time */
179 n0 = num_clocks_min(reg_t0min[mode], fsclk);
180
181 /* increase t2 until we meed the minimum cycle length */
182 if (t2_reg + teoc_reg < n0)
183 t2_reg = n0 - teoc_reg;
184
185 /* calculate the timing values for pio transfers. */
186
187 /* DIOR/DIOW to end cycle time */
188 t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
189 /* DIOR/DIOW asserted pulse width */
190 teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
191 /* Cycle Time */
192 n0 = num_clocks_min(pio_t0min[mode], fsclk);
193
194 /* increase t2 until we meed the minimum cycle length */
195 if (t2_pio + teoc_pio < n0)
196 t2_pio = n0 - teoc_pio;
197
198 /* Address valid to DIOR/DIORW */
199 t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
200
201 /* DIOW data hold */
202 t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
203
204 ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
205 ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
206 ATAPI_SET_PIO_TIM_1(base, teoc_pio);
207 if (mode > 2) {
208 ATAPI_SET_CONTROL(base,
209 ATAPI_GET_CONTROL(base) | IORDY_EN);
210 } else {
211 ATAPI_SET_CONTROL(base,
212 ATAPI_GET_CONTROL(base) & ~IORDY_EN);
213 }
214
215 /* Disable host ATAPI PIO interrupts */
216 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
217 & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
218 SSYNC();
219 }
220}
221
222/**
223 *
224 * Function: wait_complete
225 *
226 * Description: Waits the interrupt from device
227 *
228 */
229static inline void wait_complete(void __iomem *base, unsigned short mask)
230{
231 unsigned short status;
232 unsigned int i = 0;
233
234 for (i = 0; i < PATA_BFIN_WAIT_TIMEOUT; i++) {
235 status = ATAPI_GET_INT_STATUS(base) & mask;
236 if (status)
237 break;
238 }
239
240 ATAPI_SET_INT_STATUS(base, mask);
241}
242
243/**
244 *
245 * Function: write_atapi_register
246 *
247 * Description: Writes to ATA Device Resgister
248 *
249 */
250
251static void write_atapi_register(void __iomem *base,
252 unsigned long ata_reg, unsigned short value)
253{
254 /* Program the ATA_DEV_TXBUF register with write data (to be
255 * written into the device).
256 */
257 ATAPI_SET_DEV_TXBUF(base, value);
258
259 /* Program the ATA_DEV_ADDR register with address of the
260 * device register (0x01 to 0x0F).
261 */
262 ATAPI_SET_DEV_ADDR(base, ata_reg);
263
264 /* Program the ATA_CTRL register with dir set to write (1)
265 */
266 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
267
268 /* ensure PIO DMA is not set */
269 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
270
271 /* and start the transfer */
272 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
273
274 /* Wait for the interrupt to indicate the end of the transfer.
275 * (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
276 */
277 wait_complete(base, PIO_DONE_INT);
278}
279
280/**
281 *
282 * Function: read_atapi_register
283 *
284 *Description: Reads from ATA Device Resgister
285 *
286 */
287
288static unsigned short read_atapi_register(void __iomem *base,
289 unsigned long ata_reg)
290{
291 /* Program the ATA_DEV_ADDR register with address of the
292 * device register (0x01 to 0x0F).
293 */
294 ATAPI_SET_DEV_ADDR(base, ata_reg);
295
296 /* Program the ATA_CTRL register with dir set to read (0) and
297 */
298 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
299
300 /* ensure PIO DMA is not set */
301 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
302
303 /* and start the transfer */
304 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
305
306 /* Wait for the interrupt to indicate the end of the transfer.
307 * (PIO_DONE interrupt is set and it doesn't seem to matter
308 * that we don't clear it)
309 */
310 wait_complete(base, PIO_DONE_INT);
311
312 /* Read the ATA_DEV_RXBUF register with write data (to be
313 * written into the device).
314 */
315 return ATAPI_GET_DEV_RXBUF(base);
316}
317
318/**
319 *
320 * Function: write_atapi_register_data
321 *
322 * Description: Writes to ATA Device Resgister
323 *
324 */
325
326static void write_atapi_data(void __iomem *base,
327 int len, unsigned short *buf)
328{
329 int i;
330
331 /* Set transfer length to 1 */
332 ATAPI_SET_XFER_LEN(base, 1);
333
334 /* Program the ATA_DEV_ADDR register with address of the
335 * ATA_REG_DATA
336 */
337 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
338
339 /* Program the ATA_CTRL register with dir set to write (1)
340 */
341 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
342
343 /* ensure PIO DMA is not set */
344 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
345
346 for (i = 0; i < len; i++) {
347 /* Program the ATA_DEV_TXBUF register with write data (to be
348 * written into the device).
349 */
350 ATAPI_SET_DEV_TXBUF(base, buf[i]);
351
352 /* and start the transfer */
353 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
354
355 /* Wait for the interrupt to indicate the end of the transfer.
356 * (We need to wait on and clear rhe ATA_DEV_INT
357 * interrupt status)
358 */
359 wait_complete(base, PIO_DONE_INT);
360 }
361}
362
363/**
364 *
365 * Function: read_atapi_register_data
366 *
367 * Description: Reads from ATA Device Resgister
368 *
369 */
370
371static void read_atapi_data(void __iomem *base,
372 int len, unsigned short *buf)
373{
374 int i;
375
376 /* Set transfer length to 1 */
377 ATAPI_SET_XFER_LEN(base, 1);
378
379 /* Program the ATA_DEV_ADDR register with address of the
380 * ATA_REG_DATA
381 */
382 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
383
384 /* Program the ATA_CTRL register with dir set to read (0) and
385 */
386 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
387
388 /* ensure PIO DMA is not set */
389 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
390
391 for (i = 0; i < len; i++) {
392 /* and start the transfer */
393 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
394
395 /* Wait for the interrupt to indicate the end of the transfer.
396 * (PIO_DONE interrupt is set and it doesn't seem to matter
397 * that we don't clear it)
398 */
399 wait_complete(base, PIO_DONE_INT);
400
401 /* Read the ATA_DEV_RXBUF register with write data (to be
402 * written into the device).
403 */
404 buf[i] = ATAPI_GET_DEV_RXBUF(base);
405 }
406}
407
408/**
409 * bfin_check_status - Read device status reg & clear interrupt
410 * @ap: port where the device is
411 *
412 * Note: Original code is ata_check_status().
413 */
414
415static u8 bfin_check_status(struct ata_port *ap)
416{
417 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
418 return read_atapi_register(base, ATA_REG_STATUS);
419}
420
421/**
422 * bfin_check_altstatus - Read device alternate status reg
423 * @ap: port where the device is
424 */
425
426static u8 bfin_check_altstatus(struct ata_port *ap)
427{
428 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
429 return read_atapi_register(base, ATA_REG_ALTSTATUS);
430}
431
432/**
433 * bfin_ata_busy_wait - Wait for a port status register
434 * @ap: Port to wait for.
435 * @bits: bits that must be clear
436 * @max: number of 10uS waits to perform
437 *
438 * Waits up to max*10 microseconds for the selected bits in the port's
439 * status register to be cleared.
440 * Returns final value of status register.
441 *
442 * LOCKING:
443 * Inherited from caller.
444 */
445static inline u8 bfin_ata_busy_wait(struct ata_port *ap, unsigned int bits,
446 unsigned int max, u8 usealtstatus)
447{
448 u8 status;
449
450 do {
451 udelay(10);
452 if (usealtstatus)
453 status = bfin_check_altstatus(ap);
454 else
455 status = bfin_check_status(ap);
456 max--;
457 } while (status != 0xff && (status & bits) && (max > 0));
458
459 return status;
460}
461
462/**
463 * bfin_ata_busy_sleep - sleep until BSY clears, or timeout
464 * @ap: port containing status register to be polled
465 * @tmout_pat: impatience timeout in msecs
466 * @tmout: overall timeout in msecs
467 *
468 * Sleep until ATA Status register bit BSY clears,
469 * or a timeout occurs.
470 *
471 * RETURNS:
472 * 0 on success, -errno otherwise.
473 */
474static int bfin_ata_busy_sleep(struct ata_port *ap,
475 long tmout_pat, unsigned long tmout)
476{
477 u8 status;
478
479 status = bfin_ata_busy_wait(ap, ATA_BUSY, 300, 0);
480 while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
481 msleep(50);
482 tmout_pat -= 50;
483 status = bfin_ata_busy_wait(ap, ATA_BUSY, 3, 0);
484 }
485
486 if (status != 0xff && (status & ATA_BUSY))
487 printf("port is slow to respond, please be patient "
488 "(Status 0x%x)\n", status);
489
490 while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
491 msleep(50);
492 tmout_pat -= 50;
493 status = bfin_check_status(ap);
494 }
495
496 if (status == 0xff)
497 return -ENODEV;
498
499 if (status & ATA_BUSY) {
500 printf("port failed to respond "
501 "(%lu secs, Status 0x%x)\n",
502 DIV_ROUND_UP(tmout, 1000), status);
503 return -EBUSY;
504 }
505
506 return 0;
507}
508
509/**
510 * bfin_dev_select - Select device 0/1 on ATA bus
511 * @ap: ATA channel to manipulate
512 * @device: ATA device (numbered from zero) to select
513 *
514 * Note: Original code is ata_sff_dev_select().
515 */
516
517static void bfin_dev_select(struct ata_port *ap, unsigned int device)
518{
519 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
520 u8 tmp;
521
522
523 if (device == 0)
524 tmp = ATA_DEVICE_OBS;
525 else
526 tmp = ATA_DEVICE_OBS | ATA_DEV1;
527
528 write_atapi_register(base, ATA_REG_DEVICE, tmp);
529 udelay(1);
530}
531
532/**
533 * bfin_devchk - PATA device presence detection
534 * @ap: ATA channel to examine
535 * @device: Device to examine (starting at zero)
536 *
537 * Note: Original code is ata_devchk().
538 */
539
540static unsigned int bfin_devchk(struct ata_port *ap,
541 unsigned int device)
542{
543 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
544 u8 nsect, lbal;
545
546 bfin_dev_select(ap, device);
547
548 write_atapi_register(base, ATA_REG_NSECT, 0x55);
549 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
550
551 write_atapi_register(base, ATA_REG_NSECT, 0xaa);
552 write_atapi_register(base, ATA_REG_LBAL, 0x55);
553
554 write_atapi_register(base, ATA_REG_NSECT, 0x55);
555 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
556
557 nsect = read_atapi_register(base, ATA_REG_NSECT);
558 lbal = read_atapi_register(base, ATA_REG_LBAL);
559
560 if ((nsect == 0x55) && (lbal == 0xaa))
561 return 1; /* we found a device */
562
563 return 0; /* nothing found */
564}
565
566/**
567 * bfin_bus_post_reset - PATA device post reset
568 *
569 * Note: Original code is ata_bus_post_reset().
570 */
571
572static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
573{
574 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
575 unsigned int dev0 = devmask & (1 << 0);
576 unsigned int dev1 = devmask & (1 << 1);
577 long deadline;
578
579 /* if device 0 was found in ata_devchk, wait for its
580 * BSY bit to clear
581 */
582 if (dev0)
583 bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
584
585 /* if device 1 was found in ata_devchk, wait for
586 * register access, then wait for BSY to clear
587 */
588 deadline = ATA_TMOUT_BOOT;
589 while (dev1) {
590 u8 nsect, lbal;
591
592 bfin_dev_select(ap, 1);
593 nsect = read_atapi_register(base, ATA_REG_NSECT);
594 lbal = read_atapi_register(base, ATA_REG_LBAL);
595 if ((nsect == 1) && (lbal == 1))
596 break;
597 if (deadline <= 0) {
598 dev1 = 0;
599 break;
600 }
601 msleep(50); /* give drive a breather */
602 deadline -= 50;
603 }
604 if (dev1)
605 bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
606
607 /* is all this really necessary? */
608 bfin_dev_select(ap, 0);
609 if (dev1)
610 bfin_dev_select(ap, 1);
611 if (dev0)
612 bfin_dev_select(ap, 0);
613}
614
615/**
616 * bfin_bus_softreset - PATA device software reset
617 *
618 * Note: Original code is ata_bus_softreset().
619 */
620
621static unsigned int bfin_bus_softreset(struct ata_port *ap,
622 unsigned int devmask)
623{
624 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
625
626 /* software reset. causes dev0 to be selected */
627 write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
628 udelay(20);
629 write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg | ATA_SRST);
630 udelay(20);
631 write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
632
633 /* spec mandates ">= 2ms" before checking status.
634 * We wait 150ms, because that was the magic delay used for
635 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
636 * between when the ATA command register is written, and then
637 * status is checked. Because waiting for "a while" before
638 * checking status is fine, post SRST, we perform this magic
639 * delay here as well.
640 *
641 * Old drivers/ide uses the 2mS rule and then waits for ready
642 */
643 msleep(150);
644
645 /* Before we perform post reset processing we want to see if
646 * the bus shows 0xFF because the odd clown forgets the D7
647 * pulldown resistor.
648 */
649 if (bfin_check_status(ap) == 0xFF)
650 return 0;
651
652 bfin_bus_post_reset(ap, devmask);
653
654 return 0;
655}
656
657/**
658 * bfin_softreset - reset host port via ATA SRST
659 * @ap: port to reset
660 *
661 * Note: Original code is ata_sff_softreset().
662 */
663
664static int bfin_softreset(struct ata_port *ap)
665{
666 unsigned int err_mask;
667
668 ap->dev_mask = 0;
669
670 /* determine if device 0/1 are present.
671 * only one device is supported on one port by now.
672 */
673 if (bfin_devchk(ap, 0))
674 ap->dev_mask |= (1 << 0);
675 else if (bfin_devchk(ap, 1))
676 ap->dev_mask |= (1 << 1);
677 else
678 return -ENODEV;
679
680 /* select device 0 again */
681 bfin_dev_select(ap, 0);
682
683 /* issue bus reset */
684 err_mask = bfin_bus_softreset(ap, ap->dev_mask);
685 if (err_mask) {
686 printf("SRST failed (err_mask=0x%x)\n",
687 err_mask);
688 ap->dev_mask = 0;
689 return -EIO;
690 }
691
692 return 0;
693}
694
695/**
696 * bfin_irq_clear - Clear ATAPI interrupt.
697 * @ap: Port associated with this ATA transaction.
698 *
699 * Note: Original code is ata_sff_irq_clear().
700 */
701
702static void bfin_irq_clear(struct ata_port *ap)
703{
704 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
705
706 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
707 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
708 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
709}
710
711static u8 bfin_wait_for_irq(struct ata_port *ap, unsigned int max)
712{
713 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
714
715 do {
716 if (ATAPI_GET_INT_STATUS(base) & (ATAPI_DEV_INT
717 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
718 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT)) {
719 break;
720 }
721 udelay(1000);
722 max--;
723 } while ((max > 0));
724
725 return max == 0;
726}
727
728/**
729 * bfin_ata_reset_port - initialize BFIN ATAPI port.
730 */
731
732static int bfin_ata_reset_port(struct ata_port *ap)
733{
734 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
735 int count;
736 unsigned short status;
737
738 /* Disable all ATAPI interrupts */
739 ATAPI_SET_INT_MASK(base, 0);
740 SSYNC();
741
742 /* Assert the RESET signal 25us*/
743 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
744 udelay(30);
745
746 /* Negate the RESET signal for 2ms*/
747 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
748 msleep(2);
749
750 /* Wait on Busy flag to clear */
751 count = 10000000;
752 do {
753 status = read_atapi_register(base, ATA_REG_STATUS);
754 } while (--count && (status & ATA_BUSY));
755
756 /* Enable only ATAPI Device interrupt */
757 ATAPI_SET_INT_MASK(base, 1);
758 SSYNC();
759
760 return !count;
761}
762
763/**
764 *
765 * Function: bfin_config_atapi_gpio
766 *
767 * Description: Configures the ATAPI pins for use
768 *
769 */
770static int bfin_config_atapi_gpio(struct ata_port *ap)
771{
772 bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0x4);
773 bfin_write_PORTH_MUX(bfin_read_PORTH_MUX() & ~0x30);
774 bfin_write_PORTH_DIR_SET(0x4);
775
776 bfin_write_PORTJ_FER(0x7f8);
777 bfin_write_PORTJ_MUX(bfin_read_PORTI_MUX() & ~0x3fffc0);
778 bfin_write_PORTJ_DIR_SET(0x5f8);
779 bfin_write_PORTJ_DIR_CLEAR(0x200);
780 bfin_write_PORTJ_INEN(0x200);
781
782 bfin_write_PINT2_ASSIGN(0x0707);
783 bfin_write_PINT2_MASK_SET(0x200);
784 SSYNC();
785
786 return 0;
787}
788
789/**
790 * bfin_atapi_probe - attach a bfin atapi interface
791 * @pdev: platform device
792 *
793 * Register a bfin atapi interface.
794 *
795 *
796 * Platform devices are expected to contain 2 resources per port:
797 *
798 * - I/O Base (IORESOURCE_IO)
799 * - IRQ (IORESOURCE_IRQ)
800 *
801 */
802static int bfin_ata_probe_port(struct ata_port *ap)
803{
804 if (bfin_config_atapi_gpio(ap)) {
805 printf("Requesting Peripherals faild\n");
806 return -EFAULT;
807 }
808
809 if (bfin_ata_reset_port(ap)) {
810 printf("Fail to reset ATAPI device\n");
811 return -EFAULT;
812 }
813
814 if (ap->ata_mode >= XFER_PIO_0 && ap->ata_mode <= XFER_PIO_4)
815 bfin_set_piomode(ap, ap->ata_mode);
816 else {
817 printf("Given ATA data transfer mode is not supported.\n");
818 return -EFAULT;
819 }
820
821 return 0;
822}
823
824#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
825
826static void bfin_ata_identify(struct ata_port *ap, int dev)
827{
828 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
829 u8 status = 0;
830 static u16 iobuf[ATA_SECTOR_WORDS];
831 u64 n_sectors = 0;
832 hd_driveid_t *iop = (hd_driveid_t *)iobuf;
833
834 memset(iobuf, 0, sizeof(iobuf));
835
836 if (!(ap->dev_mask & (1 << dev)))
837 return;
838
839 debug("port=%d dev=%d\n", ap->port_no, dev);
840
841 bfin_dev_select(ap, dev);
842
843 status = 0;
844 /* Device Identify Command */
845 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_ID_ATA);
846 bfin_check_altstatus(ap);
847 udelay(10);
848
849 status = bfin_ata_busy_wait(ap, ATA_BUSY, 1000, 0);
850 if (status & ATA_ERR) {
851 printf("\ndevice not responding\n");
852 ap->dev_mask &= ~(1 << dev);
853 return;
854 }
855
856 read_atapi_data(base, ATA_SECTOR_WORDS, iobuf);
857
858 ata_swap_buf_le16(iobuf, ATA_SECTOR_WORDS);
859
860 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
861 if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
862 printf("ata%u: no dma/lba\n", ap->port_no);
863
864#ifdef DEBUG
865 ata_dump_id(iobuf);
866#endif
867
868 n_sectors = ata_id_n_sectors(iobuf);
869
870 if (n_sectors == 0) {
871 ap->dev_mask &= ~(1 << dev);
872 return;
873 }
874
875 ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].revision,
876 ATA_ID_FW_REV, sizeof(sata_dev_desc[ap->port_no].revision));
877 ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].vendor,
878 ATA_ID_PROD, sizeof(sata_dev_desc[ap->port_no].vendor));
879 ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].product,
880 ATA_ID_SERNO, sizeof(sata_dev_desc[ap->port_no].product));
881
882 if ((iop->config & 0x0080) == 0x0080)
883 sata_dev_desc[ap->port_no].removable = 1;
884 else
885 sata_dev_desc[ap->port_no].removable = 0;
886
887 sata_dev_desc[ap->port_no].lba = (u32) n_sectors;
888 debug("lba=0x%x\n", sata_dev_desc[ap->port_no].lba);
889
890#ifdef CONFIG_LBA48
891 if (iop->command_set_2 & 0x0400)
892 sata_dev_desc[ap->port_no].lba48 = 1;
893 else
894 sata_dev_desc[ap->port_no].lba48 = 0;
895#endif
896
897 /* assuming HD */
898 sata_dev_desc[ap->port_no].type = DEV_TYPE_HARDDISK;
899 sata_dev_desc[ap->port_no].blksz = ATA_SECT_SIZE;
900 sata_dev_desc[ap->port_no].lun = 0; /* just to fill something in... */
901
902 printf("PATA device#%d %s is found on ata port#%d.\n",
903 ap->port_no%PATA_DEV_NUM_PER_PORT,
904 sata_dev_desc[ap->port_no].vendor,
905 ap->port_no/PATA_DEV_NUM_PER_PORT);
906}
907
908static void bfin_ata_set_Feature_cmd(struct ata_port *ap, int dev)
909{
910 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
911 u8 status = 0;
912
913 if (!(ap->dev_mask & (1 << dev)))
914 return;
915
916 bfin_dev_select(ap, dev);
917
918 write_atapi_register(base, ATA_REG_FEATURE, SETFEATURES_XFER);
919 write_atapi_register(base, ATA_REG_NSECT, ap->ata_mode);
920 write_atapi_register(base, ATA_REG_LBAL, 0);
921 write_atapi_register(base, ATA_REG_LBAM, 0);
922 write_atapi_register(base, ATA_REG_LBAH, 0);
923
924 write_atapi_register(base, ATA_REG_DEVICE, ATA_DEVICE_OBS);
925 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_SET_FEATURES);
926
927 udelay(50);
928 msleep(150);
929
930 status = bfin_ata_busy_wait(ap, ATA_BUSY, 5000, 0);
931 if ((status & (ATA_BUSY | ATA_ERR))) {
932 printf("Error : status 0x%02x\n", status);
933 ap->dev_mask &= ~(1 << dev);
934 }
935}
936
937int scan_sata(int dev)
938{
939 /* dev is the index of each ata device in the system. one PATA port
940 * contains 2 devices. one element in scan_done array indicates one
941 * PATA port. device connected to one PATA port is selected by
942 * bfin_dev_select() before access.
943 */
944 struct ata_port *ap = &port[dev];
945 static int scan_done[(CONFIG_SYS_SATA_MAX_DEVICE+1)/PATA_DEV_NUM_PER_PORT];
946
947 if (scan_done[dev/PATA_DEV_NUM_PER_PORT])
948 return 0;
949
950 /* Check for attached device */
951 if (!bfin_ata_probe_port(ap)) {
952 if (bfin_softreset(ap)) {
953 /* soft reset failed, try a hard one */
954 bfin_ata_reset_port(ap);
955 if (bfin_softreset(ap))
956 scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
957 } else {
958 scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
959 }
960 }
961 if (scan_done[dev/PATA_DEV_NUM_PER_PORT]) {
962 /* Probe device and set xfer mode */
963 bfin_ata_identify(ap, dev%PATA_DEV_NUM_PER_PORT);
964 bfin_ata_set_Feature_cmd(ap, dev%PATA_DEV_NUM_PER_PORT);
965 init_part(&sata_dev_desc[dev]);
966 return 0;
967 }
968
969 printf("PATA device#%d is not present on ATA port#%d.\n",
970 ap->port_no%PATA_DEV_NUM_PER_PORT,
971 ap->port_no/PATA_DEV_NUM_PER_PORT);
972
973 return -1;
974}
975
976int init_sata(int dev)
977{
978 struct ata_port *ap = &port[dev];
979 static u8 init_done;
980 int res = 1;
981
982 if (init_done)
983 return res;
984
985 init_done = 1;
986
987 switch (dev/PATA_DEV_NUM_PER_PORT) {
988 case 0:
989 ap->ioaddr.ctl_addr = ATAPI_CONTROL;
990 ap->ata_mode = CONFIG_BFIN_ATA_MODE;
991 break;
992 default:
993 printf("Tried to scan unknown port %d.\n", dev);
994 return res;
995 }
996
997 if (ap->ata_mode < XFER_PIO_0 || ap->ata_mode > XFER_PIO_4) {
998 ap->ata_mode = XFER_PIO_4;
999 printf("DMA mode is not supported. Set to PIO mode 4.\n");
1000 }
1001
1002 ap->port_no = dev;
1003 ap->ctl_reg = 0x8; /*Default value of control reg */
1004
1005 res = 0;
1006 return res;
1007}
1008
1009/* Read up to 255 sectors
1010 *
1011 * Returns sectors read
1012*/
1013static u8 do_one_read(struct ata_port *ap, u64 blknr, u8 blkcnt, u16 *buffer,
1014 uchar lba48)
1015{
1016 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1017 u8 sr = 0;
1018 u8 status;
1019 u16 err = 0;
1020
1021 if (!(bfin_check_status(ap) & ATA_DRDY)) {
1022 printf("Device ata%d not ready\n", ap->port_no);
1023 return 0;
1024 }
1025
1026 /* Set up transfer */
1027#ifdef CONFIG_LBA48
1028 if (lba48) {
1029 /* write high bits */
1030 write_atapi_register(base, ATA_REG_NSECT, 0);
1031 write_atapi_register(base, ATA_REG_LBAL, (blknr >> 24) & 0xFF);
1032 write_atapi_register(base, ATA_REG_LBAM, (blknr >> 32) & 0xFF);
1033 write_atapi_register(base, ATA_REG_LBAH, (blknr >> 40) & 0xFF);
1034 }
1035#endif
1036 write_atapi_register(base, ATA_REG_NSECT, blkcnt);
1037 write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
1038 write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
1039 write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
1040
1041#ifdef CONFIG_LBA48
1042 if (lba48) {
1043 write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
1044 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ_EXT);
1045 } else
1046#endif
1047 {
1048 write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA | ((blknr >> 24) & 0xF));
1049 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ);
1050 }
1051 status = bfin_ata_busy_wait(ap, ATA_BUSY, 500000, 1);
1052
1053 if (status & (ATA_BUSY | ATA_ERR)) {
1054 printf("Device %d not responding status 0x%x.\n", ap->port_no, status);
1055 err = read_atapi_register(base, ATA_REG_ERR);
1056 printf("Error reg = 0x%x\n", err);
1057 return sr;
1058 }
1059
1060 while (blkcnt--) {
1061 if (bfin_wait_for_irq(ap, 500)) {
1062 printf("ata%u irq failed\n", ap->port_no);
1063 return sr;
1064 }
1065
1066 status = bfin_check_status(ap);
1067 if (status & ATA_ERR) {
1068 err = read_atapi_register(base, ATA_REG_ERR);
1069 printf("ata%u error %d\n", ap->port_no, err);
1070 return sr;
1071 }
1072 bfin_irq_clear(ap);
1073
1074 /* Read one sector */
1075 read_atapi_data(base, ATA_SECTOR_WORDS, buffer);
1076 buffer += ATA_SECTOR_WORDS;
1077 sr++;
1078 }
1079
1080 return sr;
1081}
1082
1083ulong sata_read(int dev, ulong block, ulong blkcnt, void *buff)
1084{
1085 struct ata_port *ap = &port[dev];
1086 ulong n = 0, sread;
1087 u16 *buffer = (u16 *) buff;
1088 u8 status = 0;
1089 u64 blknr = (u64) block;
1090 unsigned char lba48 = 0;
1091
1092#ifdef CONFIG_LBA48
1093 if (blknr > 0xfffffff) {
1094 if (!sata_dev_desc[dev].lba48) {
1095 printf("Drive doesn't support 48-bit addressing\n");
1096 return 0;
1097 }
1098 /* more than 28 bits used, use 48bit mode */
1099 lba48 = 1;
1100 }
1101#endif
1102 bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
1103
1104 while (blkcnt > 0) {
1105
1106 if (blkcnt > 255)
1107 sread = 255;
1108 else
1109 sread = blkcnt;
1110
1111 status = do_one_read(ap, blknr, sread, buffer, lba48);
1112 if (status != sread) {
1113 printf("Read failed\n");
1114 return n;
1115 }
1116
1117 blkcnt -= sread;
1118 blknr += sread;
1119 n += sread;
1120 buffer += sread * ATA_SECTOR_WORDS;
1121 }
1122 return n;
1123}
1124
1125ulong sata_write(int dev, ulong block, ulong blkcnt, const void *buff)
1126{
1127 struct ata_port *ap = &port[dev];
1128 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1129 ulong n = 0;
1130 u16 *buffer = (u16 *) buff;
1131 unsigned char status = 0;
1132 u64 blknr = (u64) block;
1133#ifdef CONFIG_LBA48
1134 unsigned char lba48 = 0;
1135
1136 if (blknr > 0xfffffff) {
1137 if (!sata_dev_desc[dev].lba48) {
1138 printf("Drive doesn't support 48-bit addressing\n");
1139 return 0;
1140 }
1141 /* more than 28 bits used, use 48bit mode */
1142 lba48 = 1;
1143 }
1144#endif
1145
1146 bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
1147
1148 while (blkcnt-- > 0) {
1149 status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
1150 if (status & ATA_BUSY) {
1151 printf("ata%u failed to respond\n", ap->port_no);
1152 return n;
1153 }
1154#ifdef CONFIG_LBA48
1155 if (lba48) {
1156 /* write high bits */
1157 write_atapi_register(base, ATA_REG_NSECT, 0);
1158 write_atapi_register(base, ATA_REG_LBAL,
1159 (blknr >> 24) & 0xFF);
1160 write_atapi_register(base, ATA_REG_LBAM,
1161 (blknr >> 32) & 0xFF);
1162 write_atapi_register(base, ATA_REG_LBAH,
1163 (blknr >> 40) & 0xFF);
1164 }
1165#endif
1166 write_atapi_register(base, ATA_REG_NSECT, 1);
1167 write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
1168 write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
1169 write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
1170#ifdef CONFIG_LBA48
1171 if (lba48) {
1172 write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
1173 write_atapi_register(base, ATA_REG_CMD,
1174 ATA_CMD_PIO_WRITE_EXT);
1175 } else
1176#endif
1177 {
1178 write_atapi_register(base, ATA_REG_DEVICE,
1179 ATA_LBA | ((blknr >> 24) & 0xF));
1180 write_atapi_register(base, ATA_REG_CMD,
1181 ATA_CMD_PIO_WRITE);
1182 }
1183
1184 /*may take up to 5 sec */
1185 status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
1186 if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
1187 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
1188 ap->port_no, (ulong) blknr, status);
1189 return n;
1190 }
1191
1192 write_atapi_data(base, ATA_SECTOR_WORDS, buffer);
1193 bfin_check_altstatus(ap);
1194 udelay(1);
1195
1196 ++n;
1197 ++blknr;
1198 buffer += ATA_SECTOR_WORDS;
1199 }
1200 return n;
1201}
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