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[people/ms/u-boot.git] / drivers / block / sata_mv.c
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169789dc
TK		 1/*
2 * Copyright (C) Excito Elektronik i Skåne AB, 2010.
3 * Author: Tor Krill <tor@excito.com>
4 *
5 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10/*
11 * This driver supports the SATA controller of some Mavell SoC's.
12 * Here a (most likely incomplete) list of the supported SoC's:
13 * - Kirkwood
14 * - Armada 370
15 * - Armada XP
16 *
17 * This driver implementation is an alternative to the already available
18 * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
19 * But this driver only supports PIO mode and as this new driver also
20 * supports transfer via DMA, its much faster.
21 *
22 * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
23 * by this driver. As they have an AHCI compatible SATA controller
24 * integrated.
25 */
26
27/*
28 * TODO:
29 * Better error recovery
30 * No support for using PRDs (Thus max 64KB transfers)
31 * No NCQ support
32 * No port multiplier support
33 */
34
35#include <common.h>
36#include <fis.h>
37#include <libata.h>
38#include <malloc.h>
39#include <sata.h>
40#include <asm/errno.h>
41#include <asm/io.h>
42#include <linux/mbus.h>
43
44#if defined(CONFIG_KIRKWOOD)
45#include <asm/arch/kirkwood.h>
46#define SATAHC_BASE KW_SATA_BASE
47#else
48#include <asm/arch/soc.h>
49#define SATAHC_BASE MVEBU_AXP_SATA_BASE
50#endif
51
52#define SATA0_BASE (SATAHC_BASE + 0x2000)
53#define SATA1_BASE (SATAHC_BASE + 0x4000)
54
55/* EDMA registers */
56#define EDMA_CFG 0x000
57#define EDMA_CFG_NCQ (1 << 5)
58#define EDMA_CFG_EQUE (1 << 9)
59#define EDMA_TIMER 0x004
60#define EDMA_IECR 0x008
61#define EDMA_IEMR 0x00c
62#define EDMA_RQBA_HI 0x010
63#define EDMA_RQIPR 0x014
64#define EDMA_RQIPR_IPMASK (0x1f << 5)
65#define EDMA_RQIPR_IPSHIFT 5
66#define EDMA_RQOPR 0x018
67#define EDMA_RQOPR_OPMASK (0x1f << 5)
68#define EDMA_RQOPR_OPSHIFT 5
69#define EDMA_RSBA_HI 0x01c
70#define EDMA_RSIPR 0x020
71#define EDMA_RSIPR_IPMASK (0x1f << 3)
72#define EDMA_RSIPR_IPSHIFT 3
73#define EDMA_RSOPR 0x024
74#define EDMA_RSOPR_OPMASK (0x1f << 3)
75#define EDMA_RSOPR_OPSHIFT 3
76#define EDMA_CMD 0x028
77#define EDMA_CMD_ENEDMA (0x01 << 0)
78#define EDMA_CMD_DISEDMA (0x01 << 1)
79#define EDMA_CMD_ATARST (0x01 << 2)
80#define EDMA_CMD_FREEZE (0x01 << 4)
81#define EDMA_TEST_CTL 0x02c
82#define EDMA_STATUS 0x030
83#define EDMA_IORTO 0x034
84#define EDMA_CDTR 0x040
85#define EDMA_HLTCND 0x060
86#define EDMA_NTSR 0x094
87
88/* Basic DMA registers */
89#define BDMA_CMD 0x224
90#define BDMA_STATUS 0x228
91#define BDMA_DTLB 0x22c
92#define BDMA_DTHB 0x230
93#define BDMA_DRL 0x234
94#define BDMA_DRH 0x238
95
96/* SATA Interface registers */
97#define SIR_ICFG 0x050
98#define SIR_CFG_GEN2EN (0x1 << 7)
99#define SIR_PLL_CFG 0x054
100#define SIR_SSTATUS 0x300
101#define SSTATUS_DET_MASK (0x0f << 0)
102#define SIR_SERROR 0x304
103#define SIR_SCONTROL 0x308
104#define SIR_SCONTROL_DETEN (0x01 << 0)
105#define SIR_LTMODE 0x30c
106#define SIR_LTMODE_NELBE (0x01 << 7)
107#define SIR_PHYMODE3 0x310
108#define SIR_PHYMODE4 0x314
109#define SIR_PHYMODE1 0x32c
110#define SIR_PHYMODE2 0x330
111#define SIR_BIST_CTRL 0x334
112#define SIR_BIST_DW1 0x338
113#define SIR_BIST_DW2 0x33c
114#define SIR_SERR_IRQ_MASK 0x340
115#define SIR_SATA_IFCTRL 0x344
116#define SIR_SATA_TESTCTRL 0x348
117#define SIR_SATA_IFSTATUS 0x34c
118#define SIR_VEND_UNIQ 0x35c
119#define SIR_FIS_CFG 0x360
120#define SIR_FIS_IRQ_CAUSE 0x364
121#define SIR_FIS_IRQ_MASK 0x368
122#define SIR_FIS_DWORD0 0x370
123#define SIR_FIS_DWORD1 0x374
124#define SIR_FIS_DWORD2 0x378
125#define SIR_FIS_DWORD3 0x37c
126#define SIR_FIS_DWORD4 0x380
127#define SIR_FIS_DWORD5 0x384
128#define SIR_FIS_DWORD6 0x388
129#define SIR_PHYM9_GEN2 0x398
130#define SIR_PHYM9_GEN1 0x39c
131#define SIR_PHY_CFG 0x3a0
132#define SIR_PHYCTL 0x3a4
133#define SIR_PHYM10 0x3a8
134#define SIR_PHYM12 0x3b0
135
136/* Shadow registers */
137#define PIO_DATA 0x100
138#define PIO_ERR_FEATURES 0x104
139#define PIO_SECTOR_COUNT 0x108
140#define PIO_LBA_LOW 0x10c
141#define PIO_LBA_MID 0x110
142#define PIO_LBA_HI 0x114
143#define PIO_DEVICE 0x118
144#define PIO_CMD_STATUS 0x11c
145#define PIO_STATUS_ERR (0x01 << 0)
146#define PIO_STATUS_DRQ (0x01 << 3)
147#define PIO_STATUS_DF (0x01 << 5)
148#define PIO_STATUS_DRDY (0x01 << 6)
149#define PIO_STATUS_BSY (0x01 << 7)
150#define PIO_CTRL_ALTSTAT 0x120
151
152/* SATAHC arbiter registers */
153#define SATAHC_CFG 0x000
154#define SATAHC_RQOP 0x004
155#define SATAHC_RQIP 0x008
156#define SATAHC_ICT 0x00c
157#define SATAHC_ITT 0x010
158#define SATAHC_ICR 0x014
159#define SATAHC_ICR_PORT0 (0x01 << 0)
160#define SATAHC_ICR_PORT1 (0x01 << 1)
161#define SATAHC_MIC 0x020
162#define SATAHC_MIM 0x024
163#define SATAHC_LED_CFG 0x02c
164
165#define REQUEST_QUEUE_SIZE 32
166#define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
167
168struct crqb {
169 u32 dtb_low; /* DW0 */
170 u32 dtb_high; /* DW1 */
171 u32 control_flags; /* DW2 */
172 u32 drb_count; /* DW3 */
173 u32 ata_cmd_feat; /* DW4 */
174 u32 ata_addr; /* DW5 */
175 u32 ata_addr_exp; /* DW6 */
176 u32 ata_sect_count; /* DW7 */
177};
178
179#define CRQB_ALIGN 0x400
180
181#define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
182#define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
183#define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
184#define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
185#define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
186#define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
187#define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
188#define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
189
190#define CRQB_CMDFEAT_CMDMASK (0xff << 16)
191#define CRQB_CMDFEAT_CMDSHIFT 16
192#define CRQB_CMDFEAT_FEATMASK (0xff << 16)
193#define CRQB_CMDFEAT_FEATSHIFT 24
194
195#define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
196#define CRQB_ADDR_LBA_LOWSHIFT 0
197#define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
198#define CRQB_ADDR_LBA_MIDSHIFT 8
199#define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
200#define CRQB_ADDR_LBA_HIGHSHIFT 16
201#define CRQB_ADDR_DEVICE_MASK (0xff << 24)
202#define CRQB_ADDR_DEVICE_SHIFT 24
203
204#define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
205#define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
206#define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
207#define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
208#define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
209#define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
210#define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
211#define CRQB_ADDR_FEATURE_EXP_SHIFT 24
212
213#define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
214#define CRQB_SECTCOUNT_COUNT_SHIFT 0
215#define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
216#define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
217
218#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
219#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
220
221struct eprd {
222 u32 phyaddr_low;
223 u32 bytecount_eot;
224 u32 phyaddr_hi;
225 u32 reserved;
226};
227
228#define EPRD_PHYADDR_MASK 0xfffffffe
229#define EPRD_BYTECOUNT_MASK 0x0000ffff
230#define EPRD_EOT (0x01 << 31)
231
232struct crpb {
233 u32 id;
234 u32 flags;
235 u32 timestamp;
236};
237
238#define CRPB_ALIGN 0x100
239
240#define READ_CMD 0
241#define WRITE_CMD 1
242
243/*
244 * Since we don't use PRDs yet max transfer size
245 * is 64KB
246 */
247#define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
248
249/* Keep track if hw is initialized or not */
250static u32 hw_init;
251
252struct mv_priv {
253 char name[12];
254 u32 link;
255 u32 regbase;
256 u32 queue_depth;
257 u16 pio;
258 u16 mwdma;
259 u16 udma;
260
261 void *crqb_alloc;
262 struct crqb *request;
263
264 void *crpb_alloc;
265 struct crpb *response;
266};
267
268static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
269{
270 ulong start;
271
272 start = get_timer(0);
273 do {
274 if ((in_le32(addr) & mask) == val)
275 return 0;
276 } while (get_timer(start) < timeout_msec);
277
278 return -ETIMEDOUT;
279}
280
281/* Cut from sata_mv in linux kernel */
282static int mv_stop_edma_engine(int port)
283{
284 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
285 int i;
286
287 /* Disable eDMA. The disable bit auto clears. */
288 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
289
290 /* Wait for the chip to confirm eDMA is off. */
291 for (i = 10000; i > 0; i--) {
292 u32 reg = in_le32(priv->regbase + EDMA_CMD);
293 if (!(reg & EDMA_CMD_ENEDMA)) {
294 debug("EDMA stop on port %d succesful\n", port);
295 return 0;
296 }
297 udelay(10);
298 }
299 debug("EDMA stop on port %d failed\n", port);
300 return -1;
301}
302
303static int mv_start_edma_engine(int port)
304{
305 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
306 u32 tmp;
307
308 /* Check preconditions */
309 tmp = in_le32(priv->regbase + SIR_SSTATUS);
310 if ((tmp & SSTATUS_DET_MASK) != 0x03) {
311 printf("Device error on port: %d\n", port);
312 return -1;
313 }
314
315 tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
316 if (tmp & (ATA_BUSY | ATA_DRQ)) {
317 printf("Device not ready on port: %d\n", port);
318 return -1;
319 }
320
321 /* Clear interrupt cause */
322 out_le32(priv->regbase + EDMA_IECR, 0x0);
323
324 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
325 tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
326 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
327
328 /* Configure edma operation */
329 tmp = in_le32(priv->regbase + EDMA_CFG);
330 tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
331 tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
332 out_le32(priv->regbase + EDMA_CFG, tmp);
333
334 out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
335
336 /* Configure fis, set all to no-wait for now */
337 out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
338
339 /* Setup request queue */
340 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
341 out_le32(priv->regbase + EDMA_RQIPR, priv->request);
342 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
343
344 /* Setup response queue */
345 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
346 out_le32(priv->regbase + EDMA_RSOPR, priv->response);
347 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
348
349 /* Start edma */
350 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
351
352 return 0;
353}
354
355static int mv_reset_channel(int port)
356{
357 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
358
359 /* Make sure edma is stopped */
360 mv_stop_edma_engine(port);
361
362 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
363 udelay(25); /* allow reset propagation */
364 out_le32(priv->regbase + EDMA_CMD, 0);
365 mdelay(10);
366
367 return 0;
368}
369
370static void mv_reset_port(int port)
371{
372 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
373
374 mv_reset_channel(port);
375
376 out_le32(priv->regbase + EDMA_CMD, 0x0);
377 out_le32(priv->regbase + EDMA_CFG, 0x101f);
378 out_le32(priv->regbase + EDMA_IECR, 0x0);
379 out_le32(priv->regbase + EDMA_IEMR, 0x0);
380 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
381 out_le32(priv->regbase + EDMA_RQIPR, 0x0);
382 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
383 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
384 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
385 out_le32(priv->regbase + EDMA_RSOPR, 0x0);
386 out_le32(priv->regbase + EDMA_IORTO, 0xfa);
387}
388
389static void mv_reset_one_hc(void)
390{
391 out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
392 out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
393 out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
394}
395
396static int probe_port(int port)
397{
398 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
399 int tries, tries2, set15 = 0;
400 u32 tmp;
401
402 debug("Probe port: %d\n", port);
403
404 for (tries = 0; tries < 2; tries++) {
405 /* Clear SError */
406 out_le32(priv->regbase + SIR_SERROR, 0x0);
407
408 /* trigger com-init */
409 tmp = in_le32(priv->regbase + SIR_SCONTROL);
410 tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
411 out_le32(priv->regbase + SIR_SCONTROL, tmp);
412
413 mdelay(1);
414
415 tmp = in_le32(priv->regbase + SIR_SCONTROL);
416 tries2 = 5;
417 do {
418 tmp = (tmp & 0x0f0) | 0x300;
419 out_le32(priv->regbase + SIR_SCONTROL, tmp);
420 mdelay(10);
421 tmp = in_le32(priv->regbase + SIR_SCONTROL);
422 } while ((tmp & 0xf0f) != 0x300 && tries2--);
423
424 mdelay(10);
425
426 for (tries2 = 0; tries2 < 200; tries2++) {
427 tmp = in_le32(priv->regbase + SIR_SSTATUS);
428 if ((tmp & SSTATUS_DET_MASK) == 0x03) {
429 debug("Found device on port\n");
430 return 0;
431 }
432 mdelay(1);
433 }
434
435 if ((tmp & SSTATUS_DET_MASK) == 0) {
436 debug("No device attached on port %d\n", port);
437 return -ENODEV;
438 }
439
440 if (!set15) {
441 /* Try on 1.5Gb/S */
442 debug("Try 1.5Gb link\n");
443 set15 = 1;
444 out_le32(priv->regbase + SIR_SCONTROL, 0x304);
445
446 tmp = in_le32(priv->regbase + SIR_ICFG);
447 tmp &= ~SIR_CFG_GEN2EN;
448 out_le32(priv->regbase + SIR_ICFG, tmp);
449
450 mv_reset_channel(port);
451 }
452 }
453
454 debug("Failed to probe port\n");
455 return -1;
456}
457
458/* Get request queue in pointer */
459static int get_reqip(int port)
460{
461 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
462 u32 tmp;
463
464 tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
465 tmp = tmp >> EDMA_RQIPR_IPSHIFT;
466
467 return tmp;
468}
469
470static void set_reqip(int port, int reqin)
471{
472 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
473 u32 tmp;
474
475 tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
476 tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
477 out_le32(priv->regbase + EDMA_RQIPR, tmp);
478}
479
480/* Get next available slot, ignoring possible overwrite */
481static int get_next_reqip(int port)
482{
483 int slot = get_reqip(port);
484 slot = (slot + 1) % REQUEST_QUEUE_SIZE;
485 return slot;
486}
487
488/* Get response queue in pointer */
489static int get_rspip(int port)
490{
491 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
492 u32 tmp;
493
494 tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
495 tmp = tmp >> EDMA_RSIPR_IPSHIFT;
496
497 return tmp;
498}
499
500/* Get response queue out pointer */
501static int get_rspop(int port)
502{
503 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
504 u32 tmp;
505
506 tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
507 tmp = tmp >> EDMA_RSOPR_OPSHIFT;
508 return tmp;
509}
510
511/* Get next response queue pointer */
512static int get_next_rspop(int port)
513{
514 return (get_rspop(port) + 1) % RESPONSE_QUEUE_SIZE;
515}
516
517/* Set response queue pointer */
518static void set_rspop(int port, int reqin)
519{
520 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
521 u32 tmp;
522
523 tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
524 tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
525
526 out_le32(priv->regbase + EDMA_RSOPR, tmp);
527}
528
529static int wait_dma_completion(int port, int index, u32 timeout_msec)
530{
531 u32 tmp, res;
532
533 tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
534 res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
535 tmp, timeout_msec);
536 if (res)
537 printf("Failed to wait for completion on port %d\n", port);
538
539 return res;
540}
541
542static void process_responses(int port)
543{
544#ifdef DEBUG
545 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
546#endif
547 u32 tmp;
548 u32 outind = get_rspop(port);
549
550 /* Ack interrupts */
551 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
552 if (port == 0)
553 tmp &= ~(BIT(0) | BIT(8));
554 else
555 tmp &= ~(BIT(1) | BIT(9));
556 tmp &= ~(BIT(4));
557 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
558
559 while (get_rspip(port) != outind) {
560#ifdef DEBUG
561 debug("Response index %d flags %08x on port %d\n", outind,
562 priv->response[outind].flags, port);
563#endif
564 outind = get_next_rspop(port);
565 set_rspop(port, outind);
566 }
567}
568
569static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
570 u8 *buffer, u32 len, u32 iswrite)
571{
572 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
573 struct crqb *req;
574 int slot;
575
576 if (len >= 64 * 1024) {
577 printf("We only support <64K transfers for now\n");
578 return -1;
579 }
580
581 /* Initialize request */
582 slot = get_reqip(port);
583 memset(&priv->request[slot], 0, sizeof(struct crqb));
584 req = &priv->request[slot];
585
586 req->dtb_low = (u32)buffer;
587
588 /* Dont use PRDs */
589 req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
590 req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
591 req->control_flags |=
592 ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
593 & CRQB_CNTRLFLAGS_PMPORTMASK);
594
595 req->drb_count = len;
596
597 req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
598 CRQB_CMDFEAT_CMDMASK;
599 req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
600 CRQB_CMDFEAT_FEATMASK;
601
602 req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
603 CRQB_ADDR_LBA_LOWMASK;
604 req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
605 CRQB_ADDR_LBA_MIDMASK;
606 req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
607 CRQB_ADDR_LBA_HIGHMASK;
608 req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
609 CRQB_ADDR_DEVICE_MASK;
610
611 req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
612 CRQB_ADDR_LBA_LOW_EXP_MASK;
613 req->ata_addr_exp |=
614 (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
615 CRQB_ADDR_LBA_MID_EXP_MASK;
616 req->ata_addr_exp |=
617 (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
618 CRQB_ADDR_LBA_HIGH_EXP_MASK;
619 req->ata_addr_exp |=
620 (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
621 CRQB_ADDR_FEATURE_EXP_MASK;
622
623 req->ata_sect_count =
624 (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
625 CRQB_SECTCOUNT_COUNT_MASK;
626 req->ata_sect_count |=
627 (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
628 CRQB_SECTCOUNT_COUNT_EXP_MASK;
629
630 /* Flush data */
631 flush_dcache_range((u32)req, (u32)req + sizeof(*req));
632
633 /* Trigger operation */
634 slot = get_next_reqip(port);
635 set_reqip(port, slot);
636
637 /* Wait for completion */
638 if (wait_dma_completion(port, slot, 10000)) {
639 printf("ATA operation timed out\n");
640 return -1;
641 }
642
643 process_responses(port);
644
645 /* Invalidate data on read */
646 if (buffer && len)
647 invalidate_dcache_range((u32)buffer, (u32)buffer + len);
648
649 return len;
650}
651
652static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt,
653 u8 *buffer, int is_write)
654{
655 struct sata_fis_h2d cfis;
656 u32 res;
657 u64 block;
658
659 block = (u64)start;
660
661 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
662
663 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
664 cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
665
666 cfis.lba_high_exp = (block >> 40) & 0xff;
667 cfis.lba_mid_exp = (block >> 32) & 0xff;
668 cfis.lba_low_exp = (block >> 24) & 0xff;
669 cfis.lba_high = (block >> 16) & 0xff;
670 cfis.lba_mid = (block >> 8) & 0xff;
671 cfis.lba_low = block & 0xff;
672 cfis.device = ATA_LBA;
673 cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
674 cfis.sector_count = blkcnt & 0xff;
675
676 res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
677 is_write);
678
679 return res >= 0 ? blkcnt : res;
680}
681
682static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer,
683 int is_write)
684{
685 struct sata_fis_h2d cfis;
686 lbaint_t block;
687 u32 res;
688
689 block = start;
690
691 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
692
693 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
694 cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
695 cfis.device = ATA_LBA;
696
697 cfis.device |= (block >> 24) & 0xf;
698 cfis.lba_high = (block >> 16) & 0xff;
699 cfis.lba_mid = (block >> 8) & 0xff;
700 cfis.lba_low = block & 0xff;
701 cfis.sector_count = (u8)(blkcnt & 0xff);
702
703 res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
704 is_write);
705
706 return res >= 0 ? blkcnt : res;
707}
708
709static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt,
710 void *buffer, int is_write)
711{
712 lbaint_t start, blks;
713 u8 *addr;
714 int max_blks;
715
716 debug("%s: %ld %ld\n", __func__, blknr, blkcnt);
717
718 start = blknr;
719 blks = blkcnt;
720 addr = (u8 *)buffer;
721
722 max_blks = MV_ATA_MAX_SECTORS;
723 do {
724 if (blks > max_blks) {
725 if (sata_dev_desc[dev].lba48) {
726 mv_sata_rw_cmd_ext(dev, start, max_blks, addr,
727 is_write);
728 } else {
729 mv_sata_rw_cmd(dev, start, max_blks, addr,
730 is_write);
731 }
732 start += max_blks;
733 blks -= max_blks;
734 addr += ATA_SECT_SIZE * max_blks;
735 } else {
736 if (sata_dev_desc[dev].lba48) {
737 mv_sata_rw_cmd_ext(dev, start, blks, addr,
738 is_write);
739 } else {
740 mv_sata_rw_cmd(dev, start, blks, addr,
741 is_write);
742 }
743 start += blks;
744 blks = 0;
745 addr += ATA_SECT_SIZE * blks;
746 }
747 } while (blks != 0);
748
749 return blkcnt;
750}
751
752static int mv_ata_exec_ata_cmd_nondma(int port,
753 struct sata_fis_h2d *cfis, u8 *buffer,
754 u32 len, u32 iswrite)
755{
756 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
757 int i;
758 u16 *tp;
759
760 debug("%s\n", __func__);
761
762 out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
763 out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
764 out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
765 out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
766 out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
767 out_le32(priv->regbase + PIO_DEVICE, cfis->device);
768 out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
769
770 if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
771 ATA_BUSY, 0x0, 10000)) {
772 debug("Failed to wait for completion\n");
773 return -1;
774 }
775
776 if (len > 0) {
777 tp = (u16 *)buffer;
778 for (i = 0; i < len / 2; i++) {
779 if (iswrite)
780 out_le16(priv->regbase + PIO_DATA, *tp++);
781 else
782 *tp++ = in_le16(priv->regbase + PIO_DATA);
783 }
784 }
785
786 return len;
787}
788
789static int mv_sata_identify(int port, u16 *id)
790{
791 struct sata_fis_h2d h2d;
792
793 memset(&h2d, 0, sizeof(struct sata_fis_h2d));
794
795 h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
796 h2d.command = ATA_CMD_ID_ATA;
797
798 /* Give device time to get operational */
799 mdelay(10);
800
801 return mv_ata_exec_ata_cmd_nondma(port, &h2d, (u8 *)id,
802 ATA_ID_WORDS * 2, READ_CMD);
803}
804
805static void mv_sata_xfer_mode(int port, u16 *id)
806{
807 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
808
809 priv->pio = id[ATA_ID_PIO_MODES];
810 priv->mwdma = id[ATA_ID_MWDMA_MODES];
811 priv->udma = id[ATA_ID_UDMA_MODES];
812 debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
813 priv->udma);
814}
815
816static void mv_sata_set_features(int port)
817{
818 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
819 struct sata_fis_h2d cfis;
820 u8 udma_cap;
821
822 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
823
824 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
825 cfis.command = ATA_CMD_SET_FEATURES;
826 cfis.features = SETFEATURES_XFER;
827
828 /* First check the device capablity */
829 udma_cap = (u8) (priv->udma & 0xff);
830
831 if (udma_cap == ATA_UDMA6)
832 cfis.sector_count = XFER_UDMA_6;
833 if (udma_cap == ATA_UDMA5)
834 cfis.sector_count = XFER_UDMA_5;
835 if (udma_cap == ATA_UDMA4)
836 cfis.sector_count = XFER_UDMA_4;
837 if (udma_cap == ATA_UDMA3)
838 cfis.sector_count = XFER_UDMA_3;
839
840 mv_ata_exec_ata_cmd_nondma(port, &cfis, NULL, 0, READ_CMD);
841}
842
843int mv_sata_spin_down(int dev)
844{
845 struct sata_fis_h2d cfis;
846 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
847
848 if (priv->link == 0) {
849 debug("No device on port: %d\n", dev);
850 return 1;
851 }
852
853 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
854
855 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
856 cfis.command = ATA_CMD_STANDBY;
857
858 return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
859}
860
861int mv_sata_spin_up(int dev)
862{
863 struct sata_fis_h2d cfis;
864 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
865
866 if (priv->link == 0) {
867 debug("No device on port: %d\n", dev);
868 return 1;
869 }
870
871 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
872
873 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
874 cfis.command = ATA_CMD_IDLE;
875
876 return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
877}
878
879ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
880{
881 return ata_low_level_rw(dev, blknr, blkcnt, buffer, READ_CMD);
882}
883
884ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
885{
886 return ata_low_level_rw(dev, blknr, blkcnt, (void *)buffer, WRITE_CMD);
887}
888
889/*
890 * Initialize SATA memory windows
891 */
892static void mvsata_ide_conf_mbus_windows(void)
893{
894 const struct mbus_dram_target_info *dram;
895 int i;
896
897 dram = mvebu_mbus_dram_info();
898
899 /* Disable windows, Set Size/Base to 0 */
900 for (i = 0; i < 4; i++) {
901 writel(0, MVSATA_WIN_CONTROL(i));
902 writel(0, MVSATA_WIN_BASE(i));
903 }
904
905 for (i = 0; i < dram->num_cs; i++) {
906 const struct mbus_dram_window *cs = dram->cs + i;
907 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
908 (dram->mbus_dram_target_id << 4) | 1,
909 MVSATA_WIN_CONTROL(i));
910 writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
911 }
912}
913
914int init_sata(int dev)
915{
916 struct mv_priv *priv;
917
918 debug("Initialize sata dev: %d\n", dev);
919
920 if (dev < 0 || dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
921 printf("Invalid sata device %d\n", dev);
922 return -1;
923 }
924
925 priv = (struct mv_priv *)malloc(sizeof(struct mv_priv));
926 if (!priv) {
927 printf("Failed to allocate memory for private sata data\n");
928 return -ENOMEM;
929 }
930
931 memset((void *)priv, 0, sizeof(struct mv_priv));
932
933 /* Allocate and align request buffer */
934 priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
935 CRQB_ALIGN);
936 if (!priv->crqb_alloc) {
937 printf("Unable to allocate memory for request queue\n");
938 return -ENOMEM;
939 }
940 memset(priv->crqb_alloc, 0,
941 sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
942 priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
943 ~(CRQB_ALIGN - 1));
944
945 /* Allocate and align response buffer */
946 priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
947 CRPB_ALIGN);
948 if (!priv->crpb_alloc) {
949 printf("Unable to allocate memory for response queue\n");
950 return -ENOMEM;
951 }
952 memset(priv->crpb_alloc, 0,
953 sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
954 priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
955 ~(CRPB_ALIGN - 1));
956
957 sata_dev_desc[dev].priv = (void *)priv;
958
959 sprintf(priv->name, "SATA%d", dev);
960
961 priv->regbase = dev == 0 ? SATA0_BASE : SATA1_BASE;
962
963 if (!hw_init) {
964 debug("Initialize sata hw\n");
965 hw_init = 1;
966 mv_reset_one_hc();
967 mvsata_ide_conf_mbus_windows();
968 }
969
970 mv_reset_port(dev);
971
972 if (probe_port(dev)) {
973 priv->link = 0;
974 return -ENODEV;
975 }
976 priv->link = 1;
977
978 return 0;
979}
980
981int reset_sata(int dev)
982{
983 return 0;
984}
985
986int scan_sata(int port)
987{
988 unsigned char serial[ATA_ID_SERNO_LEN + 1];
989 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
990 unsigned char product[ATA_ID_PROD_LEN + 1];
991 u64 n_sectors;
992 u16 *id;
993 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
994
995 if (!priv->link)
996 return -ENODEV;
997
998 id = (u16 *)malloc(ATA_ID_WORDS * 2);
999 if (!id) {
1000 printf("Failed to malloc id data\n");
1001 return -ENOMEM;
1002 }
1003
1004 mv_sata_identify(port, id);
1005 ata_swap_buf_le16(id, ATA_ID_WORDS);
1006#ifdef DEBUG
1007 ata_dump_id(id);
1008#endif
1009
1010 /* Serial number */
1011 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
1012 memcpy(sata_dev_desc[port].product, serial, sizeof(serial));
1013
1014 /* Firmware version */
1015 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
1016 memcpy(sata_dev_desc[port].revision, firmware, sizeof(firmware));
1017
1018 /* Product model */
1019 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
1020 memcpy(sata_dev_desc[port].vendor, product, sizeof(product));
1021
1022 /* Total sectors */
1023 n_sectors = ata_id_n_sectors(id);
1024 sata_dev_desc[port].lba = n_sectors;
1025
1026 /* Check if support LBA48 */
1027 if (ata_id_has_lba48(id)) {
1028 sata_dev_desc[port].lba48 = 1;
1029 debug("Device support LBA48\n");
1030 }
1031
1032 /* Get the NCQ queue depth from device */
1033 priv->queue_depth = ata_id_queue_depth(id);
1034
1035 /* Get the xfer mode from device */
1036 mv_sata_xfer_mode(port, id);
1037
1038 /* Set the xfer mode to highest speed */
1039 mv_sata_set_features(port);
1040
1041 /* Start up */
1042 mv_start_edma_engine(port);
1043
1044 return 0;
1045}
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