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5653fc33 | 1 | /* |
bf9e3b38 | 2 | * (C) Copyright 2002-2004 |
5653fc33 WD |
3 | * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com |
4 | * | |
5 | * Copyright (C) 2003 Arabella Software Ltd. | |
6 | * Yuli Barcohen <yuli@arabellasw.com> | |
7 | * Modified to work with AMD flashes | |
8 | * | |
bf9e3b38 WD |
9 | * Copyright (C) 2004 |
10 | * Ed Okerson | |
11 | * Modified to work with little-endian systems. | |
12 | * | |
5653fc33 WD |
13 | * See file CREDITS for list of people who contributed to this |
14 | * project. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of | |
19 | * the License, or (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
29 | * MA 02111-1307 USA | |
30 | * | |
31 | * History | |
32 | * 01/20/2004 - combined variants of original driver. | |
bf9e3b38 WD |
33 | * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) |
34 | * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) | |
35 | * 01/27/2004 - Little endian support Ed Okerson | |
5653fc33 WD |
36 | * |
37 | * Tested Architectures | |
bf9e3b38 | 38 | * Port Width Chip Width # of banks Flash Chip Board |
2d1a537d WD |
39 | * 32 16 1 28F128J3 seranoa/eagle |
40 | * 64 16 1 28F128J3 seranoa/falcon | |
cd37d9e6 | 41 | * |
5653fc33 WD |
42 | */ |
43 | ||
44 | /* The DEBUG define must be before common to enable debugging */ | |
2d1a537d WD |
45 | /* #define DEBUG */ |
46 | ||
5653fc33 WD |
47 | #include <common.h> |
48 | #include <asm/processor.h> | |
4c0d4c3b | 49 | #include <asm/byteorder.h> |
028ab6b5 | 50 | #include <linux/byteorder/swab.h> |
bf9e3b38 | 51 | #ifdef CFG_FLASH_CFI_DRIVER |
028ab6b5 | 52 | |
5653fc33 WD |
53 | /* |
54 | * This file implements a Common Flash Interface (CFI) driver for U-Boot. | |
55 | * The width of the port and the width of the chips are determined at initialization. | |
56 | * These widths are used to calculate the address for access CFI data structures. | |
57 | * It has been tested on an Intel Strataflash implementation and AMD 29F016D. | |
58 | * | |
59 | * References | |
60 | * JEDEC Standard JESD68 - Common Flash Interface (CFI) | |
61 | * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes | |
62 | * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets | |
63 | * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet | |
64 | * | |
65 | * TODO | |
66 | * | |
67 | * Use Primary Extended Query table (PRI) and Alternate Algorithm Query | |
68 | * Table (ALT) to determine if protection is available | |
69 | * | |
70 | * Add support for other command sets Use the PRI and ALT to determine command set | |
71 | * Verify erase and program timeouts. | |
72 | */ | |
73 | ||
bf9e3b38 WD |
74 | #ifndef CFG_FLASH_BANKS_LIST |
75 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | |
76 | #endif | |
77 | ||
5653fc33 WD |
78 | #define FLASH_CMD_CFI 0x98 |
79 | #define FLASH_CMD_READ_ID 0x90 | |
80 | #define FLASH_CMD_RESET 0xff | |
81 | #define FLASH_CMD_BLOCK_ERASE 0x20 | |
82 | #define FLASH_CMD_ERASE_CONFIRM 0xD0 | |
83 | #define FLASH_CMD_WRITE 0x40 | |
84 | #define FLASH_CMD_PROTECT 0x60 | |
85 | #define FLASH_CMD_PROTECT_SET 0x01 | |
86 | #define FLASH_CMD_PROTECT_CLEAR 0xD0 | |
87 | #define FLASH_CMD_CLEAR_STATUS 0x50 | |
bf9e3b38 WD |
88 | #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 |
89 | #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 | |
5653fc33 WD |
90 | |
91 | #define FLASH_STATUS_DONE 0x80 | |
92 | #define FLASH_STATUS_ESS 0x40 | |
93 | #define FLASH_STATUS_ECLBS 0x20 | |
94 | #define FLASH_STATUS_PSLBS 0x10 | |
95 | #define FLASH_STATUS_VPENS 0x08 | |
96 | #define FLASH_STATUS_PSS 0x04 | |
97 | #define FLASH_STATUS_DPS 0x02 | |
98 | #define FLASH_STATUS_R 0x01 | |
99 | #define FLASH_STATUS_PROTECT 0x01 | |
100 | ||
101 | #define AMD_CMD_RESET 0xF0 | |
102 | #define AMD_CMD_WRITE 0xA0 | |
103 | #define AMD_CMD_ERASE_START 0x80 | |
104 | #define AMD_CMD_ERASE_SECTOR 0x30 | |
855a496f WD |
105 | #define AMD_CMD_UNLOCK_START 0xAA |
106 | #define AMD_CMD_UNLOCK_ACK 0x55 | |
5653fc33 WD |
107 | |
108 | #define AMD_STATUS_TOGGLE 0x40 | |
109 | #define AMD_STATUS_ERROR 0x20 | |
855a496f WD |
110 | #define AMD_ADDR_ERASE_START 0x555 |
111 | #define AMD_ADDR_START 0x555 | |
112 | #define AMD_ADDR_ACK 0x2AA | |
5653fc33 WD |
113 | |
114 | #define FLASH_OFFSET_CFI 0x55 | |
115 | #define FLASH_OFFSET_CFI_RESP 0x10 | |
bf9e3b38 | 116 | #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 |
5653fc33 | 117 | #define FLASH_OFFSET_WTOUT 0x1F |
bf9e3b38 | 118 | #define FLASH_OFFSET_WBTOUT 0x20 |
5653fc33 | 119 | #define FLASH_OFFSET_ETOUT 0x21 |
bf9e3b38 | 120 | #define FLASH_OFFSET_CETOUT 0x22 |
5653fc33 | 121 | #define FLASH_OFFSET_WMAX_TOUT 0x23 |
bf9e3b38 | 122 | #define FLASH_OFFSET_WBMAX_TOUT 0x24 |
5653fc33 | 123 | #define FLASH_OFFSET_EMAX_TOUT 0x25 |
bf9e3b38 | 124 | #define FLASH_OFFSET_CEMAX_TOUT 0x26 |
5653fc33 | 125 | #define FLASH_OFFSET_SIZE 0x27 |
bf9e3b38 WD |
126 | #define FLASH_OFFSET_INTERFACE 0x28 |
127 | #define FLASH_OFFSET_BUFFER_SIZE 0x2A | |
5653fc33 WD |
128 | #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C |
129 | #define FLASH_OFFSET_ERASE_REGIONS 0x2D | |
130 | #define FLASH_OFFSET_PROTECT 0x02 | |
bf9e3b38 WD |
131 | #define FLASH_OFFSET_USER_PROTECTION 0x85 |
132 | #define FLASH_OFFSET_INTEL_PROTECTION 0x81 | |
5653fc33 WD |
133 | |
134 | ||
135 | #define FLASH_MAN_CFI 0x01000000 | |
136 | ||
bf9e3b38 | 137 | #define CFI_CMDSET_NONE 0 |
5653fc33 | 138 | #define CFI_CMDSET_INTEL_EXTENDED 1 |
bf9e3b38 | 139 | #define CFI_CMDSET_AMD_STANDARD 2 |
5653fc33 | 140 | #define CFI_CMDSET_INTEL_STANDARD 3 |
bf9e3b38 | 141 | #define CFI_CMDSET_AMD_EXTENDED 4 |
5653fc33 WD |
142 | #define CFI_CMDSET_MITSU_STANDARD 256 |
143 | #define CFI_CMDSET_MITSU_EXTENDED 257 | |
bf9e3b38 | 144 | #define CFI_CMDSET_SST 258 |
5653fc33 WD |
145 | |
146 | ||
147 | typedef union { | |
148 | unsigned char c; | |
149 | unsigned short w; | |
150 | unsigned long l; | |
151 | unsigned long long ll; | |
152 | } cfiword_t; | |
153 | ||
154 | typedef union { | |
bf9e3b38 | 155 | volatile unsigned char *cp; |
5653fc33 | 156 | volatile unsigned short *wp; |
bf9e3b38 | 157 | volatile unsigned long *lp; |
5653fc33 WD |
158 | volatile unsigned long long *llp; |
159 | } cfiptr_t; | |
160 | ||
161 | #define NUM_ERASE_REGIONS 4 | |
162 | ||
163 | static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; | |
164 | ||
bf9e3b38 | 165 | flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
5653fc33 WD |
166 | |
167 | /*----------------------------------------------------------------------- | |
168 | * Functions | |
169 | */ | |
170 | ||
171 | typedef unsigned long flash_sect_t; | |
172 | ||
bf9e3b38 WD |
173 | static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); |
174 | static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); | |
028ab6b5 | 175 | static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); |
bf9e3b38 | 176 | static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); |
028ab6b5 WD |
177 | static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); |
178 | static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); | |
179 | static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); | |
bf9e3b38 | 180 | static int flash_detect_cfi (flash_info_t * info); |
5653fc33 | 181 | static ulong flash_get_size (ulong base, int banknum); |
028ab6b5 | 182 | static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); |
bf9e3b38 WD |
183 | static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, |
184 | ulong tout, char *prompt); | |
5653fc33 | 185 | #ifdef CFG_FLASH_USE_BUFFER_WRITE |
028ab6b5 | 186 | static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len); |
5653fc33 WD |
187 | #endif |
188 | ||
bf9e3b38 WD |
189 | /*----------------------------------------------------------------------- |
190 | * create an address based on the offset and the port width | |
191 | */ | |
028ab6b5 | 192 | inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset) |
bf9e3b38 WD |
193 | { |
194 | return ((uchar *) (info->start[sect] + (offset * info->portwidth))); | |
195 | } | |
196 | ||
5653fc33 | 197 | #ifdef DEBUG |
bf9e3b38 WD |
198 | /*----------------------------------------------------------------------- |
199 | * Debug support | |
200 | */ | |
201 | void print_longlong (char *str, unsigned long long data) | |
5653fc33 WD |
202 | { |
203 | int i; | |
204 | char *cp; | |
bf9e3b38 WD |
205 | |
206 | cp = (unsigned char *) &data; | |
207 | for (i = 0; i < 8; i++) | |
208 | sprintf (&str[i * 2], "%2.2x", *cp++); | |
209 | } | |
210 | static void flash_printqry (flash_info_t * info, flash_sect_t sect) | |
211 | { | |
212 | cfiptr_t cptr; | |
213 | int x, y; | |
214 | ||
215 | for (x = 0; x < 0x40; x += 16 / info->portwidth) { | |
216 | cptr.cp = | |
217 | flash_make_addr (info, sect, | |
218 | x + FLASH_OFFSET_CFI_RESP); | |
219 | debug ("%p : ", cptr.cp); | |
220 | for (y = 0; y < 16; y++) { | |
221 | debug ("%2.2x ", cptr.cp[y]); | |
222 | } | |
223 | debug (" "); | |
224 | for (y = 0; y < 16; y++) { | |
225 | if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) { | |
226 | debug ("%c", cptr.cp[y]); | |
227 | } else { | |
228 | debug ("."); | |
229 | } | |
230 | } | |
231 | debug ("\n"); | |
232 | } | |
5653fc33 WD |
233 | } |
234 | #endif | |
235 | ||
236 | ||
5653fc33 WD |
237 | /*----------------------------------------------------------------------- |
238 | * read a character at a port width address | |
239 | */ | |
bf9e3b38 | 240 | inline uchar flash_read_uchar (flash_info_t * info, uint offset) |
5653fc33 WD |
241 | { |
242 | uchar *cp; | |
bf9e3b38 WD |
243 | |
244 | cp = flash_make_addr (info, 0, offset); | |
245 | #if defined(__LITTLE_ENDIAN) | |
246 | return (cp[0]); | |
247 | #else | |
5653fc33 | 248 | return (cp[info->portwidth - 1]); |
bf9e3b38 | 249 | #endif |
5653fc33 WD |
250 | } |
251 | ||
252 | /*----------------------------------------------------------------------- | |
253 | * read a short word by swapping for ppc format. | |
254 | */ | |
bf9e3b38 | 255 | ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) |
5653fc33 | 256 | { |
bf9e3b38 WD |
257 | uchar *addr; |
258 | ushort retval; | |
5653fc33 | 259 | |
bf9e3b38 WD |
260 | #ifdef DEBUG |
261 | int x; | |
262 | #endif | |
263 | addr = flash_make_addr (info, sect, offset); | |
5653fc33 | 264 | |
bf9e3b38 WD |
265 | #ifdef DEBUG |
266 | debug ("ushort addr is at %p info->portwidth = %d\n", addr, | |
267 | info->portwidth); | |
268 | for (x = 0; x < 2 * info->portwidth; x++) { | |
269 | debug ("addr[%x] = 0x%x\n", x, addr[x]); | |
270 | } | |
271 | #endif | |
272 | #if defined(__LITTLE_ENDIAN) | |
273 | retval = ((addr[(info->portwidth)] << 8) | addr[0]); | |
274 | #else | |
275 | retval = ((addr[(2 * info->portwidth) - 1] << 8) | | |
276 | addr[info->portwidth - 1]); | |
277 | #endif | |
278 | ||
279 | debug ("retval = 0x%x\n", retval); | |
280 | return retval; | |
5653fc33 WD |
281 | } |
282 | ||
283 | /*----------------------------------------------------------------------- | |
284 | * read a long word by picking the least significant byte of each maiximum | |
285 | * port size word. Swap for ppc format. | |
286 | */ | |
bf9e3b38 | 287 | ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) |
5653fc33 | 288 | { |
bf9e3b38 WD |
289 | uchar *addr; |
290 | ulong retval; | |
291 | ||
292 | #ifdef DEBUG | |
293 | int x; | |
294 | #endif | |
295 | addr = flash_make_addr (info, sect, offset); | |
5653fc33 | 296 | |
bf9e3b38 WD |
297 | #ifdef DEBUG |
298 | debug ("long addr is at %p info->portwidth = %d\n", addr, | |
299 | info->portwidth); | |
300 | for (x = 0; x < 4 * info->portwidth; x++) { | |
301 | debug ("addr[%x] = 0x%x\n", x, addr[x]); | |
302 | } | |
303 | #endif | |
304 | #if defined(__LITTLE_ENDIAN) | |
305 | retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) | | |
028ab6b5 | 306 | (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8); |
bf9e3b38 WD |
307 | #else |
308 | retval = (addr[(2 * info->portwidth) - 1] << 24) | | |
309 | (addr[(info->portwidth) - 1] << 16) | | |
310 | (addr[(4 * info->portwidth) - 1] << 8) | | |
311 | addr[(3 * info->portwidth) - 1]; | |
312 | #endif | |
313 | return retval; | |
5653fc33 WD |
314 | } |
315 | ||
316 | /*----------------------------------------------------------------------- | |
317 | */ | |
318 | unsigned long flash_init (void) | |
319 | { | |
320 | unsigned long size = 0; | |
321 | int i; | |
322 | ||
323 | /* Init: no FLASHes known */ | |
bf9e3b38 | 324 | for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { |
5653fc33 | 325 | flash_info[i].flash_id = FLASH_UNKNOWN; |
bf9e3b38 | 326 | size += flash_info[i].size = flash_get_size (bank_base[i], i); |
5653fc33 | 327 | if (flash_info[i].flash_id == FLASH_UNKNOWN) { |
028ab6b5 WD |
328 | printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", |
329 | i, flash_info[i].size, flash_info[i].size << 20); | |
5653fc33 WD |
330 | } |
331 | } | |
332 | ||
333 | /* Monitor protection ON by default */ | |
334 | #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) | |
bf9e3b38 WD |
335 | flash_protect (FLAG_PROTECT_SET, |
336 | CFG_MONITOR_BASE, | |
337 | CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, | |
338 | &flash_info[0]); | |
5653fc33 WD |
339 | #endif |
340 | ||
656658dd WD |
341 | /* Environment protection ON by default */ |
342 | #ifdef CFG_ENV_IS_IN_FLASH | |
343 | flash_protect (FLAG_PROTECT_SET, | |
344 | CFG_ENV_ADDR, | |
345 | CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, | |
346 | &flash_info[0]); | |
347 | #endif | |
348 | ||
349 | /* Redundant environment protection ON by default */ | |
350 | #ifdef CFG_ENV_ADDR_REDUND | |
351 | flash_protect (FLAG_PROTECT_SET, | |
352 | CFG_ENV_ADDR_REDUND, | |
353 | CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, | |
354 | &flash_info[0]); | |
355 | #endif | |
5653fc33 WD |
356 | return (size); |
357 | } | |
358 | ||
359 | /*----------------------------------------------------------------------- | |
360 | */ | |
bf9e3b38 | 361 | int flash_erase (flash_info_t * info, int s_first, int s_last) |
5653fc33 WD |
362 | { |
363 | int rcode = 0; | |
364 | int prot; | |
365 | flash_sect_t sect; | |
366 | ||
bf9e3b38 | 367 | if (info->flash_id != FLASH_MAN_CFI) { |
4b9206ed | 368 | puts ("Can't erase unknown flash type - aborted\n"); |
5653fc33 WD |
369 | return 1; |
370 | } | |
371 | if ((s_first < 0) || (s_first > s_last)) { | |
4b9206ed | 372 | puts ("- no sectors to erase\n"); |
5653fc33 WD |
373 | return 1; |
374 | } | |
375 | ||
376 | prot = 0; | |
bf9e3b38 | 377 | for (sect = s_first; sect <= s_last; ++sect) { |
5653fc33 WD |
378 | if (info->protect[sect]) { |
379 | prot++; | |
380 | } | |
381 | } | |
382 | if (prot) { | |
bf9e3b38 | 383 | printf ("- Warning: %d protected sectors will not be erased!\n", prot); |
5653fc33 | 384 | } else { |
4b9206ed | 385 | putc ('\n'); |
5653fc33 WD |
386 | } |
387 | ||
388 | ||
bf9e3b38 | 389 | for (sect = s_first; sect <= s_last; sect++) { |
5653fc33 | 390 | if (info->protect[sect] == 0) { /* not protected */ |
bf9e3b38 | 391 | switch (info->vendor) { |
5653fc33 WD |
392 | case CFI_CMDSET_INTEL_STANDARD: |
393 | case CFI_CMDSET_INTEL_EXTENDED: | |
028ab6b5 WD |
394 | flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS); |
395 | flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE); | |
396 | flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM); | |
5653fc33 WD |
397 | break; |
398 | case CFI_CMDSET_AMD_STANDARD: | |
399 | case CFI_CMDSET_AMD_EXTENDED: | |
bf9e3b38 | 400 | flash_unlock_seq (info, sect); |
855a496f WD |
401 | flash_write_cmd (info, sect, AMD_ADDR_ERASE_START, |
402 | AMD_CMD_ERASE_START); | |
bf9e3b38 | 403 | flash_unlock_seq (info, sect); |
028ab6b5 | 404 | flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR); |
5653fc33 WD |
405 | break; |
406 | default: | |
bf9e3b38 WD |
407 | debug ("Unkown flash vendor %d\n", |
408 | info->vendor); | |
5653fc33 WD |
409 | break; |
410 | } | |
411 | ||
bf9e3b38 WD |
412 | if (flash_full_status_check |
413 | (info, sect, info->erase_blk_tout, "erase")) { | |
5653fc33 WD |
414 | rcode = 1; |
415 | } else | |
4b9206ed | 416 | putc ('.'); |
5653fc33 WD |
417 | } |
418 | } | |
4b9206ed | 419 | puts (" done\n"); |
5653fc33 WD |
420 | return rcode; |
421 | } | |
422 | ||
423 | /*----------------------------------------------------------------------- | |
424 | */ | |
bf9e3b38 | 425 | void flash_print_info (flash_info_t * info) |
5653fc33 WD |
426 | { |
427 | int i; | |
428 | ||
429 | if (info->flash_id != FLASH_MAN_CFI) { | |
4b9206ed | 430 | puts ("missing or unknown FLASH type\n"); |
5653fc33 WD |
431 | return; |
432 | } | |
433 | ||
bf9e3b38 WD |
434 | printf ("CFI conformant FLASH (%d x %d)", |
435 | (info->portwidth << 3), (info->chipwidth << 3)); | |
5653fc33 WD |
436 | printf (" Size: %ld MB in %d Sectors\n", |
437 | info->size >> 20, info->sector_count); | |
028ab6b5 WD |
438 | printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", |
439 | info->erase_blk_tout, | |
440 | info->write_tout, | |
441 | info->buffer_write_tout, | |
442 | info->buffer_size); | |
5653fc33 | 443 | |
4b9206ed | 444 | puts (" Sector Start Addresses:"); |
bf9e3b38 | 445 | for (i = 0; i < info->sector_count; ++i) { |
5653fc33 WD |
446 | #ifdef CFG_FLASH_EMPTY_INFO |
447 | int k; | |
448 | int size; | |
449 | int erased; | |
450 | volatile unsigned long *flash; | |
451 | ||
452 | /* | |
453 | * Check if whole sector is erased | |
454 | */ | |
bf9e3b38 WD |
455 | if (i != (info->sector_count - 1)) |
456 | size = info->start[i + 1] - info->start[i]; | |
5653fc33 | 457 | else |
bf9e3b38 | 458 | size = info->start[0] + info->size - info->start[i]; |
5653fc33 | 459 | erased = 1; |
bf9e3b38 WD |
460 | flash = (volatile unsigned long *) info->start[i]; |
461 | size = size >> 2; /* divide by 4 for longword access */ | |
462 | for (k = 0; k < size; k++) { | |
463 | if (*flash++ != 0xffffffff) { | |
464 | erased = 0; | |
465 | break; | |
466 | } | |
467 | } | |
5653fc33 WD |
468 | |
469 | if ((i % 5) == 0) | |
470 | printf ("\n"); | |
471 | /* print empty and read-only info */ | |
472 | printf (" %08lX%s%s", | |
473 | info->start[i], | |
474 | erased ? " E" : " ", | |
475 | info->protect[i] ? "RO " : " "); | |
476 | #else | |
477 | if ((i % 5) == 0) | |
478 | printf ("\n "); | |
479 | printf (" %08lX%s", | |
30d56fae | 480 | info->start[i], info->protect[i] ? " (RO) " : " "); |
5653fc33 WD |
481 | #endif |
482 | } | |
4b9206ed | 483 | putc ('\n'); |
5653fc33 WD |
484 | return; |
485 | } | |
486 | ||
487 | /*----------------------------------------------------------------------- | |
488 | * Copy memory to flash, returns: | |
489 | * 0 - OK | |
490 | * 1 - write timeout | |
491 | * 2 - Flash not erased | |
492 | */ | |
bf9e3b38 | 493 | int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
5653fc33 WD |
494 | { |
495 | ulong wp; | |
496 | ulong cp; | |
497 | int aln; | |
498 | cfiword_t cword; | |
499 | int i, rc; | |
500 | ||
bf9e3b38 WD |
501 | #ifdef CFG_FLASH_USE_BUFFER_WRITE |
502 | int buffered_size; | |
503 | #endif | |
bf9e3b38 | 504 | /* get lower aligned address */ |
5653fc33 WD |
505 | /* get lower aligned address */ |
506 | wp = (addr & ~(info->portwidth - 1)); | |
507 | ||
508 | /* handle unaligned start */ | |
bf9e3b38 | 509 | if ((aln = addr - wp) != 0) { |
5653fc33 WD |
510 | cword.l = 0; |
511 | cp = wp; | |
bf9e3b38 WD |
512 | for (i = 0; i < aln; ++i, ++cp) |
513 | flash_add_byte (info, &cword, (*(uchar *) cp)); | |
5653fc33 | 514 | |
bf9e3b38 WD |
515 | for (; (i < info->portwidth) && (cnt > 0); i++) { |
516 | flash_add_byte (info, &cword, *src++); | |
5653fc33 WD |
517 | cnt--; |
518 | cp++; | |
519 | } | |
bf9e3b38 WD |
520 | for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) |
521 | flash_add_byte (info, &cword, (*(uchar *) cp)); | |
522 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
5653fc33 WD |
523 | return rc; |
524 | wp = cp; | |
525 | } | |
526 | ||
bf9e3b38 | 527 | /* handle the aligned part */ |
5653fc33 | 528 | #ifdef CFG_FLASH_USE_BUFFER_WRITE |
bf9e3b38 WD |
529 | buffered_size = (info->portwidth / info->chipwidth); |
530 | buffered_size *= info->buffer_size; | |
531 | while (cnt >= info->portwidth) { | |
532 | i = buffered_size > cnt ? cnt : buffered_size; | |
533 | if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) | |
5653fc33 | 534 | return rc; |
cce625e5 | 535 | i -= (i % info->portwidth); |
5653fc33 WD |
536 | wp += i; |
537 | src += i; | |
bf9e3b38 | 538 | cnt -= i; |
5653fc33 WD |
539 | } |
540 | #else | |
bf9e3b38 | 541 | while (cnt >= info->portwidth) { |
5653fc33 | 542 | cword.l = 0; |
bf9e3b38 WD |
543 | for (i = 0; i < info->portwidth; i++) { |
544 | flash_add_byte (info, &cword, *src++); | |
5653fc33 | 545 | } |
bf9e3b38 | 546 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) |
5653fc33 WD |
547 | return rc; |
548 | wp += info->portwidth; | |
549 | cnt -= info->portwidth; | |
550 | } | |
551 | #endif /* CFG_FLASH_USE_BUFFER_WRITE */ | |
552 | if (cnt == 0) { | |
553 | return (0); | |
554 | } | |
555 | ||
556 | /* | |
557 | * handle unaligned tail bytes | |
558 | */ | |
559 | cword.l = 0; | |
bf9e3b38 WD |
560 | for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { |
561 | flash_add_byte (info, &cword, *src++); | |
5653fc33 WD |
562 | --cnt; |
563 | } | |
bf9e3b38 WD |
564 | for (; i < info->portwidth; ++i, ++cp) { |
565 | flash_add_byte (info, &cword, (*(uchar *) cp)); | |
5653fc33 WD |
566 | } |
567 | ||
bf9e3b38 | 568 | return flash_write_cfiword (info, wp, cword); |
5653fc33 WD |
569 | } |
570 | ||
571 | /*----------------------------------------------------------------------- | |
572 | */ | |
573 | #ifdef CFG_FLASH_PROTECTION | |
574 | ||
bf9e3b38 | 575 | int flash_real_protect (flash_info_t * info, long sector, int prot) |
5653fc33 WD |
576 | { |
577 | int retcode = 0; | |
578 | ||
bf9e3b38 WD |
579 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
580 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); | |
581 | if (prot) | |
582 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); | |
5653fc33 | 583 | else |
bf9e3b38 | 584 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); |
5653fc33 | 585 | |
bf9e3b38 WD |
586 | if ((retcode = |
587 | flash_full_status_check (info, sector, info->erase_blk_tout, | |
588 | prot ? "protect" : "unprotect")) == 0) { | |
5653fc33 WD |
589 | |
590 | info->protect[sector] = prot; | |
591 | /* Intel's unprotect unprotects all locking */ | |
bf9e3b38 | 592 | if (prot == 0) { |
5653fc33 | 593 | flash_sect_t i; |
bf9e3b38 WD |
594 | |
595 | for (i = 0; i < info->sector_count; i++) { | |
596 | if (info->protect[i]) | |
597 | flash_real_protect (info, i, 1); | |
5653fc33 WD |
598 | } |
599 | } | |
600 | } | |
5653fc33 | 601 | return retcode; |
bf9e3b38 WD |
602 | } |
603 | ||
5653fc33 WD |
604 | /*----------------------------------------------------------------------- |
605 | * flash_read_user_serial - read the OneTimeProgramming cells | |
606 | */ | |
bf9e3b38 WD |
607 | void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, |
608 | int len) | |
5653fc33 | 609 | { |
bf9e3b38 WD |
610 | uchar *src; |
611 | uchar *dst; | |
5653fc33 WD |
612 | |
613 | dst = buffer; | |
bf9e3b38 WD |
614 | src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION); |
615 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); | |
616 | memcpy (dst, src + offset, len); | |
617 | flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); | |
5653fc33 | 618 | } |
bf9e3b38 | 619 | |
5653fc33 WD |
620 | /* |
621 | * flash_read_factory_serial - read the device Id from the protection area | |
622 | */ | |
bf9e3b38 WD |
623 | void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, |
624 | int len) | |
5653fc33 | 625 | { |
bf9e3b38 | 626 | uchar *src; |
cd37d9e6 | 627 | |
bf9e3b38 WD |
628 | src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION); |
629 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); | |
630 | memcpy (buffer, src + offset, len); | |
631 | flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); | |
5653fc33 WD |
632 | } |
633 | ||
634 | #endif /* CFG_FLASH_PROTECTION */ | |
635 | ||
bf9e3b38 WD |
636 | /* |
637 | * flash_is_busy - check to see if the flash is busy | |
638 | * This routine checks the status of the chip and returns true if the chip is busy | |
639 | */ | |
640 | static int flash_is_busy (flash_info_t * info, flash_sect_t sect) | |
5653fc33 WD |
641 | { |
642 | int retval; | |
bf9e3b38 WD |
643 | |
644 | switch (info->vendor) { | |
5653fc33 WD |
645 | case CFI_CMDSET_INTEL_STANDARD: |
646 | case CFI_CMDSET_INTEL_EXTENDED: | |
bf9e3b38 | 647 | retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); |
5653fc33 WD |
648 | break; |
649 | case CFI_CMDSET_AMD_STANDARD: | |
650 | case CFI_CMDSET_AMD_EXTENDED: | |
bf9e3b38 | 651 | retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); |
5653fc33 WD |
652 | break; |
653 | default: | |
654 | retval = 0; | |
655 | } | |
bf9e3b38 | 656 | debug ("flash_is_busy: %d\n", retval); |
5653fc33 WD |
657 | return retval; |
658 | } | |
bf9e3b38 | 659 | |
5653fc33 WD |
660 | /*----------------------------------------------------------------------- |
661 | * wait for XSR.7 to be set. Time out with an error if it does not. | |
662 | * This routine does not set the flash to read-array mode. | |
663 | */ | |
bf9e3b38 WD |
664 | static int flash_status_check (flash_info_t * info, flash_sect_t sector, |
665 | ulong tout, char *prompt) | |
5653fc33 WD |
666 | { |
667 | ulong start; | |
668 | ||
669 | /* Wait for command completion */ | |
670 | start = get_timer (0); | |
bf9e3b38 WD |
671 | while (flash_is_busy (info, sector)) { |
672 | if (get_timer (start) > info->erase_blk_tout * CFG_HZ) { | |
673 | printf ("Flash %s timeout at address %lx data %lx\n", | |
674 | prompt, info->start[sector], | |
675 | flash_read_long (info, sector, 0)); | |
676 | flash_write_cmd (info, sector, 0, info->cmd_reset); | |
5653fc33 WD |
677 | return ERR_TIMOUT; |
678 | } | |
679 | } | |
680 | return ERR_OK; | |
681 | } | |
bf9e3b38 | 682 | |
5653fc33 WD |
683 | /*----------------------------------------------------------------------- |
684 | * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. | |
685 | * This routine sets the flash to read-array mode. | |
686 | */ | |
bf9e3b38 WD |
687 | static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, |
688 | ulong tout, char *prompt) | |
5653fc33 WD |
689 | { |
690 | int retcode; | |
bf9e3b38 WD |
691 | |
692 | retcode = flash_status_check (info, sector, tout, prompt); | |
693 | switch (info->vendor) { | |
5653fc33 WD |
694 | case CFI_CMDSET_INTEL_EXTENDED: |
695 | case CFI_CMDSET_INTEL_STANDARD: | |
bf9e3b38 WD |
696 | if ((retcode != ERR_OK) |
697 | && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { | |
5653fc33 | 698 | retcode = ERR_INVAL; |
bf9e3b38 WD |
699 | printf ("Flash %s error at address %lx\n", prompt, |
700 | info->start[sector]); | |
028ab6b5 | 701 | if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { |
4b9206ed | 702 | puts ("Command Sequence Error.\n"); |
028ab6b5 | 703 | } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { |
4b9206ed | 704 | puts ("Block Erase Error.\n"); |
5653fc33 | 705 | retcode = ERR_NOT_ERASED; |
028ab6b5 | 706 | } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { |
4b9206ed | 707 | puts ("Locking Error\n"); |
5653fc33 | 708 | } |
bf9e3b38 | 709 | if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { |
4b9206ed | 710 | puts ("Block locked.\n"); |
bf9e3b38 WD |
711 | retcode = ERR_PROTECTED; |
712 | } | |
713 | if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) | |
4b9206ed | 714 | puts ("Vpp Low Error.\n"); |
5653fc33 | 715 | } |
bf9e3b38 | 716 | flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); |
5653fc33 WD |
717 | break; |
718 | default: | |
719 | break; | |
720 | } | |
721 | return retcode; | |
722 | } | |
bf9e3b38 | 723 | |
5653fc33 WD |
724 | /*----------------------------------------------------------------------- |
725 | */ | |
bf9e3b38 | 726 | static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) |
5653fc33 | 727 | { |
4d13cbad WD |
728 | #if defined(__LITTLE_ENDIAN) |
729 | unsigned short w; | |
730 | unsigned int l; | |
731 | unsigned long long ll; | |
732 | #endif | |
733 | ||
bf9e3b38 | 734 | switch (info->portwidth) { |
5653fc33 WD |
735 | case FLASH_CFI_8BIT: |
736 | cword->c = c; | |
737 | break; | |
738 | case FLASH_CFI_16BIT: | |
4d13cbad WD |
739 | #if defined(__LITTLE_ENDIAN) |
740 | w = c; | |
741 | w <<= 8; | |
742 | cword->w = (cword->w >> 8) | w; | |
743 | #else | |
5653fc33 | 744 | cword->w = (cword->w << 8) | c; |
4d13cbad | 745 | #endif |
5653fc33 WD |
746 | break; |
747 | case FLASH_CFI_32BIT: | |
4d13cbad WD |
748 | #if defined(__LITTLE_ENDIAN) |
749 | l = c; | |
750 | l <<= 24; | |
751 | cword->l = (cword->l >> 8) | l; | |
752 | #else | |
5653fc33 | 753 | cword->l = (cword->l << 8) | c; |
4d13cbad | 754 | #endif |
5653fc33 WD |
755 | break; |
756 | case FLASH_CFI_64BIT: | |
4d13cbad WD |
757 | #if defined(__LITTLE_ENDIAN) |
758 | ll = c; | |
759 | ll <<= 56; | |
760 | cword->ll = (cword->ll >> 8) | ll; | |
761 | #else | |
5653fc33 | 762 | cword->ll = (cword->ll << 8) | c; |
4d13cbad | 763 | #endif |
5653fc33 WD |
764 | break; |
765 | } | |
766 | } | |
767 | ||
768 | ||
769 | /*----------------------------------------------------------------------- | |
770 | * make a proper sized command based on the port and chip widths | |
771 | */ | |
bf9e3b38 | 772 | static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) |
5653fc33 WD |
773 | { |
774 | int i; | |
bf9e3b38 WD |
775 | |
776 | #if defined(__LITTLE_ENDIAN) | |
028ab6b5 WD |
777 | ushort stmpw; |
778 | uint stmpi; | |
bf9e3b38 WD |
779 | #endif |
780 | uchar *cp = (uchar *) cmdbuf; | |
781 | ||
782 | for (i = 0; i < info->portwidth; i++) | |
783 | *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd; | |
784 | #if defined(__LITTLE_ENDIAN) | |
028ab6b5 WD |
785 | switch (info->portwidth) { |
786 | case FLASH_CFI_8BIT: | |
787 | break; | |
788 | case FLASH_CFI_16BIT: | |
789 | stmpw = *(ushort *) cmdbuf; | |
790 | *(ushort *) cmdbuf = __swab16 (stmpw); | |
791 | break; | |
792 | case FLASH_CFI_32BIT: | |
793 | stmpi = *(uint *) cmdbuf; | |
794 | *(uint *) cmdbuf = __swab32 (stmpi); | |
795 | break; | |
796 | default: | |
4b9206ed | 797 | puts ("WARNING: flash_make_cmd: unsuppported LittleEndian mode\n"); |
028ab6b5 | 798 | break; |
bf9e3b38 WD |
799 | } |
800 | #endif | |
5653fc33 WD |
801 | } |
802 | ||
803 | /* | |
804 | * Write a proper sized command to the correct address | |
805 | */ | |
028ab6b5 | 806 | static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) |
5653fc33 WD |
807 | { |
808 | ||
809 | volatile cfiptr_t addr; | |
810 | cfiword_t cword; | |
bf9e3b38 WD |
811 | |
812 | addr.cp = flash_make_addr (info, sect, offset); | |
813 | flash_make_cmd (info, cmd, &cword); | |
814 | switch (info->portwidth) { | |
5653fc33 | 815 | case FLASH_CFI_8BIT: |
bf9e3b38 WD |
816 | debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd, |
817 | cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
5653fc33 WD |
818 | *addr.cp = cword.c; |
819 | break; | |
820 | case FLASH_CFI_16BIT: | |
bf9e3b38 WD |
821 | debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp, |
822 | cmd, cword.w, | |
5653fc33 WD |
823 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
824 | *addr.wp = cword.w; | |
825 | break; | |
826 | case FLASH_CFI_32BIT: | |
bf9e3b38 WD |
827 | debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp, |
828 | cmd, cword.l, | |
5653fc33 WD |
829 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
830 | *addr.lp = cword.l; | |
831 | break; | |
832 | case FLASH_CFI_64BIT: | |
833 | #ifdef DEBUG | |
bf9e3b38 | 834 | { |
5653fc33 | 835 | char str[20]; |
cd37d9e6 | 836 | |
bf9e3b38 WD |
837 | print_longlong (str, cword.ll); |
838 | ||
839 | debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", | |
840 | addr.llp, cmd, str, | |
5653fc33 WD |
841 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
842 | } | |
843 | #endif | |
844 | *addr.llp = cword.ll; | |
845 | break; | |
846 | } | |
847 | } | |
848 | ||
bf9e3b38 | 849 | static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) |
5653fc33 | 850 | { |
855a496f WD |
851 | flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START); |
852 | flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK); | |
5653fc33 | 853 | } |
bf9e3b38 | 854 | |
5653fc33 WD |
855 | /*----------------------------------------------------------------------- |
856 | */ | |
028ab6b5 | 857 | static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) |
5653fc33 WD |
858 | { |
859 | cfiptr_t cptr; | |
860 | cfiword_t cword; | |
861 | int retval; | |
5653fc33 | 862 | |
bf9e3b38 WD |
863 | cptr.cp = flash_make_addr (info, sect, offset); |
864 | flash_make_cmd (info, cmd, &cword); | |
865 | ||
866 | debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp); | |
867 | switch (info->portwidth) { | |
5653fc33 | 868 | case FLASH_CFI_8BIT: |
bf9e3b38 | 869 | debug ("is= %x %x\n", cptr.cp[0], cword.c); |
5653fc33 WD |
870 | retval = (cptr.cp[0] == cword.c); |
871 | break; | |
872 | case FLASH_CFI_16BIT: | |
bf9e3b38 | 873 | debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w); |
5653fc33 WD |
874 | retval = (cptr.wp[0] == cword.w); |
875 | break; | |
876 | case FLASH_CFI_32BIT: | |
bf9e3b38 | 877 | debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l); |
5653fc33 WD |
878 | retval = (cptr.lp[0] == cword.l); |
879 | break; | |
880 | case FLASH_CFI_64BIT: | |
cd37d9e6 | 881 | #ifdef DEBUG |
bf9e3b38 | 882 | { |
5653fc33 WD |
883 | char str1[20]; |
884 | char str2[20]; | |
bf9e3b38 WD |
885 | |
886 | print_longlong (str1, cptr.llp[0]); | |
887 | print_longlong (str2, cword.ll); | |
888 | debug ("is= %s %s\n", str1, str2); | |
5653fc33 WD |
889 | } |
890 | #endif | |
891 | retval = (cptr.llp[0] == cword.ll); | |
892 | break; | |
893 | default: | |
894 | retval = 0; | |
895 | break; | |
896 | } | |
897 | return retval; | |
898 | } | |
bf9e3b38 | 899 | |
5653fc33 WD |
900 | /*----------------------------------------------------------------------- |
901 | */ | |
028ab6b5 | 902 | static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) |
5653fc33 WD |
903 | { |
904 | cfiptr_t cptr; | |
905 | cfiword_t cword; | |
906 | int retval; | |
bf9e3b38 WD |
907 | |
908 | cptr.cp = flash_make_addr (info, sect, offset); | |
909 | flash_make_cmd (info, cmd, &cword); | |
910 | switch (info->portwidth) { | |
5653fc33 WD |
911 | case FLASH_CFI_8BIT: |
912 | retval = ((cptr.cp[0] & cword.c) == cword.c); | |
913 | break; | |
914 | case FLASH_CFI_16BIT: | |
915 | retval = ((cptr.wp[0] & cword.w) == cword.w); | |
916 | break; | |
917 | case FLASH_CFI_32BIT: | |
918 | retval = ((cptr.lp[0] & cword.l) == cword.l); | |
919 | break; | |
920 | case FLASH_CFI_64BIT: | |
921 | retval = ((cptr.llp[0] & cword.ll) == cword.ll); | |
bf9e3b38 | 922 | break; |
5653fc33 WD |
923 | default: |
924 | retval = 0; | |
925 | break; | |
926 | } | |
927 | return retval; | |
928 | } | |
929 | ||
930 | /*----------------------------------------------------------------------- | |
931 | */ | |
028ab6b5 | 932 | static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) |
5653fc33 WD |
933 | { |
934 | cfiptr_t cptr; | |
935 | cfiword_t cword; | |
936 | int retval; | |
bf9e3b38 WD |
937 | |
938 | cptr.cp = flash_make_addr (info, sect, offset); | |
939 | flash_make_cmd (info, cmd, &cword); | |
940 | switch (info->portwidth) { | |
5653fc33 WD |
941 | case FLASH_CFI_8BIT: |
942 | retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c)); | |
943 | break; | |
944 | case FLASH_CFI_16BIT: | |
945 | retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w)); | |
946 | break; | |
947 | case FLASH_CFI_32BIT: | |
948 | retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l)); | |
949 | break; | |
950 | case FLASH_CFI_64BIT: | |
bf9e3b38 WD |
951 | retval = ((cptr.llp[0] & cword.ll) != |
952 | (cptr.llp[0] & cword.ll)); | |
5653fc33 WD |
953 | break; |
954 | default: | |
955 | retval = 0; | |
956 | break; | |
957 | } | |
958 | return retval; | |
959 | } | |
960 | ||
961 | /*----------------------------------------------------------------------- | |
962 | * detect if flash is compatible with the Common Flash Interface (CFI) | |
963 | * http://www.jedec.org/download/search/jesd68.pdf | |
964 | * | |
965 | */ | |
bf9e3b38 | 966 | static int flash_detect_cfi (flash_info_t * info) |
5653fc33 | 967 | { |
bf9e3b38 WD |
968 | debug ("flash detect cfi\n"); |
969 | ||
970 | for (info->portwidth = FLASH_CFI_8BIT; | |
971 | info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { | |
972 | for (info->chipwidth = FLASH_CFI_BY8; | |
973 | info->chipwidth <= info->portwidth; | |
974 | info->chipwidth <<= 1) { | |
975 | flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); | |
028ab6b5 WD |
976 | flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); |
977 | if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') | |
978 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') | |
979 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { | |
980 | info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE); | |
bf9e3b38 WD |
981 | debug ("device interface is %d\n", |
982 | info->interface); | |
983 | debug ("found port %d chip %d ", | |
984 | info->portwidth, info->chipwidth); | |
985 | debug ("port %d bits chip %d bits\n", | |
028ab6b5 WD |
986 | info->portwidth << CFI_FLASH_SHIFT_WIDTH, |
987 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
5653fc33 WD |
988 | return 1; |
989 | } | |
990 | } | |
991 | } | |
bf9e3b38 | 992 | debug ("not found\n"); |
5653fc33 WD |
993 | return 0; |
994 | } | |
bf9e3b38 | 995 | |
5653fc33 WD |
996 | /* |
997 | * The following code cannot be run from FLASH! | |
998 | * | |
999 | */ | |
1000 | static ulong flash_get_size (ulong base, int banknum) | |
1001 | { | |
bf9e3b38 | 1002 | flash_info_t *info = &flash_info[banknum]; |
5653fc33 WD |
1003 | int i, j; |
1004 | flash_sect_t sect_cnt; | |
1005 | unsigned long sector; | |
1006 | unsigned long tmp; | |
1007 | int size_ratio; | |
1008 | uchar num_erase_regions; | |
bf9e3b38 WD |
1009 | int erase_region_size; |
1010 | int erase_region_count; | |
5653fc33 WD |
1011 | |
1012 | info->start[0] = base; | |
1013 | ||
bf9e3b38 | 1014 | if (flash_detect_cfi (info)) { |
028ab6b5 | 1015 | info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR); |
bf9e3b38 WD |
1016 | #ifdef DEBUG |
1017 | flash_printqry (info, 0); | |
1018 | #endif | |
1019 | switch (info->vendor) { | |
5653fc33 WD |
1020 | case CFI_CMDSET_INTEL_STANDARD: |
1021 | case CFI_CMDSET_INTEL_EXTENDED: | |
1022 | default: | |
1023 | info->cmd_reset = FLASH_CMD_RESET; | |
1024 | break; | |
1025 | case CFI_CMDSET_AMD_STANDARD: | |
1026 | case CFI_CMDSET_AMD_EXTENDED: | |
1027 | info->cmd_reset = AMD_CMD_RESET; | |
1028 | break; | |
1029 | } | |
cd37d9e6 | 1030 | |
bf9e3b38 | 1031 | debug ("manufacturer is %d\n", info->vendor); |
5653fc33 | 1032 | size_ratio = info->portwidth / info->chipwidth; |
bf9e3b38 WD |
1033 | /* if the chip is x8/x16 reduce the ratio by half */ |
1034 | if ((info->interface == FLASH_CFI_X8X16) | |
1035 | && (info->chipwidth == FLASH_CFI_BY8)) { | |
1036 | size_ratio >>= 1; | |
1037 | } | |
028ab6b5 | 1038 | num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS); |
bf9e3b38 WD |
1039 | debug ("size_ratio %d port %d bits chip %d bits\n", |
1040 | size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
1041 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
1042 | debug ("found %d erase regions\n", num_erase_regions); | |
5653fc33 WD |
1043 | sect_cnt = 0; |
1044 | sector = base; | |
bf9e3b38 WD |
1045 | for (i = 0; i < num_erase_regions; i++) { |
1046 | if (i > NUM_ERASE_REGIONS) { | |
028ab6b5 WD |
1047 | printf ("%d erase regions found, only %d used\n", |
1048 | num_erase_regions, NUM_ERASE_REGIONS); | |
5653fc33 WD |
1049 | break; |
1050 | } | |
bf9e3b38 WD |
1051 | tmp = flash_read_long (info, 0, |
1052 | FLASH_OFFSET_ERASE_REGIONS + | |
1053 | i * 4); | |
1054 | erase_region_size = | |
1055 | (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; | |
5653fc33 | 1056 | tmp >>= 16; |
bf9e3b38 | 1057 | erase_region_count = (tmp & 0xffff) + 1; |
4c0d4c3b | 1058 | debug ("erase_region_count = %d erase_region_size = %d\n", |
028ab6b5 | 1059 | erase_region_count, erase_region_size); |
bf9e3b38 | 1060 | for (j = 0; j < erase_region_count; j++) { |
5653fc33 WD |
1061 | info->start[sect_cnt] = sector; |
1062 | sector += (erase_region_size * size_ratio); | |
bf9e3b38 WD |
1063 | info->protect[sect_cnt] = |
1064 | flash_isset (info, sect_cnt, | |
1065 | FLASH_OFFSET_PROTECT, | |
1066 | FLASH_STATUS_PROTECT); | |
5653fc33 WD |
1067 | sect_cnt++; |
1068 | } | |
1069 | } | |
1070 | ||
1071 | info->sector_count = sect_cnt; | |
1072 | /* multiply the size by the number of chips */ | |
028ab6b5 WD |
1073 | info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio; |
1074 | info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE)); | |
bf9e3b38 | 1075 | tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); |
028ab6b5 | 1076 | info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); |
bf9e3b38 | 1077 | tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); |
028ab6b5 | 1078 | info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); |
bf9e3b38 | 1079 | tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT); |
028ab6b5 | 1080 | info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000; |
5653fc33 | 1081 | info->flash_id = FLASH_MAN_CFI; |
855a496f WD |
1082 | if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { |
1083 | info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */ | |
1084 | } | |
5653fc33 WD |
1085 | } |
1086 | ||
bf9e3b38 WD |
1087 | flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); |
1088 | return (info->size); | |
5653fc33 WD |
1089 | } |
1090 | ||
1091 | ||
1092 | /*----------------------------------------------------------------------- | |
1093 | */ | |
bf9e3b38 WD |
1094 | static int flash_write_cfiword (flash_info_t * info, ulong dest, |
1095 | cfiword_t cword) | |
5653fc33 WD |
1096 | { |
1097 | ||
1098 | cfiptr_t ctladdr; | |
1099 | cfiptr_t cptr; | |
1100 | int flag; | |
1101 | ||
bf9e3b38 WD |
1102 | ctladdr.cp = flash_make_addr (info, 0, 0); |
1103 | cptr.cp = (uchar *) dest; | |
5653fc33 WD |
1104 | |
1105 | ||
1106 | /* Check if Flash is (sufficiently) erased */ | |
bf9e3b38 | 1107 | switch (info->portwidth) { |
5653fc33 WD |
1108 | case FLASH_CFI_8BIT: |
1109 | flag = ((cptr.cp[0] & cword.c) == cword.c); | |
1110 | break; | |
1111 | case FLASH_CFI_16BIT: | |
1112 | flag = ((cptr.wp[0] & cword.w) == cword.w); | |
1113 | break; | |
1114 | case FLASH_CFI_32BIT: | |
bf9e3b38 | 1115 | flag = ((cptr.lp[0] & cword.l) == cword.l); |
5653fc33 WD |
1116 | break; |
1117 | case FLASH_CFI_64BIT: | |
1118 | flag = ((cptr.lp[0] & cword.ll) == cword.ll); | |
1119 | break; | |
1120 | default: | |
1121 | return 2; | |
1122 | } | |
bf9e3b38 | 1123 | if (!flag) |
5653fc33 WD |
1124 | return 2; |
1125 | ||
1126 | /* Disable interrupts which might cause a timeout here */ | |
bf9e3b38 | 1127 | flag = disable_interrupts (); |
5653fc33 | 1128 | |
bf9e3b38 | 1129 | switch (info->vendor) { |
5653fc33 WD |
1130 | case CFI_CMDSET_INTEL_EXTENDED: |
1131 | case CFI_CMDSET_INTEL_STANDARD: | |
bf9e3b38 WD |
1132 | flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); |
1133 | flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); | |
5653fc33 WD |
1134 | break; |
1135 | case CFI_CMDSET_AMD_EXTENDED: | |
1136 | case CFI_CMDSET_AMD_STANDARD: | |
bf9e3b38 | 1137 | flash_unlock_seq (info, 0); |
855a496f | 1138 | flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE); |
5653fc33 WD |
1139 | break; |
1140 | } | |
1141 | ||
bf9e3b38 | 1142 | switch (info->portwidth) { |
5653fc33 WD |
1143 | case FLASH_CFI_8BIT: |
1144 | cptr.cp[0] = cword.c; | |
1145 | break; | |
1146 | case FLASH_CFI_16BIT: | |
1147 | cptr.wp[0] = cword.w; | |
1148 | break; | |
1149 | case FLASH_CFI_32BIT: | |
1150 | cptr.lp[0] = cword.l; | |
1151 | break; | |
1152 | case FLASH_CFI_64BIT: | |
1153 | cptr.llp[0] = cword.ll; | |
1154 | break; | |
1155 | } | |
1156 | ||
1157 | /* re-enable interrupts if necessary */ | |
bf9e3b38 WD |
1158 | if (flag) |
1159 | enable_interrupts (); | |
5653fc33 | 1160 | |
bf9e3b38 | 1161 | return flash_full_status_check (info, 0, info->write_tout, "write"); |
5653fc33 WD |
1162 | } |
1163 | ||
1164 | #ifdef CFG_FLASH_USE_BUFFER_WRITE | |
1165 | ||
1166 | /* loop through the sectors from the highest address | |
1167 | * when the passed address is greater or equal to the sector address | |
1168 | * we have a match | |
1169 | */ | |
bf9e3b38 | 1170 | static flash_sect_t find_sector (flash_info_t * info, ulong addr) |
5653fc33 WD |
1171 | { |
1172 | flash_sect_t sector; | |
bf9e3b38 WD |
1173 | |
1174 | for (sector = info->sector_count - 1; sector >= 0; sector--) { | |
1175 | if (addr >= info->start[sector]) | |
5653fc33 WD |
1176 | break; |
1177 | } | |
1178 | return sector; | |
1179 | } | |
1180 | ||
bf9e3b38 WD |
1181 | static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, |
1182 | int len) | |
5653fc33 WD |
1183 | { |
1184 | flash_sect_t sector; | |
1185 | int cnt; | |
1186 | int retcode; | |
1187 | volatile cfiptr_t src; | |
1188 | volatile cfiptr_t dst; | |
855a496f WD |
1189 | /* buffered writes in the AMD chip set is not supported yet */ |
1190 | if((info->vendor == CFI_CMDSET_AMD_STANDARD) || | |
1191 | (info->vendor == CFI_CMDSET_AMD_EXTENDED)) | |
1192 | return ERR_INVAL; | |
5653fc33 WD |
1193 | |
1194 | src.cp = cp; | |
bf9e3b38 WD |
1195 | dst.cp = (uchar *) dest; |
1196 | sector = find_sector (info, dest); | |
1197 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); | |
1198 | flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); | |
1199 | if ((retcode = | |
1200 | flash_status_check (info, sector, info->buffer_write_tout, | |
1201 | "write to buffer")) == ERR_OK) { | |
1202 | /* reduce the number of loops by the width of the port */ | |
1203 | switch (info->portwidth) { | |
5653fc33 WD |
1204 | case FLASH_CFI_8BIT: |
1205 | cnt = len; | |
1206 | break; | |
1207 | case FLASH_CFI_16BIT: | |
1208 | cnt = len >> 1; | |
1209 | break; | |
1210 | case FLASH_CFI_32BIT: | |
1211 | cnt = len >> 2; | |
1212 | break; | |
1213 | case FLASH_CFI_64BIT: | |
1214 | cnt = len >> 3; | |
1215 | break; | |
1216 | default: | |
1217 | return ERR_INVAL; | |
1218 | break; | |
1219 | } | |
bf9e3b38 WD |
1220 | flash_write_cmd (info, sector, 0, (uchar) cnt - 1); |
1221 | while (cnt-- > 0) { | |
1222 | switch (info->portwidth) { | |
5653fc33 WD |
1223 | case FLASH_CFI_8BIT: |
1224 | *dst.cp++ = *src.cp++; | |
1225 | break; | |
1226 | case FLASH_CFI_16BIT: | |
1227 | *dst.wp++ = *src.wp++; | |
1228 | break; | |
1229 | case FLASH_CFI_32BIT: | |
1230 | *dst.lp++ = *src.lp++; | |
1231 | break; | |
1232 | case FLASH_CFI_64BIT: | |
1233 | *dst.llp++ = *src.llp++; | |
1234 | break; | |
1235 | default: | |
1236 | return ERR_INVAL; | |
1237 | break; | |
1238 | } | |
1239 | } | |
bf9e3b38 WD |
1240 | flash_write_cmd (info, sector, 0, |
1241 | FLASH_CMD_WRITE_BUFFER_CONFIRM); | |
1242 | retcode = | |
1243 | flash_full_status_check (info, sector, | |
1244 | info->buffer_write_tout, | |
1245 | "buffer write"); | |
5653fc33 | 1246 | } |
bf9e3b38 | 1247 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
5653fc33 WD |
1248 | return retcode; |
1249 | } | |
cce625e5 | 1250 | #endif /* CFG_FLASH_USE_BUFFER_WRITE */ |
5653fc33 | 1251 | #endif /* CFG_FLASH_CFI */ |