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clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c
[people/ms/u-boot.git] / drivers / clk / Kconfig
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81385818
MY
1menu "Clock"
2
f26c8a8e
SG
3config CLK
4 bool "Enable clock driver support"
5 depends on DM
6 help
7 This allows drivers to be provided for clock generators, including
8 oscillators and PLLs. Devices can use a common clock API to request
9 a particular clock rate and check on available clocks. Clocks can
10 feed into other clocks in a tree structure, with multiplexers to
11 choose the source for each clock.
12
05435891 13config SPL_CLK
f26c8a8e 14 bool "Enable clock support in SPL"
0712b672 15 depends on CLK && SPL && SPL_DM
f26c8a8e
SG
16 help
17 The clock subsystem adds a small amount of overhead to the image.
18 If this is acceptable and you have a need to use clock drivers in
19 SPL, enable this option. It might provide a cleaner interface to
20 setting up clocks within SPL, and allows the same drivers to be
21 used as U-Boot proper.
81385818 22
7c819e7f
PT
23config TPL_CLK
24 bool "Enable clock support in TPL"
25 depends on CLK && TPL_DM
26 help
27 The clock subsystem adds a small amount of overhead to the image.
28 If this is acceptable and you have a need to use clock drivers in
29 SPL, enable this option. It might provide a cleaner interface to
30 setting up clocks within TPL, and allows the same drivers to be
31 used as U-Boot proper.
32
5357eb95
ÁFR
33config CLK_BCM6345
34 bool "Clock controller driver for BCM6345"
35 depends on CLK && ARCH_BMIPS
36 default y
37 help
38 This clock driver adds support for enabling and disabling peripheral
39 clocks on BCM6345 SoCs. HW has no rate changing capabilities.
40
dd7c7494
PB
41config CLK_BOSTON
42 def_bool y if TARGET_BOSTON
43 depends on CLK
44 select REGMAP
45 select SYSCON
46 help
47 Enable this to support the clocks
48
f264e235
PC
49config CLK_STM32F
50 bool "Enable clock driver support for STM32F family"
51 depends on CLK && (STM32F7 || STM32F4)
52 default y
53 help
54 This clock driver adds support for RCC clock management
55 for STM32F4 and STM32F7 SoCs.
56
3a64b253
SH
57config CLK_ZYNQ
58 bool "Enable clock driver support for Zynq"
59 depends on CLK && ARCH_ZYNQ
60 default y
61 help
62 This clock driver adds support for clock realted settings for
63 Zynq platform.
64
128ec1fe
SDPP
65config CLK_ZYNQMP
66 bool "Enable clock driver support for ZynqMP"
67 depends on ARCH_ZYNQMP
68 help
69 This clock driver adds support for clock realted settings for
70 ZynqMP platform.
71
d9fd7008 72source "drivers/clk/tegra/Kconfig"
48264d9b 73source "drivers/clk/uniphier/Kconfig"
166097e8 74source "drivers/clk/exynos/Kconfig"
9e5935c0 75source "drivers/clk/at91/Kconfig"
36c2ee4c 76source "drivers/clk/renesas/Kconfig"
48264d9b 77
81385818 78endmenu