[people/ms/u-boot.git] / drivers / clk / at91 / clk-peripheral.c

/*
 * Copyright (C) 2016 Atmel Corporation
 *               Wenyou.Yang <wenyou.yang@atmel.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm/device.h>
#include <linux/io.h>
#include <mach/at91_pmc.h>
#include "pmc.h"

#define PERIPHERAL_ID_MIN	2
#define PERIPHERAL_ID_MAX	31
#define PERIPHERAL_MASK(id)	(1 << ((id) & PERIPHERAL_ID_MAX))

/**
 * sam9x5_periph_clk_bind() - for the periph clock driver
 * Recursively bind its children as clk devices.
 *
 * @return: 0 on success, or negative error code on failure
 */
static int sam9x5_periph_clk_bind(struct udevice *dev)
{
	return at91_clk_sub_device_bind(dev, "periph-clk");
}

static const struct udevice_id sam9x5_periph_clk_match[] = {
	{ .compatible = "atmel,at91sam9x5-clk-peripheral" },
	{}
};

U_BOOT_DRIVER(sam9x5_periph_clk) = {
	.name = "sam9x5-periph-clk",
	.id = UCLASS_MISC,
	.of_match = sam9x5_periph_clk_match,
	.bind = sam9x5_periph_clk_bind,
};

/*---------------------------------------------------------*/

static int periph_clk_enable(struct clk *clk)
{
	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
	struct at91_pmc *pmc = plat->reg_base;

	if (clk->id < PERIPHERAL_ID_MIN)
		return -1;

	writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
	setbits_le32(&pmc->pcr, AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);

	return 0;
}

static ulong periph_get_rate(struct clk *clk)
{
	struct udevice *dev;
	struct clk clk_dev;
	ulong clk_rate;
	int ret;

	dev = dev_get_parent(clk->dev);

	ret = clk_get_by_index(dev, 0, &clk_dev);
	if (ret)
		return ret;

	clk_rate = clk_get_rate(&clk_dev);

	clk_free(&clk_dev);

	return clk_rate;
}

static struct clk_ops periph_clk_ops = {
	.of_xlate = at91_clk_of_xlate,
	.enable = periph_clk_enable,
	.get_rate = periph_get_rate,
};

U_BOOT_DRIVER(clk_periph) = {
	.name	= "periph-clk",
	.id	= UCLASS_CLK,
	.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
	.probe = at91_clk_probe,
	.ops	= &periph_clk_ops,
};
Commit	Line	Data
9e5935c0 WY	1	/*
	2	* Copyright (C) 2016 Atmel Corporation
	3	* Wenyou.Yang <wenyou.yang@atmel.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <clk-uclass.h>
	10	#include <dm/device.h>
	11	#include <linux/io.h>
	12	#include <mach/at91_pmc.h>
	13	#include "pmc.h"
	14
	15	#define PERIPHERAL_ID_MIN 2
	16	#define PERIPHERAL_ID_MAX 31
	17	#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
	18
6cadaa04 WY	19	/**
	20	* sam9x5_periph_clk_bind() - for the periph clock driver
	21	* Recursively bind its children as clk devices.
	22	*
	23	* @return: 0 on success, or negative error code on failure
	24	*/
	25	static int sam9x5_periph_clk_bind(struct udevice *dev)
	26	{
	27	return at91_clk_sub_device_bind(dev, "periph-clk");
	28	}
	29
	30	static const struct udevice_id sam9x5_periph_clk_match[] = {
	31	{ .compatible = "atmel,at91sam9x5-clk-peripheral" },
	32	{}
	33	};
	34
	35	U_BOOT_DRIVER(sam9x5_periph_clk) = {
	36	.name = "sam9x5-periph-clk",
	37	.id = UCLASS_MISC,
	38	.of_match = sam9x5_periph_clk_match,
	39	.bind = sam9x5_periph_clk_bind,
	40	};
	41
	42	/---------------------------------------------------------/
	43
	44	static int periph_clk_enable(struct clk *clk)
9e5935c0 WY	45	{
	46	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
	47	struct at91_pmc *pmc = plat->reg_base;
	48
	49	if (clk->id < PERIPHERAL_ID_MIN)
	50	return -1;
	51
	52	writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
	53	setbits_le32(&pmc->pcr, AT91_PMC_PCR_CMD_WRITE \| AT91_PMC_PCR_EN);
	54
	55	return 0;
	56	}
	57
6cadaa04	58	static ulong periph_get_rate(struct clk *clk)
9e5935c0	59	{
6cadaa04 WY	60	struct udevice *dev;
	61	struct clk clk_dev;
	62	ulong clk_rate;
	63	int ret;
9e5935c0	64
6cadaa04 WY	65	dev = dev_get_parent(clk->dev);
	66
	67	ret = clk_get_by_index(dev, 0, &clk_dev);
	68	if (ret)
	69	return ret;
	70
	71	clk_rate = clk_get_rate(&clk_dev);
	72
	73	clk_free(&clk_dev);
	74
	75	return clk_rate;
9e5935c0 WY	76	}
9e5935c0 WY	77
6cadaa04 WY	78	static struct clk_ops periph_clk_ops = {
	79	.of_xlate = at91_clk_of_xlate,
	80	.enable = periph_clk_enable,
	81	.get_rate = periph_get_rate,
9e5935c0 WY	82	};
9e5935c0 WY	83
6cadaa04 WY	84	U_BOOT_DRIVER(clk_periph) = {
	85	.name = "periph-clk",
	86	.id = UCLASS_CLK,
9e5935c0	87	.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
6cadaa04 WY	88	.probe = at91_clk_probe,
6cadaa04 WY	89	.ops = &periph_clk_ops,
9e5935c0	90	};