[thirdparty/linux.git] / drivers / clk / clk-max77686.c

// SPDX-License-Identifier: GPL-2.0+
//
// clk-max77686.c - Clock driver for Maxim 77686/MAX77802
//
// Copyright (C) 2012 Samsung Electornics
// Jonghwa Lee <jonghwa3.lee@samsung.com>

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/max77620.h>
#include <linux/mfd/max77686.h>
#include <linux/mfd/max77686-private.h>
#include <linux/clk-provider.h>
#include <linux/mutex.h>
#include <linux/clkdev.h>
#include <linux/of.h>
#include <linux/regmap.h>

#include <dt-bindings/clock/maxim,max77686.h>
#include <dt-bindings/clock/maxim,max77802.h>
#include <dt-bindings/clock/maxim,max77620.h>

#define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3

enum max77686_chip_name {
	CHIP_MAX77686,
	CHIP_MAX77802,
	CHIP_MAX77620,
};

struct max77686_hw_clk_info {
	const char *name;
	u32 clk_reg;
	u32 clk_enable_mask;
	u32 flags;
};

struct max77686_clk_init_data {
	struct regmap *regmap;
	struct clk_hw hw;
	struct clk_init_data clk_idata;
	const struct max77686_hw_clk_info *clk_info;
};

struct max77686_clk_driver_data {
	enum max77686_chip_name chip;
	struct max77686_clk_init_data *max_clk_data;
	size_t num_clks;
};

static const struct
max77686_hw_clk_info max77686_hw_clks_info[MAX77686_CLKS_NUM] = {
	[MAX77686_CLK_AP] = {
		.name = "32khz_ap",
		.clk_reg = MAX77686_REG_32KHZ,
		.clk_enable_mask = BIT(MAX77686_CLK_AP),
	},
	[MAX77686_CLK_CP] = {
		.name = "32khz_cp",
		.clk_reg = MAX77686_REG_32KHZ,
		.clk_enable_mask = BIT(MAX77686_CLK_CP),
	},
	[MAX77686_CLK_PMIC] = {
		.name = "32khz_pmic",
		.clk_reg = MAX77686_REG_32KHZ,
		.clk_enable_mask = BIT(MAX77686_CLK_PMIC),
	},
};

static const struct
max77686_hw_clk_info max77802_hw_clks_info[MAX77802_CLKS_NUM] = {
	[MAX77802_CLK_32K_AP] = {
		.name = "32khz_ap",
		.clk_reg = MAX77802_REG_32KHZ,
		.clk_enable_mask = BIT(MAX77802_CLK_32K_AP),
	},
	[MAX77802_CLK_32K_CP] = {
		.name = "32khz_cp",
		.clk_reg = MAX77802_REG_32KHZ,
		.clk_enable_mask = BIT(MAX77802_CLK_32K_CP),
	},
};

static const struct
max77686_hw_clk_info max77620_hw_clks_info[MAX77620_CLKS_NUM] = {
	[MAX77620_CLK_32K_OUT0] = {
		.name = "32khz_out0",
		.clk_reg = MAX77620_REG_CNFG1_32K,
		.clk_enable_mask = MAX77620_CNFG1_32K_OUT0_EN,
	},
};

static struct max77686_clk_init_data *to_max77686_clk_init_data(
				struct clk_hw *hw)
{
	return container_of(hw, struct max77686_clk_init_data, hw);
}

static int max77686_clk_prepare(struct clk_hw *hw)
{
	struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);

	return regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
				  max77686->clk_info->clk_enable_mask,
				  max77686->clk_info->clk_enable_mask);
}

static void max77686_clk_unprepare(struct clk_hw *hw)
{
	struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);

	regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
			   max77686->clk_info->clk_enable_mask,
			   ~max77686->clk_info->clk_enable_mask);
}

static int max77686_clk_is_prepared(struct clk_hw *hw)
{
	struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
	int ret;
	u32 val;

	ret = regmap_read(max77686->regmap, max77686->clk_info->clk_reg, &val);

	if (ret < 0)
		return -EINVAL;

	return val & max77686->clk_info->clk_enable_mask;
}

static unsigned long max77686_recalc_rate(struct clk_hw *hw,
					  unsigned long parent_rate)
{
	return 32768;
}

static const struct clk_ops max77686_clk_ops = {
	.prepare	= max77686_clk_prepare,
	.unprepare	= max77686_clk_unprepare,
	.is_prepared	= max77686_clk_is_prepared,
	.recalc_rate	= max77686_recalc_rate,
};

static struct clk_hw *
of_clk_max77686_get(struct of_phandle_args *clkspec, void *data)
{
	struct max77686_clk_driver_data *drv_data = data;
	unsigned int idx = clkspec->args[0];

	if (idx >= drv_data->num_clks) {
		pr_err("%s: invalid index %u\n", __func__, idx);
		return ERR_PTR(-EINVAL);
	}

	return &drv_data->max_clk_data[idx].hw;
}

static int max77686_clk_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device *parent = dev->parent;
	const struct platform_device_id *id = platform_get_device_id(pdev);
	struct max77686_clk_driver_data *drv_data;
	const struct max77686_hw_clk_info *hw_clks;
	struct regmap *regmap;
	int i, ret, num_clks;

	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
	if (!drv_data)
		return -ENOMEM;

	regmap = dev_get_regmap(parent, NULL);
	if (!regmap) {
		dev_err(dev, "Failed to get rtc regmap\n");
		return -ENODEV;
	}

	drv_data->chip = id->driver_data;

	switch (drv_data->chip) {
	case CHIP_MAX77686:
		num_clks = MAX77686_CLKS_NUM;
		hw_clks = max77686_hw_clks_info;
		break;

	case CHIP_MAX77802:
		num_clks = MAX77802_CLKS_NUM;
		hw_clks = max77802_hw_clks_info;
		break;

	case CHIP_MAX77620:
		num_clks = MAX77620_CLKS_NUM;
		hw_clks = max77620_hw_clks_info;
		break;

	default:
		dev_err(dev, "Unknown Chip ID\n");
		return -EINVAL;
	}

	drv_data->num_clks = num_clks;
	drv_data->max_clk_data = devm_kcalloc(dev, num_clks,
					      sizeof(*drv_data->max_clk_data),
					      GFP_KERNEL);
	if (!drv_data->max_clk_data)
		return -ENOMEM;

	for (i = 0; i < num_clks; i++) {
		struct max77686_clk_init_data *max_clk_data;
		const char *clk_name;

		max_clk_data = &drv_data->max_clk_data[i];

		max_clk_data->regmap = regmap;
		max_clk_data->clk_info = &hw_clks[i];
		max_clk_data->clk_idata.flags = hw_clks[i].flags;
		max_clk_data->clk_idata.ops = &max77686_clk_ops;

		if (parent->of_node &&
		    !of_property_read_string_index(parent->of_node,
						   "clock-output-names",
						   i, &clk_name))
			max_clk_data->clk_idata.name = clk_name;
		else
			max_clk_data->clk_idata.name = hw_clks[i].name;

		max_clk_data->hw.init = &max_clk_data->clk_idata;

		ret = devm_clk_hw_register(dev, &max_clk_data->hw);
		if (ret) {
			dev_err(dev, "Failed to clock register: %d\n", ret);
			return ret;
		}

		ret = devm_clk_hw_register_clkdev(dev, &max_clk_data->hw,
						  max_clk_data->clk_idata.name,
						  NULL);
		if (ret < 0) {
			dev_err(dev, "Failed to clkdev register: %d\n", ret);
			return ret;
		}
	}

	if (parent->of_node) {
		ret = devm_of_clk_add_hw_provider(dev, of_clk_max77686_get,
						  drv_data);

		if (ret < 0) {
			dev_err(dev, "Failed to register OF clock provider: %d\n",
				ret);
			return ret;
		}
	}

	/* MAX77802: Enable low-jitter mode on the 32khz clocks. */
	if (drv_data->chip == CHIP_MAX77802) {
		ret = regmap_update_bits(regmap, MAX77802_REG_32KHZ,
					 1 << MAX77802_CLOCK_LOW_JITTER_SHIFT,
					 1 << MAX77802_CLOCK_LOW_JITTER_SHIFT);
		if (ret < 0) {
			dev_err(dev, "Failed to config low-jitter: %d\n", ret);
			return ret;
		}
	}

	return 0;
}

static const struct platform_device_id max77686_clk_id[] = {
	{ "max77686-clk", .driver_data = CHIP_MAX77686, },
	{ "max77802-clk", .driver_data = CHIP_MAX77802, },
	{ "max77620-clock", .driver_data = CHIP_MAX77620, },
	{},
};
MODULE_DEVICE_TABLE(platform, max77686_clk_id);

static struct platform_driver max77686_clk_driver = {
	.driver = {
		.name  = "max77686-clk",
	},
	.probe = max77686_clk_probe,
	.id_table = max77686_clk_id,
};

module_platform_driver(max77686_clk_driver);

MODULE_DESCRIPTION("MAXIM 77686 Clock Driver");
MODULE_AUTHOR("Jonghwa Lee <jonghwa3.lee@samsung.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
f300168a KK	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// clk-max77686.c - Clock driver for Maxim 77686/MAX77802
	4	//
	5	// Copyright (C) 2012 Samsung Electornics
	6	// Jonghwa Lee <jonghwa3.lee@samsung.com>
73118e61 JL	7
	8	#include <linux/kernel.h>
	9	#include <linux/slab.h>
	10	#include <linux/err.h>
a0c4dfee	11	#include <linux/module.h>
73118e61	12	#include <linux/platform_device.h>
5a227cd1	13	#include <linux/mfd/max77620.h>
73118e61 JL	14	#include <linux/mfd/max77686.h>
	15	#include <linux/mfd/max77686-private.h>
	16	#include <linux/clk-provider.h>
	17	#include <linux/mutex.h>
	18	#include <linux/clkdev.h>
8ad313fe LD	19	#include <linux/of.h>
8ad313fe LD	20	#include <linux/regmap.h>
73118e61	21
a8a76f56	22	#include <dt-bindings/clock/maxim,max77686.h>
8ad313fe	23	#include <dt-bindings/clock/maxim,max77802.h>
5a227cd1	24	#include <dt-bindings/clock/maxim,max77620.h>
73118e61	25
8ad313fe LD	26	#define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3
	27
	28	enum max77686_chip_name {
	29	CHIP_MAX77686,
	30	CHIP_MAX77802,
5a227cd1	31	CHIP_MAX77620,
8ad313fe LD	32	};
	33
	34	struct max77686_hw_clk_info {
	35	const char *name;
	36	u32 clk_reg;
	37	u32 clk_enable_mask;
	38	u32 flags;
	39	};
	40
	41	struct max77686_clk_init_data {
	42	struct regmap *regmap;
	43	struct clk_hw hw;
	44	struct clk_init_data clk_idata;
	45	const struct max77686_hw_clk_info *clk_info;
	46	};
	47
	48	struct max77686_clk_driver_data {
	49	enum max77686_chip_name chip;
8ad313fe	50	struct max77686_clk_init_data *max_clk_data;
9b4cac33	51	size_t num_clks;
8ad313fe LD	52	};
	53
	54	static const struct
	55	max77686_hw_clk_info max77686_hw_clks_info[MAX77686_CLKS_NUM] = {
73118e61 JL	56	[MAX77686_CLK_AP] = {
73118e61 JL	57	.name = "32khz_ap",
8ad313fe LD	58	.clk_reg = MAX77686_REG_32KHZ,
8ad313fe LD	59	.clk_enable_mask = BIT(MAX77686_CLK_AP),
73118e61 JL	60	},
	61	[MAX77686_CLK_CP] = {
	62	.name = "32khz_cp",
8ad313fe LD	63	.clk_reg = MAX77686_REG_32KHZ,
8ad313fe LD	64	.clk_enable_mask = BIT(MAX77686_CLK_CP),
73118e61 JL	65	},
	66	[MAX77686_CLK_PMIC] = {
	67	.name = "32khz_pmic",
8ad313fe LD	68	.clk_reg = MAX77686_REG_32KHZ,
	69	.clk_enable_mask = BIT(MAX77686_CLK_PMIC),
	70	},
	71	};
	72
	73	static const struct
	74	max77686_hw_clk_info max77802_hw_clks_info[MAX77802_CLKS_NUM] = {
	75	[MAX77802_CLK_32K_AP] = {
	76	.name = "32khz_ap",
	77	.clk_reg = MAX77802_REG_32KHZ,
	78	.clk_enable_mask = BIT(MAX77802_CLK_32K_AP),
	79	},
	80	[MAX77802_CLK_32K_CP] = {
	81	.name = "32khz_cp",
	82	.clk_reg = MAX77802_REG_32KHZ,
	83	.clk_enable_mask = BIT(MAX77802_CLK_32K_CP),
73118e61 JL	84	},
	85	};
	86
5a227cd1 LD	87	static const struct
	88	max77686_hw_clk_info max77620_hw_clks_info[MAX77620_CLKS_NUM] = {
	89	[MAX77620_CLK_32K_OUT0] = {
	90	.name = "32khz_out0",
	91	.clk_reg = MAX77620_REG_CNFG1_32K,
	92	.clk_enable_mask = MAX77620_CNFG1_32K_OUT0_EN,
	93	},
	94	};
	95
8ad313fe LD	96	static struct max77686_clk_init_data *to_max77686_clk_init_data(
	97	struct clk_hw *hw)
	98	{
	99	return container_of(hw, struct max77686_clk_init_data, hw);
	100	}
	101
	102	static int max77686_clk_prepare(struct clk_hw *hw)
	103	{
	104	struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
	105
	106	return regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
	107	max77686->clk_info->clk_enable_mask,
	108	max77686->clk_info->clk_enable_mask);
	109	}
	110
	111	static void max77686_clk_unprepare(struct clk_hw *hw)
	112	{
	113	struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
	114
	115	regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
	116	max77686->clk_info->clk_enable_mask,
	117	~max77686->clk_info->clk_enable_mask);
	118	}
	119
	120	static int max77686_clk_is_prepared(struct clk_hw *hw)
	121	{
	122	struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
	123	int ret;
	124	u32 val;
	125
	126	ret = regmap_read(max77686->regmap, max77686->clk_info->clk_reg, &val);
	127
	128	if (ret < 0)
	129	return -EINVAL;
	130
	131	return val & max77686->clk_info->clk_enable_mask;
	132	}
	133
	134	static unsigned long max77686_recalc_rate(struct clk_hw *hw,
	135	unsigned long parent_rate)
	136	{
	137	return 32768;
	138	}
	139
25600dad	140	static const struct clk_ops max77686_clk_ops = {
8ad313fe LD	141	.prepare = max77686_clk_prepare,
	142	.unprepare = max77686_clk_unprepare,
	143	.is_prepared = max77686_clk_is_prepared,
	144	.recalc_rate = max77686_recalc_rate,
	145	};
	146
9b4cac33 SB	147	static struct clk_hw *
	148	of_clk_max77686_get(struct of_phandle_args clkspec, void data)
	149	{
	150	struct max77686_clk_driver_data *drv_data = data;
	151	unsigned int idx = clkspec->args[0];
	152
	153	if (idx >= drv_data->num_clks) {
	154	pr_err("%s: invalid index %u\n", __func__, idx);
	155	return ERR_PTR(-EINVAL);
	156	}
	157
	158	return &drv_data->max_clk_data[idx].hw;
	159	}
	160
018ae93f	161	static int max77686_clk_probe(struct platform_device *pdev)
73118e61	162	{
8ad313fe LD	163	struct device *dev = &pdev->dev;
	164	struct device *parent = dev->parent;
	165	const struct platform_device_id *id = platform_get_device_id(pdev);
	166	struct max77686_clk_driver_data *drv_data;
	167	const struct max77686_hw_clk_info *hw_clks;
	168	struct regmap *regmap;
	169	int i, ret, num_clks;
	170
	171	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
	172	if (!drv_data)
	173	return -ENOMEM;
	174
	175	regmap = dev_get_regmap(parent, NULL);
	176	if (!regmap) {
	177	dev_err(dev, "Failed to get rtc regmap\n");
	178	return -ENODEV;
	179	}
	180
	181	drv_data->chip = id->driver_data;
	182
	183	switch (drv_data->chip) {
	184	case CHIP_MAX77686:
	185	num_clks = MAX77686_CLKS_NUM;
	186	hw_clks = max77686_hw_clks_info;
	187	break;
	188
	189	case CHIP_MAX77802:
	190	num_clks = MAX77802_CLKS_NUM;
	191	hw_clks = max77802_hw_clks_info;
	192	break;
	193
5a227cd1 LD	194	case CHIP_MAX77620:
	195	num_clks = MAX77620_CLKS_NUM;
	196	hw_clks = max77620_hw_clks_info;
	197	break;
	198
8ad313fe LD	199	default:
	200	dev_err(dev, "Unknown Chip ID\n");
	201	return -EINVAL;
	202	}
	203
1c703225	204	drv_data->num_clks = num_clks;
8ad313fe LD	205	drv_data->max_clk_data = devm_kcalloc(dev, num_clks,
	206	sizeof(*drv_data->max_clk_data),
	207	GFP_KERNEL);
	208	if (!drv_data->max_clk_data)
	209	return -ENOMEM;
	210
8ad313fe LD	211	for (i = 0; i < num_clks; i++) {
8ad313fe LD	212	struct max77686_clk_init_data *max_clk_data;
8ad313fe LD	213	const char *clk_name;
	214
	215	max_clk_data = &drv_data->max_clk_data[i];
	216
	217	max_clk_data->regmap = regmap;
	218	max_clk_data->clk_info = &hw_clks[i];
	219	max_clk_data->clk_idata.flags = hw_clks[i].flags;
	220	max_clk_data->clk_idata.ops = &max77686_clk_ops;
	221
	222	if (parent->of_node &&
	223	!of_property_read_string_index(parent->of_node,
	224	"clock-output-names",
	225	i, &clk_name))
	226	max_clk_data->clk_idata.name = clk_name;
	227	else
	228	max_clk_data->clk_idata.name = hw_clks[i].name;
	229
	230	max_clk_data->hw.init = &max_clk_data->clk_idata;
	231
9b4cac33 SB	232	ret = devm_clk_hw_register(dev, &max_clk_data->hw);
9b4cac33 SB	233	if (ret) {
8ad313fe LD	234	dev_err(dev, "Failed to clock register: %d\n", ret);
	235	return ret;
	236	}
	237
8144e1e8 MV	238	ret = devm_clk_hw_register_clkdev(dev, &max_clk_data->hw,
	239	max_clk_data->clk_idata.name,
	240	NULL);
8ad313fe LD	241	if (ret < 0) {
	242	dev_err(dev, "Failed to clkdev register: %d\n", ret);
	243	return ret;
	244	}
8ad313fe LD	245	}
8ad313fe LD	246
8ad313fe	247	if (parent->of_node) {
8144e1e8 MV	248	ret = devm_of_clk_add_hw_provider(dev, of_clk_max77686_get,
8144e1e8 MV	249	drv_data);
8ad313fe LD	250
	251	if (ret < 0) {
	252	dev_err(dev, "Failed to register OF clock provider: %d\n",
	253	ret);
	254	return ret;
	255	}
	256	}
	257
	258	/* MAX77802: Enable low-jitter mode on the 32khz clocks. */
	259	if (drv_data->chip == CHIP_MAX77802) {
	260	ret = regmap_update_bits(regmap, MAX77802_REG_32KHZ,
	261	1 << MAX77802_CLOCK_LOW_JITTER_SHIFT,
	262	1 << MAX77802_CLOCK_LOW_JITTER_SHIFT);
	263	if (ret < 0) {
	264	dev_err(dev, "Failed to config low-jitter: %d\n", ret);
8144e1e8	265	return ret;
8ad313fe LD	266	}
	267	}
	268
	269	return 0;
73118e61 JL	270	}
	271
	272	static const struct platform_device_id max77686_clk_id[] = {
8ad313fe LD	273	{ "max77686-clk", .driver_data = CHIP_MAX77686, },
8ad313fe LD	274	{ "max77802-clk", .driver_data = CHIP_MAX77802, },
5a227cd1	275	{ "max77620-clock", .driver_data = CHIP_MAX77620, },
8ad313fe	276	{},
73118e61 JL	277	};
	278	MODULE_DEVICE_TABLE(platform, max77686_clk_id);
	279
	280	static struct platform_driver max77686_clk_driver = {
	281	.driver = {
	282	.name = "max77686-clk",
73118e61 JL	283	},
73118e61 JL	284	.probe = max77686_clk_probe,
73118e61 JL	285	.id_table = max77686_clk_id,
	286	};
	287
1887d693	288	module_platform_driver(max77686_clk_driver);
73118e61 JL	289
	290	MODULE_DESCRIPTION("MAXIM 77686 Clock Driver");
	291	MODULE_AUTHOR("Jonghwa Lee <jonghwa3.lee@samsung.com>");
	292	MODULE_LICENSE("GPL");