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Merge tag 'u-boot-rockchip-20190809' of https://gitlab.denx.de/u-boot/custodians...
[thirdparty/u-boot.git] / drivers / clk / clk_fixed_rate.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
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2/*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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4 */
5
6#include <common.h>
135aa950 7#include <clk-uclass.h>
9d922450 8#include <dm.h>
4f305bf1 9#include <linux/clk-provider.h>
b21e20b2 10
135aa950 11static ulong clk_fixed_rate_get_rate(struct clk *clk)
b21e20b2 12{
135aa950 13 return to_clk_fixed_rate(clk->dev)->fixed_rate;
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14}
15
16const struct clk_ops clk_fixed_rate_ops = {
17 .get_rate = clk_fixed_rate_get_rate,
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18};
19
20static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
21{
36bac0a1 22 struct clk *clk = &to_clk_fixed_rate(dev)->clk;
7423daa6 23#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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24 to_clk_fixed_rate(dev)->fixed_rate =
25 dev_read_u32_default(dev, "clock-frequency", 0);
7423daa6 26#endif
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27 /* Make fixed rate clock accessible from higher level struct clk */
28 dev->uclass_priv = clk;
29 clk->dev = dev;
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30
31 return 0;
32}
33
34static const struct udevice_id clk_fixed_rate_match[] = {
35 {
36 .compatible = "fixed-clock",
37 },
38 { /* sentinel */ }
39};
40
41U_BOOT_DRIVER(clk_fixed_rate) = {
42 .name = "fixed_rate_clock",
43 .id = UCLASS_CLK,
44 .of_match = clk_fixed_rate_match,
45 .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
46 .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
47 .ops = &clk_fixed_rate_ops,
48};