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b21e20b2 MY |
1 | /* |
2 | * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
135aa950 | 8 | #include <clk-uclass.h> |
b21e20b2 MY |
9 | #include <dm/device.h> |
10 | ||
11 | DECLARE_GLOBAL_DATA_PTR; | |
12 | ||
13 | struct clk_fixed_rate { | |
14 | unsigned long fixed_rate; | |
15 | }; | |
16 | ||
17 | #define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev)) | |
18 | ||
135aa950 | 19 | static ulong clk_fixed_rate_get_rate(struct clk *clk) |
b21e20b2 | 20 | { |
135aa950 SW |
21 | if (clk->id != 0) |
22 | return -EINVAL; | |
b21e20b2 | 23 | |
135aa950 | 24 | return to_clk_fixed_rate(clk->dev)->fixed_rate; |
b21e20b2 MY |
25 | } |
26 | ||
27 | const struct clk_ops clk_fixed_rate_ops = { | |
28 | .get_rate = clk_fixed_rate_get_rate, | |
b21e20b2 MY |
29 | }; |
30 | ||
31 | static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) | |
32 | { | |
33 | to_clk_fixed_rate(dev)->fixed_rate = | |
34 | fdtdec_get_int(gd->fdt_blob, dev->of_offset, | |
35 | "clock-frequency", 0); | |
36 | ||
37 | return 0; | |
38 | } | |
39 | ||
40 | static const struct udevice_id clk_fixed_rate_match[] = { | |
41 | { | |
42 | .compatible = "fixed-clock", | |
43 | }, | |
44 | { /* sentinel */ } | |
45 | }; | |
46 | ||
47 | U_BOOT_DRIVER(clk_fixed_rate) = { | |
48 | .name = "fixed_rate_clock", | |
49 | .id = UCLASS_CLK, | |
50 | .of_match = clk_fixed_rate_match, | |
51 | .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata, | |
52 | .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate), | |
53 | .ops = &clk_fixed_rate_ops, | |
54 | }; |