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clk: convert API to match reset/mailbox style
[people/ms/u-boot.git] / drivers / clk / clk_rk3288.c
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99c15650
SG		 1/*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
135aa950 8#include <clk-uclass.h>
99c15650
SG		 9#include <dm.h>
10#include <errno.h>
11#include <syscon.h>
12#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/cru_rk3288.h>
15#include <asm/arch/grf_rk3288.h>
16#include <asm/arch/hardware.h>
898d6439 17#include <dt-bindings/clock/rk3288-cru.h>
64b7faa7 18#include <dm/device-internal.h>
99c15650 19#include <dm/lists.h>
64b7faa7 20#include <dm/uclass-internal.h>
99c15650
SG		 21
22DECLARE_GLOBAL_DATA_PTR;
23
99c15650
SG		 24struct rk3288_clk_priv {
25 struct rk3288_grf *grf;
26 struct rk3288_cru *cru;
27 ulong rate;
28};
29
30struct pll_div {
31 u32 nr;
32 u32 nf;
33 u32 no;
34};
35
36enum {
37 VCO_MAX_HZ = 2200U * 1000000,
38 VCO_MIN_HZ = 440 * 1000000,
39 OUTPUT_MAX_HZ = 2200U * 1000000,
40 OUTPUT_MIN_HZ = 27500000,
41 FREF_MAX_HZ = 2200U * 1000000,
42 FREF_MIN_HZ = 269 * 1000000,
43};
44
45enum {
46 /* PLL CON0 */
47 PLL_OD_MASK = 0x0f,
48
49 /* PLL CON1 */
50 PLL_NF_MASK = 0x1fff,
51
52 /* PLL CON2 */
53 PLL_BWADJ_MASK = 0x0fff,
54
55 /* PLL CON3 */
56 PLL_RESET_SHIFT = 5,
57
dae594f2
SG		 58 /* CLKSEL0 */
59 CORE_SEL_PLL_MASK = 1,
60 CORE_SEL_PLL_SHIFT = 15,
61 A17_DIV_MASK = 0x1f,
62 A17_DIV_SHIFT = 8,
63 MP_DIV_MASK = 0xf,
64 MP_DIV_SHIFT = 4,
65 M0_DIV_MASK = 0xf,
66 M0_DIV_SHIFT = 0,
67
99c15650
SG		 68 /* CLKSEL1: pd bus clk pll sel: codec or general */
69 PD_BUS_SEL_PLL_MASK = 15,
70 PD_BUS_SEL_CPLL = 0,
71 PD_BUS_SEL_GPLL,
72
73 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
74 PD_BUS_PCLK_DIV_SHIFT = 12,
75 PD_BUS_PCLK_DIV_MASK = 7,
76
77 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
78 PD_BUS_HCLK_DIV_SHIFT = 8,
79 PD_BUS_HCLK_DIV_MASK = 3,
80
81 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
82 PD_BUS_ACLK_DIV0_SHIFT = 3,
83 PD_BUS_ACLK_DIV0_MASK = 0x1f,
84 PD_BUS_ACLK_DIV1_SHIFT = 0,
85 PD_BUS_ACLK_DIV1_MASK = 0x7,
86
87 /*
88 * CLKSEL10
89 * peripheral bus pclk div:
90 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
91 */
c87c129f
SG		 92 PERI_SEL_PLL_MASK = 1,
93 PERI_SEL_PLL_SHIFT = 15,
94 PERI_SEL_CPLL = 0,
95 PERI_SEL_GPLL,
96
99c15650 97 PERI_PCLK_DIV_SHIFT = 12,
c87c129f 98 PERI_PCLK_DIV_MASK = 3,
99c15650
SG		 99
100 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
101 PERI_HCLK_DIV_SHIFT = 8,
102 PERI_HCLK_DIV_MASK = 3,
103
104 /*
105 * peripheral bus aclk div:
106 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
107 */
108 PERI_ACLK_DIV_SHIFT = 0,
109 PERI_ACLK_DIV_MASK = 0x1f,
110
99c15650
SG		 111 SOCSTS_DPLL_LOCK = 1 << 5,
112 SOCSTS_APLL_LOCK = 1 << 6,
113 SOCSTS_CPLL_LOCK = 1 << 7,
114 SOCSTS_GPLL_LOCK = 1 << 8,
115 SOCSTS_NPLL_LOCK = 1 << 9,
116};
117
118#define RATE_TO_DIV(input_rate, output_rate) \
119 ((input_rate) / (output_rate) - 1);
120
121#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
122
123#define PLL_DIVISORS(hz, _nr, _no) {\
124 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
125 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
126 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
127 "divisors on line " __stringify(__LINE__));
128
129/* Keep divisors as low as possible to reduce jitter and power usage */
130static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
131static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
132static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
133
5ddf5d77
SG		 134void *rockchip_get_cru(void)
135{
136 struct rk3288_clk_priv *priv;
137 struct udevice *dev;
138 int ret;
139
135aa950 140 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
5ddf5d77
SG		 141 if (ret)
142 return ERR_PTR(ret);
135aa950 143
5ddf5d77 144 priv = dev_get_priv(dev);
135aa950 145
5ddf5d77
SG		 146 return priv->cru;
147}
148
99c15650
SG		 149static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
150 const struct pll_div *div)
151{
152 int pll_id = rk_pll_id(clk_id);
153 struct rk3288_pll *pll = &cru->pll[pll_id];
154 /* All PLLs have same VCO and output frequency range restrictions. */
155 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
156 uint output_hz = vco_hz / div->no;
157
c87c129f
SG		 158 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
159 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
99c15650
SG		 160 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
161 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
162 (div->no == 1 || !(div->no % 2)));
163
c87c129f 164 /* enter reset */
99c15650
SG		 165 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
166
167 rk_clrsetreg(&pll->con0,
168 CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
169 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
170 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
171 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
172
173 udelay(10);
174
c87c129f 175 /* return from reset */
99c15650
SG		 176 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
177
178 return 0;
179}
180
181static inline unsigned int log2(unsigned int value)
182{
183 return fls(value) - 1;
184}
185
186static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
187 unsigned int hz)
188{
189 static const struct pll_div dpll_cfg[] = {
190 {.nf = 25, .nr = 2, .no = 1},
191 {.nf = 400, .nr = 9, .no = 2},
192 {.nf = 500, .nr = 9, .no = 2},
193 {.nf = 100, .nr = 3, .no = 1},
194 };
195 int cfg;
196
99c15650
SG		 197 switch (hz) {
198 case 300000000:
199 cfg = 0;
200 break;
201 case 533000000: /* actually 533.3P MHz */
202 cfg = 1;
203 break;
204 case 666000000: /* actually 666.6P MHz */
205 cfg = 2;
206 break;
207 case 800000000:
208 cfg = 3;
209 break;
210 default:
c87c129f 211 debug("Unsupported SDRAM frequency");
99c15650
SG		 212 return -EINVAL;
213 }
214
215 /* pll enter slow-mode */
216 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
217 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
218
219 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
220
221 /* wait for pll lock */
222 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
223 udelay(1);
224
225 /* PLL enter normal-mode */
226 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
009741fb 227 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
99c15650
SG		 228
229 return 0;
230}
231
830a6081
SG		 232#ifndef CONFIG_SPL_BUILD
233#define VCO_MAX_KHZ 2200000
234#define VCO_MIN_KHZ 440000
235#define FREF_MAX_KHZ 2200000
236#define FREF_MIN_KHZ 269
237
238static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
239{
240 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
241 uint fref_khz;
242 uint diff_khz, best_diff_khz;
243 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
244 uint vco_khz;
245 uint no = 1;
246 uint freq_khz = freq_hz / 1000;
247
248 if (!freq_hz) {
249 printf("%s: the frequency can not be 0 Hz\n", __func__);
250 return -EINVAL;
251 }
252
253 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
254 if (ext_div) {
255 *ext_div = DIV_ROUND_UP(no, max_no);
256 no = DIV_ROUND_UP(no, *ext_div);
257 }
258
259 /* only even divisors (and 1) are supported */
260 if (no > 1)
261 no = DIV_ROUND_UP(no, 2) * 2;
262
263 vco_khz = freq_khz * no;
264 if (ext_div)
265 vco_khz *= *ext_div;
266
267 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
268 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
269 __func__, freq_hz);
270 return -1;
271 }
272
273 div->no = no;
274
275 best_diff_khz = vco_khz;
276 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
277 fref_khz = ref_khz / nr;
278 if (fref_khz < FREF_MIN_KHZ)
279 break;
280 if (fref_khz > FREF_MAX_KHZ)
281 continue;
282
283 nf = vco_khz / fref_khz;
284 if (nf >= max_nf)
285 continue;
286 diff_khz = vco_khz - nf * fref_khz;
287 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
288 nf++;
289 diff_khz = fref_khz - diff_khz;
290 }
291
292 if (diff_khz >= best_diff_khz)
293 continue;
294
295 best_diff_khz = diff_khz;
296 div->nr = nr;
297 div->nf = nf;
298 }
299
300 if (best_diff_khz > 4 * 1000) {
301 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
302 __func__, freq_hz, best_diff_khz * 1000);
303 return -EINVAL;
304 }
305
306 return 0;
307}
308
0aefc0b0
SS		 309static int rockchip_mac_set_clk(struct rk3288_cru *cru,
310 int periph, uint freq)
311{
312 /* Assuming mac_clk is fed by an external clock */
313 rk_clrsetreg(&cru->cru_clksel_con[21],
314 RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
315 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
316
317 return 0;
318}
319
830a6081
SG		 320static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
321 int periph, unsigned int rate_hz)
322{
323 struct pll_div npll_config = {0};
324 u32 lcdc_div;
325 int ret;
326
327 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
328 if (ret)
329 return ret;
330
331 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
332 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
333 rkclk_set_pll(cru, CLK_NEW, &npll_config);
334
335 /* waiting for pll lock */
336 while (1) {
337 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
338 break;
339 udelay(1);
340 }
341
342 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
343 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
344
345 /* vop dclk source clk: npll,dclk_div: 1 */
346 switch (periph) {
347 case DCLK_VOP0:
348 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
349 (lcdc_div - 1) << 8 | 2 << 0);
350 break;
351 case DCLK_VOP1:
352 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
353 (lcdc_div - 1) << 8 | 2 << 6);
354 break;
355 }
356
357 return 0;
358}
359#endif
360
99c15650
SG		 361#ifdef CONFIG_SPL_BUILD
362static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
363{
364 u32 aclk_div;
365 u32 hclk_div;
366 u32 pclk_div;
367
368 /* pll enter slow-mode */
369 rk_clrsetreg(&cru->cru_mode_con,
370 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
371 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
372 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
373 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
374
375 /* init pll */
376 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
377 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
378
379 /* waiting for pll lock */
380 while ((readl(&grf->soc_status[1]) &
381 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
382 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
383 udelay(1);
384
385 /*
386 * pd_bus clock pll source selection and
387 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
388 */
389 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
390 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
391 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
392 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
393 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
394
395 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
396 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
397 PD_BUS_ACLK_HZ && pclk_div < 0x7);
398
399 rk_clrsetreg(&cru->cru_clksel_con[1],
400 PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
401 PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
402 PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
403 PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
404 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
405 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
406 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
407 0 << 0);
408
409 /*
410 * peri clock pll source selection and
411 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
412 */
413 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
414 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
415
416 hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
417 assert((1 << hclk_div) * PERI_HCLK_HZ ==
418 PERI_ACLK_HZ && (hclk_div < 0x4));
419
420 pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
421 assert((1 << pclk_div) * PERI_PCLK_HZ ==
422 PERI_ACLK_HZ && (pclk_div < 0x4));
423
424 rk_clrsetreg(&cru->cru_clksel_con[10],
425 PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
426 PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
427 PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
c87c129f 428 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
99c15650
SG		 429 pclk_div << PERI_PCLK_DIV_SHIFT |
430 hclk_div << PERI_HCLK_DIV_SHIFT |
431 aclk_div << PERI_ACLK_DIV_SHIFT);
432
433 /* PLL enter normal-mode */
434 rk_clrsetreg(&cru->cru_mode_con,
435 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
436 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
009741fb
SG		 437 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
438 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
99c15650
SG		 439}
440#endif
441
dae594f2
SG		 442void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
443{
444 /* pll enter slow-mode */
445 rk_clrsetreg(&cru->cru_mode_con,
446 APLL_MODE_MASK << APLL_MODE_SHIFT,
447 APLL_MODE_SLOW << APLL_MODE_SHIFT);
448
449 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
450
451 /* waiting for pll lock */
452 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
453 udelay(1);
454
455 /*
456 * core clock pll source selection and
457 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
458 * core clock select apll, apll clk = 1800MHz
459 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
460 */
461 rk_clrsetreg(&cru->cru_clksel_con[0],
462 CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
463 A17_DIV_MASK << A17_DIV_SHIFT |
464 MP_DIV_MASK << MP_DIV_SHIFT |
465 M0_DIV_MASK << M0_DIV_SHIFT,
466 0 << A17_DIV_SHIFT |
467 3 << MP_DIV_SHIFT |
468 1 << M0_DIV_SHIFT);
469
470 /*
471 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
472 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
473 */
474 rk_clrsetreg(&cru->cru_clksel_con[37],
475 CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
476 ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
477 PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
478 1 << CLK_L2RAM_DIV_SHIFT |
479 3 << ATCLK_CORE_DIV_CON_SHIFT |
480 3 << PCLK_CORE_DBG_DIV_SHIFT);
481
482 /* PLL enter normal-mode */
483 rk_clrsetreg(&cru->cru_mode_con,
484 APLL_MODE_MASK << APLL_MODE_SHIFT,
485 APLL_MODE_NORMAL << APLL_MODE_SHIFT);
486}
487
99c15650
SG		 488/* Get pll rate by id */
489static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
490 enum rk_clk_id clk_id)
491{
492 uint32_t nr, no, nf;
493 uint32_t con;
494 int pll_id = rk_pll_id(clk_id);
495 struct rk3288_pll *pll = &cru->pll[pll_id];
496 static u8 clk_shift[CLK_COUNT] = {
009741fb
SG		 497 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
498 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
99c15650
SG		 499 };
500 uint shift;
501
502 con = readl(&cru->cru_mode_con);
503 shift = clk_shift[clk_id];
009741fb
SG		 504 switch ((con >> shift) & APLL_MODE_MASK) {
505 case APLL_MODE_SLOW:
99c15650 506 return OSC_HZ;
009741fb 507 case APLL_MODE_NORMAL:
99c15650
SG		 508 /* normal mode */
509 con = readl(&pll->con0);
510 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
511 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
512 con = readl(&pll->con1);
513 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
514
515 return (24 * nf / (nr * no)) * 1000000;
009741fb 516 case APLL_MODE_DEEP:
99c15650
SG		 517 default:
518 return 32768;
519 }
520}
521
542635a0 522static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
898d6439 523 int periph)
99c15650
SG		 524{
525 uint src_rate;
526 uint div, mux;
527 u32 con;
528
529 switch (periph) {
898d6439 530 case HCLK_EMMC:
99c15650
SG		 531 con = readl(&cru->cru_clksel_con[12]);
532 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
533 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
534 break;
898d6439
SG		 535 case HCLK_SDMMC:
536 con = readl(&cru->cru_clksel_con[11]);
99c15650
SG		 537 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
538 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
539 break;
898d6439 540 case HCLK_SDIO0:
99c15650
SG		 541 con = readl(&cru->cru_clksel_con[12]);
542 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
543 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
544 break;
545 default:
546 return -EINVAL;
547 }
548
542635a0 549 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
99c15650
SG		 550 return DIV_TO_RATE(src_rate, div);
551}
552
542635a0 553static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
898d6439 554 int periph, uint freq)
99c15650
SG		 555{
556 int src_clk_div;
557 int mux;
558
542635a0
SG		 559 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
560 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
99c15650
SG		 561
562 if (src_clk_div > 0x3f) {
563 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
564 mux = EMMC_PLL_SELECT_24MHZ;
565 assert((int)EMMC_PLL_SELECT_24MHZ ==
566 (int)MMC0_PLL_SELECT_24MHZ);
567 } else {
568 mux = EMMC_PLL_SELECT_GENERAL;
569 assert((int)EMMC_PLL_SELECT_GENERAL ==
570 (int)MMC0_PLL_SELECT_GENERAL);
571 }
572 switch (periph) {
898d6439 573 case HCLK_EMMC:
99c15650
SG		 574 rk_clrsetreg(&cru->cru_clksel_con[12],
575 EMMC_PLL_MASK << EMMC_PLL_SHIFT |
576 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
577 mux << EMMC_PLL_SHIFT |
578 (src_clk_div - 1) << EMMC_DIV_SHIFT);
579 break;
898d6439 580 case HCLK_SDMMC:
99c15650
SG		 581 rk_clrsetreg(&cru->cru_clksel_con[11],
582 MMC0_PLL_MASK << MMC0_PLL_SHIFT |
583 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
584 mux << MMC0_PLL_SHIFT |
585 (src_clk_div - 1) << MMC0_DIV_SHIFT);
586 break;
898d6439 587 case HCLK_SDIO0:
99c15650
SG		 588 rk_clrsetreg(&cru->cru_clksel_con[12],
589 SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
590 SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
591 mux << SDIO0_PLL_SHIFT |
592 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
593 break;
594 default:
595 return -EINVAL;
596 }
597
542635a0 598 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
99c15650
SG		 599}
600
542635a0 601static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
898d6439 602 int periph)
99c15650
SG		 603{
604 uint div, mux;
605 u32 con;
606
607 switch (periph) {
898d6439 608 case SCLK_SPI0:
99c15650
SG		 609 con = readl(&cru->cru_clksel_con[25]);
610 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
611 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
612 break;
898d6439 613 case SCLK_SPI1:
99c15650
SG		 614 con = readl(&cru->cru_clksel_con[25]);
615 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
616 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
617 break;
898d6439 618 case SCLK_SPI2:
99c15650
SG		 619 con = readl(&cru->cru_clksel_con[39]);
620 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
621 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
622 break;
623 default:
624 return -EINVAL;
625 }
626 assert(mux == SPI0_PLL_SELECT_GENERAL);
627
542635a0 628 return DIV_TO_RATE(gclk_rate, div);
99c15650
SG		 629}
630
542635a0 631static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
898d6439 632 int periph, uint freq)
99c15650
SG		 633{
634 int src_clk_div;
635
542635a0
SG		 636 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
637 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
99c15650 638 switch (periph) {
898d6439 639 case SCLK_SPI0:
99c15650
SG		 640 rk_clrsetreg(&cru->cru_clksel_con[25],
641 SPI0_PLL_MASK << SPI0_PLL_SHIFT |
642 SPI0_DIV_MASK << SPI0_DIV_SHIFT,
643 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
644 src_clk_div << SPI0_DIV_SHIFT);
645 break;
898d6439 646 case SCLK_SPI1:
99c15650
SG		 647 rk_clrsetreg(&cru->cru_clksel_con[25],
648 SPI1_PLL_MASK << SPI1_PLL_SHIFT |
649 SPI1_DIV_MASK << SPI1_DIV_SHIFT,
650 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
651 src_clk_div << SPI1_DIV_SHIFT);
652 break;
898d6439 653 case SCLK_SPI2:
99c15650
SG		 654 rk_clrsetreg(&cru->cru_clksel_con[39],
655 SPI2_PLL_MASK << SPI2_PLL_SHIFT |
656 SPI2_DIV_MASK << SPI2_DIV_SHIFT,
657 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
658 src_clk_div << SPI2_DIV_SHIFT);
659 break;
660 default:
661 return -EINVAL;
662 }
663
542635a0 664 return rockchip_spi_get_clk(cru, gclk_rate, periph);
99c15650
SG		 665}
666
135aa950 667static ulong rk3288_clk_get_rate(struct clk *clk)
4f43673e 668{
135aa950 669 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
4f43673e 670 ulong new_rate, gclk_rate;
4f43673e 671
135aa950
SW		 672 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
673 switch (clk->id) {
674 case 0 ... 63:
675 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
676 break;
4f43673e 677 case HCLK_EMMC:
342999f9 678 case HCLK_SDMMC:
4f43673e 679 case HCLK_SDIO0:
135aa950 680 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
4f43673e
SG		 681 break;
682 case SCLK_SPI0:
683 case SCLK_SPI1:
684 case SCLK_SPI2:
135aa950 685 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
4f43673e
SG		 686 break;
687 case PCLK_I2C0:
688 case PCLK_I2C1:
689 case PCLK_I2C2:
690 case PCLK_I2C3:
691 case PCLK_I2C4:
692 case PCLK_I2C5:
693 return gclk_rate;
694 default:
695 return -ENOENT;
696 }
697
698 return new_rate;
699}
700
135aa950 701static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
99c15650 702{
135aa950 703 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
830a6081 704 struct rk3288_cru *cru = priv->cru;
898d6439 705 ulong new_rate, gclk_rate;
898d6439 706
135aa950
SW		 707 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
708 switch (clk->id) {
709 case CLK_DDR:
710 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
711 break;
898d6439
SG		 712 case HCLK_EMMC:
713 case HCLK_SDMMC:
714 case HCLK_SDIO0:
135aa950 715 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
99c15650 716 break;
898d6439
SG		 717 case SCLK_SPI0:
718 case SCLK_SPI1:
719 case SCLK_SPI2:
135aa950 720 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
99c15650 721 break;
830a6081 722#ifndef CONFIG_SPL_BUILD
0aefc0b0 723 case SCLK_MAC:
135aa950 724 new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
0aefc0b0 725 break;
830a6081
SG		 726 case DCLK_VOP0:
727 case DCLK_VOP1:
135aa950 728 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
830a6081
SG		 729 break;
730 case SCLK_EDP_24M:
731 /* clk_edp_24M source: 24M */
732 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
733
734 /* rst edp */
735 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
736 udelay(1);
737 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
738 new_rate = rate;
739 break;
740 case ACLK_VOP0:
741 case ACLK_VOP1: {
742 u32 div;
743
744 /* vop aclk source clk: cpll */
745 div = CPLL_HZ / rate;
746 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
747
135aa950 748 switch (clk->id) {
830a6081
SG		 749 case ACLK_VOP0:
750 rk_clrsetreg(&cru->cru_clksel_con[31],
751 3 << 6 | 0x1f << 0,
752 0 << 6 | (div - 1) << 0);
753 break;
754 case ACLK_VOP1:
755 rk_clrsetreg(&cru->cru_clksel_con[31],
756 3 << 14 | 0x1f << 8,
757 0 << 14 | (div - 1) << 8);
758 break;
759 }
760 new_rate = rate;
761 break;
762 }
763 case PCLK_HDMI_CTRL:
764 /* enable pclk hdmi ctrl */
765 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
766
767 /* software reset hdmi */
768 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
769 udelay(1);
770 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
771 new_rate = rate;
772 break;
773#endif
99c15650
SG		 774 default:
775 return -ENOENT;
776 }
777
778 return new_rate;
779}
780
781static struct clk_ops rk3288_clk_ops = {
782 .get_rate = rk3288_clk_get_rate,
783 .set_rate = rk3288_clk_set_rate,
99c15650
SG		 784};
785
786static int rk3288_clk_probe(struct udevice *dev)
787{
99c15650
SG		 788 struct rk3288_clk_priv *priv = dev_get_priv(dev);
789
99c15650
SG		 790 priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
791 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
792#ifdef CONFIG_SPL_BUILD
793 rkclk_init(priv->cru, priv->grf);
794#endif
795
796 return 0;
797}
798
99c15650
SG		 799static int rk3288_clk_bind(struct udevice *dev)
800{
135aa950 801 int ret;
99c15650
SG		 802
803 /* The reset driver does not have a device node, so bind it here */
11636258 804 ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
99c15650
SG		 805 if (ret)
806 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
807
808 return 0;
809}
810
811static const struct udevice_id rk3288_clk_ids[] = {
812 { .compatible = "rockchip,rk3288-cru" },
813 { }
814};
815
816U_BOOT_DRIVER(clk_rk3288) = {
817 .name = "clk_rk3288",
818 .id = UCLASS_CLK,
819 .of_match = rk3288_clk_ids,
820 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
99c15650
SG		 821 .ops = &rk3288_clk_ops,
822 .bind = rk3288_clk_bind,
823 .probe = rk3288_clk_probe,
824};
"Das U-Boot" Source Tree