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4549e789 | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
a6151916 PD |
2 | /* |
3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved | |
a6151916 PD |
4 | */ |
5 | ||
6 | #include <common.h> | |
7 | #include <clk-uclass.h> | |
8 | #include <div64.h> | |
9 | #include <dm.h> | |
10 | #include <regmap.h> | |
11 | #include <spl.h> | |
12 | #include <syscon.h> | |
1045315d | 13 | #include <time.h> |
2189d5f1 | 14 | #include <vsprintf.h> |
a6151916 | 15 | #include <linux/io.h> |
266fa4df | 16 | #include <linux/iopoll.h> |
a6151916 | 17 | #include <dt-bindings/clock/stm32mp1-clks.h> |
266fa4df PD |
18 | #include <dt-bindings/clock/stm32mp1-clksrc.h> |
19 | ||
4de076ed PD |
20 | DECLARE_GLOBAL_DATA_PTR; |
21 | ||
654706be | 22 | #ifndef CONFIG_TFABOOT |
266fa4df PD |
23 | #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) |
24 | /* activate clock tree initialization in the driver */ | |
25 | #define STM32MP1_CLOCK_TREE_INIT | |
26 | #endif | |
abf2678f | 27 | #endif |
a6151916 PD |
28 | |
29 | #define MAX_HSI_HZ 64000000 | |
30 | ||
266fa4df PD |
31 | /* TIMEOUT */ |
32 | #define TIMEOUT_200MS 200000 | |
33 | #define TIMEOUT_1S 1000000 | |
34 | ||
938e0e3f PD |
35 | /* STGEN registers */ |
36 | #define STGENC_CNTCR 0x00 | |
37 | #define STGENC_CNTSR 0x04 | |
38 | #define STGENC_CNTCVL 0x08 | |
39 | #define STGENC_CNTCVU 0x0C | |
40 | #define STGENC_CNTFID0 0x20 | |
41 | ||
42 | #define STGENC_CNTCR_EN BIT(0) | |
43 | ||
a6151916 PD |
44 | /* RCC registers */ |
45 | #define RCC_OCENSETR 0x0C | |
46 | #define RCC_OCENCLRR 0x10 | |
47 | #define RCC_HSICFGR 0x18 | |
48 | #define RCC_MPCKSELR 0x20 | |
49 | #define RCC_ASSCKSELR 0x24 | |
50 | #define RCC_RCK12SELR 0x28 | |
51 | #define RCC_MPCKDIVR 0x2C | |
52 | #define RCC_AXIDIVR 0x30 | |
53 | #define RCC_APB4DIVR 0x3C | |
54 | #define RCC_APB5DIVR 0x40 | |
55 | #define RCC_RTCDIVR 0x44 | |
56 | #define RCC_MSSCKSELR 0x48 | |
57 | #define RCC_PLL1CR 0x80 | |
58 | #define RCC_PLL1CFGR1 0x84 | |
59 | #define RCC_PLL1CFGR2 0x88 | |
60 | #define RCC_PLL1FRACR 0x8C | |
61 | #define RCC_PLL1CSGR 0x90 | |
62 | #define RCC_PLL2CR 0x94 | |
63 | #define RCC_PLL2CFGR1 0x98 | |
64 | #define RCC_PLL2CFGR2 0x9C | |
65 | #define RCC_PLL2FRACR 0xA0 | |
66 | #define RCC_PLL2CSGR 0xA4 | |
67 | #define RCC_I2C46CKSELR 0xC0 | |
68 | #define RCC_CPERCKSELR 0xD0 | |
69 | #define RCC_STGENCKSELR 0xD4 | |
70 | #define RCC_DDRITFCR 0xD8 | |
71 | #define RCC_BDCR 0x140 | |
72 | #define RCC_RDLSICR 0x144 | |
73 | #define RCC_MP_APB4ENSETR 0x200 | |
74 | #define RCC_MP_APB5ENSETR 0x208 | |
75 | #define RCC_MP_AHB5ENSETR 0x210 | |
76 | #define RCC_MP_AHB6ENSETR 0x218 | |
77 | #define RCC_OCRDYR 0x808 | |
78 | #define RCC_DBGCFGR 0x80C | |
79 | #define RCC_RCK3SELR 0x820 | |
80 | #define RCC_RCK4SELR 0x824 | |
81 | #define RCC_MCUDIVR 0x830 | |
82 | #define RCC_APB1DIVR 0x834 | |
83 | #define RCC_APB2DIVR 0x838 | |
84 | #define RCC_APB3DIVR 0x83C | |
85 | #define RCC_PLL3CR 0x880 | |
86 | #define RCC_PLL3CFGR1 0x884 | |
87 | #define RCC_PLL3CFGR2 0x888 | |
88 | #define RCC_PLL3FRACR 0x88C | |
89 | #define RCC_PLL3CSGR 0x890 | |
90 | #define RCC_PLL4CR 0x894 | |
91 | #define RCC_PLL4CFGR1 0x898 | |
92 | #define RCC_PLL4CFGR2 0x89C | |
93 | #define RCC_PLL4FRACR 0x8A0 | |
94 | #define RCC_PLL4CSGR 0x8A4 | |
95 | #define RCC_I2C12CKSELR 0x8C0 | |
96 | #define RCC_I2C35CKSELR 0x8C4 | |
248278d7 | 97 | #define RCC_SPI2S1CKSELR 0x8D8 |
0c90e0cf | 98 | #define RCC_SPI45CKSELR 0x8E0 |
a6151916 PD |
99 | #define RCC_UART6CKSELR 0x8E4 |
100 | #define RCC_UART24CKSELR 0x8E8 | |
101 | #define RCC_UART35CKSELR 0x8EC | |
102 | #define RCC_UART78CKSELR 0x8F0 | |
103 | #define RCC_SDMMC12CKSELR 0x8F4 | |
104 | #define RCC_SDMMC3CKSELR 0x8F8 | |
105 | #define RCC_ETHCKSELR 0x8FC | |
106 | #define RCC_QSPICKSELR 0x900 | |
107 | #define RCC_FMCCKSELR 0x904 | |
108 | #define RCC_USBCKSELR 0x91C | |
88fa34df | 109 | #define RCC_DSICKSELR 0x924 |
5b25eb9f | 110 | #define RCC_ADCCKSELR 0x928 |
a6151916 PD |
111 | #define RCC_MP_APB1ENSETR 0xA00 |
112 | #define RCC_MP_APB2ENSETR 0XA08 | |
f198bbac | 113 | #define RCC_MP_APB3ENSETR 0xA10 |
a6151916 | 114 | #define RCC_MP_AHB2ENSETR 0xA18 |
283bcd9a | 115 | #define RCC_MP_AHB3ENSETR 0xA20 |
a6151916 PD |
116 | #define RCC_MP_AHB4ENSETR 0xA28 |
117 | ||
118 | /* used for most of SELR register */ | |
119 | #define RCC_SELR_SRC_MASK GENMASK(2, 0) | |
120 | #define RCC_SELR_SRCRDY BIT(31) | |
121 | ||
122 | /* Values of RCC_MPCKSELR register */ | |
123 | #define RCC_MPCKSELR_HSI 0 | |
124 | #define RCC_MPCKSELR_HSE 1 | |
125 | #define RCC_MPCKSELR_PLL 2 | |
126 | #define RCC_MPCKSELR_PLL_MPUDIV 3 | |
127 | ||
128 | /* Values of RCC_ASSCKSELR register */ | |
129 | #define RCC_ASSCKSELR_HSI 0 | |
130 | #define RCC_ASSCKSELR_HSE 1 | |
131 | #define RCC_ASSCKSELR_PLL 2 | |
132 | ||
133 | /* Values of RCC_MSSCKSELR register */ | |
134 | #define RCC_MSSCKSELR_HSI 0 | |
135 | #define RCC_MSSCKSELR_HSE 1 | |
136 | #define RCC_MSSCKSELR_CSI 2 | |
137 | #define RCC_MSSCKSELR_PLL 3 | |
138 | ||
139 | /* Values of RCC_CPERCKSELR register */ | |
140 | #define RCC_CPERCKSELR_HSI 0 | |
141 | #define RCC_CPERCKSELR_CSI 1 | |
142 | #define RCC_CPERCKSELR_HSE 2 | |
143 | ||
144 | /* used for most of DIVR register : max div for RTC */ | |
145 | #define RCC_DIVR_DIV_MASK GENMASK(5, 0) | |
146 | #define RCC_DIVR_DIVRDY BIT(31) | |
147 | ||
148 | /* Masks for specific DIVR registers */ | |
149 | #define RCC_APBXDIV_MASK GENMASK(2, 0) | |
150 | #define RCC_MPUDIV_MASK GENMASK(2, 0) | |
151 | #define RCC_AXIDIV_MASK GENMASK(2, 0) | |
152 | #define RCC_MCUDIV_MASK GENMASK(3, 0) | |
153 | ||
154 | /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ | |
155 | #define RCC_MP_ENCLRR_OFFSET 4 | |
156 | ||
157 | /* Fields of RCC_BDCR register */ | |
158 | #define RCC_BDCR_LSEON BIT(0) | |
159 | #define RCC_BDCR_LSEBYP BIT(1) | |
160 | #define RCC_BDCR_LSERDY BIT(2) | |
d2194155 | 161 | #define RCC_BDCR_DIGBYP BIT(3) |
a6151916 PD |
162 | #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) |
163 | #define RCC_BDCR_LSEDRV_SHIFT 4 | |
164 | #define RCC_BDCR_LSECSSON BIT(8) | |
165 | #define RCC_BDCR_RTCCKEN BIT(20) | |
166 | #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) | |
167 | #define RCC_BDCR_RTCSRC_SHIFT 16 | |
168 | ||
169 | /* Fields of RCC_RDLSICR register */ | |
170 | #define RCC_RDLSICR_LSION BIT(0) | |
171 | #define RCC_RDLSICR_LSIRDY BIT(1) | |
172 | ||
173 | /* used for ALL PLLNCR registers */ | |
174 | #define RCC_PLLNCR_PLLON BIT(0) | |
175 | #define RCC_PLLNCR_PLLRDY BIT(1) | |
bbd108a0 | 176 | #define RCC_PLLNCR_SSCG_CTRL BIT(2) |
a6151916 PD |
177 | #define RCC_PLLNCR_DIVPEN BIT(4) |
178 | #define RCC_PLLNCR_DIVQEN BIT(5) | |
179 | #define RCC_PLLNCR_DIVREN BIT(6) | |
180 | #define RCC_PLLNCR_DIVEN_SHIFT 4 | |
181 | ||
182 | /* used for ALL PLLNCFGR1 registers */ | |
183 | #define RCC_PLLNCFGR1_DIVM_SHIFT 16 | |
184 | #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) | |
185 | #define RCC_PLLNCFGR1_DIVN_SHIFT 0 | |
186 | #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) | |
187 | /* only for PLL3 and PLL4 */ | |
188 | #define RCC_PLLNCFGR1_IFRGE_SHIFT 24 | |
189 | #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) | |
190 | ||
c2fa5dc8 PD |
191 | /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */ |
192 | #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8) | |
a6151916 | 193 | #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) |
c2fa5dc8 | 194 | #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P) |
a6151916 | 195 | #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) |
c2fa5dc8 | 196 | #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q) |
a6151916 | 197 | #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) |
c2fa5dc8 | 198 | #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R) |
a6151916 PD |
199 | #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) |
200 | ||
201 | /* used for ALL PLLNFRACR registers */ | |
202 | #define RCC_PLLNFRACR_FRACV_SHIFT 3 | |
203 | #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) | |
204 | #define RCC_PLLNFRACR_FRACLE BIT(16) | |
205 | ||
206 | /* used for ALL PLLNCSGR registers */ | |
207 | #define RCC_PLLNCSGR_INC_STEP_SHIFT 16 | |
208 | #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) | |
209 | #define RCC_PLLNCSGR_MOD_PER_SHIFT 0 | |
210 | #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) | |
211 | #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 | |
212 | #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) | |
213 | ||
214 | /* used for RCC_OCENSETR and RCC_OCENCLRR registers */ | |
215 | #define RCC_OCENR_HSION BIT(0) | |
216 | #define RCC_OCENR_CSION BIT(4) | |
d2194155 | 217 | #define RCC_OCENR_DIGBYP BIT(7) |
a6151916 PD |
218 | #define RCC_OCENR_HSEON BIT(8) |
219 | #define RCC_OCENR_HSEBYP BIT(10) | |
220 | #define RCC_OCENR_HSECSSON BIT(11) | |
221 | ||
222 | /* Fields of RCC_OCRDYR register */ | |
223 | #define RCC_OCRDYR_HSIRDY BIT(0) | |
224 | #define RCC_OCRDYR_HSIDIVRDY BIT(2) | |
225 | #define RCC_OCRDYR_CSIRDY BIT(4) | |
226 | #define RCC_OCRDYR_HSERDY BIT(8) | |
227 | ||
228 | /* Fields of DDRITFCR register */ | |
229 | #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) | |
230 | #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 | |
231 | #define RCC_DDRITFCR_DDRCKMOD_SSR 0 | |
232 | ||
233 | /* Fields of RCC_HSICFGR register */ | |
234 | #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) | |
235 | ||
236 | /* used for MCO related operations */ | |
237 | #define RCC_MCOCFG_MCOON BIT(12) | |
238 | #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) | |
239 | #define RCC_MCOCFG_MCODIV_SHIFT 4 | |
240 | #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) | |
241 | ||
242 | enum stm32mp1_parent_id { | |
243 | /* | |
244 | * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved | |
245 | * they are used as index in osc[] as entry point | |
246 | */ | |
247 | _HSI, | |
248 | _HSE, | |
249 | _CSI, | |
250 | _LSI, | |
251 | _LSE, | |
252 | _I2S_CKIN, | |
a6151916 PD |
253 | NB_OSC, |
254 | ||
255 | /* other parent source */ | |
256 | _HSI_KER = NB_OSC, | |
257 | _HSE_KER, | |
258 | _HSE_KER_DIV2, | |
259 | _CSI_KER, | |
260 | _PLL1_P, | |
261 | _PLL1_Q, | |
262 | _PLL1_R, | |
263 | _PLL2_P, | |
264 | _PLL2_Q, | |
265 | _PLL2_R, | |
266 | _PLL3_P, | |
267 | _PLL3_Q, | |
268 | _PLL3_R, | |
269 | _PLL4_P, | |
270 | _PLL4_Q, | |
271 | _PLL4_R, | |
272 | _ACLK, | |
273 | _PCLK1, | |
274 | _PCLK2, | |
275 | _PCLK3, | |
276 | _PCLK4, | |
277 | _PCLK5, | |
278 | _HCLK6, | |
279 | _HCLK2, | |
280 | _CK_PER, | |
281 | _CK_MPU, | |
282 | _CK_MCU, | |
88fa34df | 283 | _DSI_PHY, |
86617dd1 | 284 | _USB_PHY_48, |
a6151916 PD |
285 | _PARENT_NB, |
286 | _UNKNOWN_ID = 0xff, | |
287 | }; | |
288 | ||
289 | enum stm32mp1_parent_sel { | |
290 | _I2C12_SEL, | |
291 | _I2C35_SEL, | |
292 | _I2C46_SEL, | |
293 | _UART6_SEL, | |
294 | _UART24_SEL, | |
295 | _UART35_SEL, | |
296 | _UART78_SEL, | |
297 | _SDMMC12_SEL, | |
298 | _SDMMC3_SEL, | |
299 | _ETH_SEL, | |
300 | _QSPI_SEL, | |
301 | _FMC_SEL, | |
302 | _USBPHY_SEL, | |
303 | _USBO_SEL, | |
304 | _STGEN_SEL, | |
88fa34df | 305 | _DSI_SEL, |
5b25eb9f | 306 | _ADC12_SEL, |
248278d7 | 307 | _SPI1_SEL, |
0c90e0cf | 308 | _SPI45_SEL, |
fd7fe1bb | 309 | _RTC_SEL, |
a6151916 PD |
310 | _PARENT_SEL_NB, |
311 | _UNKNOWN_SEL = 0xff, | |
312 | }; | |
313 | ||
314 | enum stm32mp1_pll_id { | |
315 | _PLL1, | |
316 | _PLL2, | |
317 | _PLL3, | |
318 | _PLL4, | |
319 | _PLL_NB | |
320 | }; | |
321 | ||
322 | enum stm32mp1_div_id { | |
323 | _DIV_P, | |
324 | _DIV_Q, | |
325 | _DIV_R, | |
326 | _DIV_NB, | |
327 | }; | |
328 | ||
329 | enum stm32mp1_clksrc_id { | |
330 | CLKSRC_MPU, | |
331 | CLKSRC_AXI, | |
332 | CLKSRC_MCU, | |
333 | CLKSRC_PLL12, | |
334 | CLKSRC_PLL3, | |
335 | CLKSRC_PLL4, | |
336 | CLKSRC_RTC, | |
337 | CLKSRC_MCO1, | |
338 | CLKSRC_MCO2, | |
339 | CLKSRC_NB | |
340 | }; | |
341 | ||
342 | enum stm32mp1_clkdiv_id { | |
343 | CLKDIV_MPU, | |
344 | CLKDIV_AXI, | |
345 | CLKDIV_MCU, | |
346 | CLKDIV_APB1, | |
347 | CLKDIV_APB2, | |
348 | CLKDIV_APB3, | |
349 | CLKDIV_APB4, | |
350 | CLKDIV_APB5, | |
351 | CLKDIV_RTC, | |
352 | CLKDIV_MCO1, | |
353 | CLKDIV_MCO2, | |
354 | CLKDIV_NB | |
355 | }; | |
356 | ||
357 | enum stm32mp1_pllcfg { | |
358 | PLLCFG_M, | |
359 | PLLCFG_N, | |
360 | PLLCFG_P, | |
361 | PLLCFG_Q, | |
362 | PLLCFG_R, | |
363 | PLLCFG_O, | |
364 | PLLCFG_NB | |
365 | }; | |
366 | ||
367 | enum stm32mp1_pllcsg { | |
368 | PLLCSG_MOD_PER, | |
369 | PLLCSG_INC_STEP, | |
370 | PLLCSG_SSCG_MODE, | |
371 | PLLCSG_NB | |
372 | }; | |
373 | ||
374 | enum stm32mp1_plltype { | |
375 | PLL_800, | |
376 | PLL_1600, | |
377 | PLL_TYPE_NB | |
378 | }; | |
379 | ||
380 | struct stm32mp1_pll { | |
381 | u8 refclk_min; | |
382 | u8 refclk_max; | |
383 | u8 divn_max; | |
384 | }; | |
385 | ||
386 | struct stm32mp1_clk_gate { | |
387 | u16 offset; | |
388 | u8 bit; | |
389 | u8 index; | |
390 | u8 set_clr; | |
391 | u8 sel; | |
392 | u8 fixed; | |
393 | }; | |
394 | ||
395 | struct stm32mp1_clk_sel { | |
396 | u16 offset; | |
397 | u8 src; | |
398 | u8 msk; | |
399 | u8 nb_parent; | |
400 | const u8 *parent; | |
401 | }; | |
402 | ||
403 | #define REFCLK_SIZE 4 | |
404 | struct stm32mp1_clk_pll { | |
405 | enum stm32mp1_plltype plltype; | |
406 | u16 rckxselr; | |
407 | u16 pllxcfgr1; | |
408 | u16 pllxcfgr2; | |
409 | u16 pllxfracr; | |
410 | u16 pllxcr; | |
411 | u16 pllxcsgr; | |
412 | u8 refclk[REFCLK_SIZE]; | |
413 | }; | |
414 | ||
415 | struct stm32mp1_clk_data { | |
416 | const struct stm32mp1_clk_gate *gate; | |
417 | const struct stm32mp1_clk_sel *sel; | |
418 | const struct stm32mp1_clk_pll *pll; | |
419 | const int nb_gate; | |
420 | }; | |
421 | ||
422 | struct stm32mp1_clk_priv { | |
423 | fdt_addr_t base; | |
424 | const struct stm32mp1_clk_data *data; | |
425 | ulong osc[NB_OSC]; | |
426 | struct udevice *osc_dev[NB_OSC]; | |
427 | }; | |
428 | ||
429 | #define STM32MP1_CLK(off, b, idx, s) \ | |
430 | { \ | |
431 | .offset = (off), \ | |
432 | .bit = (b), \ | |
433 | .index = (idx), \ | |
434 | .set_clr = 0, \ | |
435 | .sel = (s), \ | |
436 | .fixed = _UNKNOWN_ID, \ | |
437 | } | |
438 | ||
439 | #define STM32MP1_CLK_F(off, b, idx, f) \ | |
440 | { \ | |
441 | .offset = (off), \ | |
442 | .bit = (b), \ | |
443 | .index = (idx), \ | |
444 | .set_clr = 0, \ | |
445 | .sel = _UNKNOWN_SEL, \ | |
446 | .fixed = (f), \ | |
447 | } | |
448 | ||
449 | #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ | |
450 | { \ | |
451 | .offset = (off), \ | |
452 | .bit = (b), \ | |
453 | .index = (idx), \ | |
454 | .set_clr = 1, \ | |
455 | .sel = (s), \ | |
456 | .fixed = _UNKNOWN_ID, \ | |
457 | } | |
458 | ||
459 | #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ | |
460 | { \ | |
461 | .offset = (off), \ | |
462 | .bit = (b), \ | |
463 | .index = (idx), \ | |
464 | .set_clr = 1, \ | |
465 | .sel = _UNKNOWN_SEL, \ | |
466 | .fixed = (f), \ | |
467 | } | |
468 | ||
469 | #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \ | |
470 | [(idx)] = { \ | |
471 | .offset = (off), \ | |
472 | .src = (s), \ | |
473 | .msk = (m), \ | |
474 | .parent = (p), \ | |
475 | .nb_parent = ARRAY_SIZE((p)) \ | |
476 | } | |
477 | ||
478 | #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\ | |
479 | p1, p2, p3, p4) \ | |
480 | [(idx)] = { \ | |
481 | .plltype = (type), \ | |
482 | .rckxselr = (off1), \ | |
483 | .pllxcfgr1 = (off2), \ | |
484 | .pllxcfgr2 = (off3), \ | |
485 | .pllxfracr = (off4), \ | |
486 | .pllxcr = (off5), \ | |
487 | .pllxcsgr = (off6), \ | |
488 | .refclk[0] = (p1), \ | |
489 | .refclk[1] = (p2), \ | |
490 | .refclk[2] = (p3), \ | |
491 | .refclk[3] = (p4), \ | |
492 | } | |
493 | ||
494 | static const u8 stm32mp1_clks[][2] = { | |
495 | {CK_PER, _CK_PER}, | |
496 | {CK_MPU, _CK_MPU}, | |
497 | {CK_AXI, _ACLK}, | |
498 | {CK_MCU, _CK_MCU}, | |
499 | {CK_HSE, _HSE}, | |
500 | {CK_CSI, _CSI}, | |
501 | {CK_LSI, _LSI}, | |
502 | {CK_LSE, _LSE}, | |
503 | {CK_HSI, _HSI}, | |
504 | {CK_HSE_DIV2, _HSE_KER_DIV2}, | |
505 | }; | |
506 | ||
507 | static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { | |
508 | STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), | |
509 | STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), | |
510 | STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), | |
511 | STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), | |
512 | STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), | |
513 | STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), | |
514 | STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), | |
515 | STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), | |
516 | STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), | |
517 | STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), | |
518 | STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), | |
519 | ||
520 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), | |
521 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), | |
522 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), | |
523 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), | |
524 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), | |
525 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), | |
526 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), | |
527 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), | |
528 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), | |
529 | STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), | |
530 | ||
248278d7 | 531 | STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL), |
0c90e0cf | 532 | STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL), |
a6151916 PD |
533 | STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), |
534 | ||
f198bbac FG |
535 | STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3), |
536 | ||
88fa34df PD |
537 | STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q), |
538 | STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q), | |
539 | STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL), | |
a6151916 PD |
540 | STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), |
541 | STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), | |
542 | STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), | |
543 | ||
544 | STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), | |
fd7fe1bb | 545 | STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), |
a6151916 PD |
546 | STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), |
547 | ||
5b25eb9f PD |
548 | STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2), |
549 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL), | |
a6151916 PD |
550 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), |
551 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), | |
552 | ||
283bcd9a | 553 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), |
d661f618 | 554 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL), |
283bcd9a | 555 | |
a6151916 PD |
556 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), |
557 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), | |
558 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), | |
559 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), | |
560 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), | |
561 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), | |
562 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), | |
563 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), | |
564 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), | |
565 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), | |
566 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), | |
567 | ||
568 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), | |
82ebf0f6 | 569 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL), |
a6151916 | 570 | |
f6ccdda1 | 571 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL), |
a6151916 PD |
572 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL), |
573 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL), | |
a6151916 PD |
574 | STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK), |
575 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), | |
576 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), | |
577 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), | |
578 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), | |
579 | STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), | |
580 | ||
581 | STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), | |
fd7fe1bb PD |
582 | |
583 | STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL), | |
a6151916 PD |
584 | }; |
585 | ||
586 | static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; | |
587 | static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; | |
588 | static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; | |
589 | static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, | |
590 | _HSE_KER}; | |
591 | static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, | |
592 | _HSE_KER}; | |
593 | static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, | |
594 | _HSE_KER}; | |
595 | static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, | |
596 | _HSE_KER}; | |
597 | static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; | |
598 | static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; | |
599 | static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q}; | |
600 | static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; | |
601 | static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; | |
602 | static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; | |
603 | static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48}; | |
604 | static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER}; | |
88fa34df | 605 | static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P}; |
5b25eb9f | 606 | static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q}; |
248278d7 PC |
607 | static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER, |
608 | _PLL3_R}; | |
0c90e0cf PD |
609 | static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, |
610 | _HSE_KER}; | |
fd7fe1bb | 611 | static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE}; |
a6151916 PD |
612 | |
613 | static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { | |
614 | STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents), | |
615 | STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), | |
616 | STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), | |
617 | STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), | |
618 | STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, | |
619 | uart24_parents), | |
620 | STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, | |
621 | uart35_parents), | |
622 | STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, | |
623 | uart78_parents), | |
624 | STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, | |
625 | sdmmc12_parents), | |
626 | STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, | |
627 | sdmmc3_parents), | |
628 | STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents), | |
69ffb557 PD |
629 | STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents), |
630 | STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents), | |
a6151916 PD |
631 | STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), |
632 | STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), | |
633 | STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), | |
88fa34df | 634 | STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents), |
69ffb557 | 635 | STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents), |
248278d7 | 636 | STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents), |
0c90e0cf | 637 | STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents), |
fd7fe1bb PD |
638 | STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT, |
639 | (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT), | |
640 | rtc_parents), | |
a6151916 PD |
641 | }; |
642 | ||
643 | #ifdef STM32MP1_CLOCK_TREE_INIT | |
644 | /* define characteristic of PLL according type */ | |
645 | #define DIVN_MIN 24 | |
646 | static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { | |
647 | [PLL_800] = { | |
648 | .refclk_min = 4, | |
649 | .refclk_max = 16, | |
650 | .divn_max = 99, | |
651 | }, | |
652 | [PLL_1600] = { | |
653 | .refclk_min = 8, | |
654 | .refclk_max = 16, | |
655 | .divn_max = 199, | |
656 | }, | |
657 | }; | |
658 | #endif /* STM32MP1_CLOCK_TREE_INIT */ | |
659 | ||
660 | static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { | |
661 | STM32MP1_CLK_PLL(_PLL1, PLL_1600, | |
662 | RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, | |
663 | RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, | |
664 | _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), | |
665 | STM32MP1_CLK_PLL(_PLL2, PLL_1600, | |
666 | RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, | |
667 | RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, | |
668 | _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), | |
669 | STM32MP1_CLK_PLL(_PLL3, PLL_800, | |
670 | RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, | |
671 | RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, | |
672 | _HSI, _HSE, _CSI, _UNKNOWN_ID), | |
673 | STM32MP1_CLK_PLL(_PLL4, PLL_800, | |
674 | RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, | |
675 | RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, | |
676 | _HSI, _HSE, _CSI, _I2S_CKIN), | |
677 | }; | |
678 | ||
679 | /* Prescaler table lookups for clock computation */ | |
680 | /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ | |
681 | static const u8 stm32mp1_mcu_div[16] = { | |
682 | 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 | |
683 | }; | |
684 | ||
685 | /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/ | |
686 | #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div | |
687 | #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div | |
688 | static const u8 stm32mp1_mpu_apbx_div[8] = { | |
689 | 0, 1, 2, 3, 4, 4, 4, 4 | |
690 | }; | |
691 | ||
692 | /* div = /1 /2 /3 /4 */ | |
693 | static const u8 stm32mp1_axi_div[8] = { | |
694 | 1, 2, 3, 4, 4, 4, 4, 4 | |
695 | }; | |
696 | ||
8d6310aa PD |
697 | static const __maybe_unused |
698 | char * const stm32mp1_clk_parent_name[_PARENT_NB] = { | |
a6151916 PD |
699 | [_HSI] = "HSI", |
700 | [_HSE] = "HSE", | |
701 | [_CSI] = "CSI", | |
702 | [_LSI] = "LSI", | |
703 | [_LSE] = "LSE", | |
704 | [_I2S_CKIN] = "I2S_CKIN", | |
705 | [_HSI_KER] = "HSI_KER", | |
706 | [_HSE_KER] = "HSE_KER", | |
707 | [_HSE_KER_DIV2] = "HSE_KER_DIV2", | |
708 | [_CSI_KER] = "CSI_KER", | |
709 | [_PLL1_P] = "PLL1_P", | |
710 | [_PLL1_Q] = "PLL1_Q", | |
711 | [_PLL1_R] = "PLL1_R", | |
712 | [_PLL2_P] = "PLL2_P", | |
713 | [_PLL2_Q] = "PLL2_Q", | |
714 | [_PLL2_R] = "PLL2_R", | |
715 | [_PLL3_P] = "PLL3_P", | |
716 | [_PLL3_Q] = "PLL3_Q", | |
717 | [_PLL3_R] = "PLL3_R", | |
718 | [_PLL4_P] = "PLL4_P", | |
719 | [_PLL4_Q] = "PLL4_Q", | |
720 | [_PLL4_R] = "PLL4_R", | |
721 | [_ACLK] = "ACLK", | |
722 | [_PCLK1] = "PCLK1", | |
723 | [_PCLK2] = "PCLK2", | |
724 | [_PCLK3] = "PCLK3", | |
725 | [_PCLK4] = "PCLK4", | |
726 | [_PCLK5] = "PCLK5", | |
727 | [_HCLK6] = "KCLK6", | |
728 | [_HCLK2] = "HCLK2", | |
729 | [_CK_PER] = "CK_PER", | |
730 | [_CK_MPU] = "CK_MPU", | |
731 | [_CK_MCU] = "CK_MCU", | |
88fa34df PD |
732 | [_USB_PHY_48] = "USB_PHY_48", |
733 | [_DSI_PHY] = "DSI_PHY_PLL", | |
a6151916 PD |
734 | }; |
735 | ||
8d6310aa PD |
736 | static const __maybe_unused |
737 | char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { | |
a6151916 PD |
738 | [_I2C12_SEL] = "I2C12", |
739 | [_I2C35_SEL] = "I2C35", | |
740 | [_I2C46_SEL] = "I2C46", | |
741 | [_UART6_SEL] = "UART6", | |
742 | [_UART24_SEL] = "UART24", | |
743 | [_UART35_SEL] = "UART35", | |
744 | [_UART78_SEL] = "UART78", | |
745 | [_SDMMC12_SEL] = "SDMMC12", | |
746 | [_SDMMC3_SEL] = "SDMMC3", | |
747 | [_ETH_SEL] = "ETH", | |
748 | [_QSPI_SEL] = "QSPI", | |
749 | [_FMC_SEL] = "FMC", | |
750 | [_USBPHY_SEL] = "USBPHY", | |
751 | [_USBO_SEL] = "USBO", | |
88fa34df PD |
752 | [_STGEN_SEL] = "STGEN", |
753 | [_DSI_SEL] = "DSI", | |
5b25eb9f | 754 | [_ADC12_SEL] = "ADC12", |
248278d7 | 755 | [_SPI1_SEL] = "SPI1", |
0c90e0cf | 756 | [_SPI45_SEL] = "SPI45", |
fd7fe1bb | 757 | [_RTC_SEL] = "RTC", |
a6151916 | 758 | }; |
a6151916 PD |
759 | |
760 | static const struct stm32mp1_clk_data stm32mp1_data = { | |
761 | .gate = stm32mp1_clk_gate, | |
762 | .sel = stm32mp1_clk_sel, | |
763 | .pll = stm32mp1_clk_pll, | |
764 | .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), | |
765 | }; | |
766 | ||
767 | static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) | |
768 | { | |
769 | if (idx >= NB_OSC) { | |
770 | debug("%s: clk id %d not found\n", __func__, idx); | |
771 | return 0; | |
772 | } | |
773 | ||
a6151916 PD |
774 | return priv->osc[idx]; |
775 | } | |
776 | ||
777 | static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) | |
778 | { | |
779 | const struct stm32mp1_clk_gate *gate = priv->data->gate; | |
780 | int i, nb_clks = priv->data->nb_gate; | |
781 | ||
782 | for (i = 0; i < nb_clks; i++) { | |
783 | if (gate[i].index == id) | |
784 | break; | |
785 | } | |
786 | ||
787 | if (i == nb_clks) { | |
788 | printf("%s: clk id %d not found\n", __func__, (u32)id); | |
789 | return -EINVAL; | |
790 | } | |
791 | ||
792 | return i; | |
793 | } | |
794 | ||
795 | static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, | |
796 | int i) | |
797 | { | |
798 | const struct stm32mp1_clk_gate *gate = priv->data->gate; | |
799 | ||
800 | if (gate[i].sel > _PARENT_SEL_NB) { | |
801 | printf("%s: parents for clk id %d not found\n", | |
802 | __func__, i); | |
803 | return -EINVAL; | |
804 | } | |
805 | ||
806 | return gate[i].sel; | |
807 | } | |
808 | ||
809 | static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, | |
810 | int i) | |
811 | { | |
812 | const struct stm32mp1_clk_gate *gate = priv->data->gate; | |
813 | ||
814 | if (gate[i].fixed == _UNKNOWN_ID) | |
815 | return -ENOENT; | |
816 | ||
817 | return gate[i].fixed; | |
818 | } | |
819 | ||
820 | static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, | |
821 | unsigned long id) | |
822 | { | |
823 | const struct stm32mp1_clk_sel *sel = priv->data->sel; | |
824 | int i; | |
825 | int s, p; | |
67d74ce2 | 826 | unsigned int idx; |
a6151916 | 827 | |
67d74ce2 PD |
828 | for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++) |
829 | if (stm32mp1_clks[idx][0] == id) | |
830 | return stm32mp1_clks[idx][1]; | |
a6151916 PD |
831 | |
832 | i = stm32mp1_clk_get_id(priv, id); | |
833 | if (i < 0) | |
834 | return i; | |
835 | ||
836 | p = stm32mp1_clk_get_fixed_parent(priv, i); | |
837 | if (p >= 0 && p < _PARENT_NB) | |
838 | return p; | |
839 | ||
840 | s = stm32mp1_clk_get_sel(priv, i); | |
841 | if (s < 0) | |
842 | return s; | |
843 | ||
844 | p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk; | |
845 | ||
846 | if (p < sel[s].nb_parent) { | |
847 | #ifdef DEBUG | |
848 | debug("%s: %s clock is the parent %s of clk id %d\n", __func__, | |
849 | stm32mp1_clk_parent_name[sel[s].parent[p]], | |
850 | stm32mp1_clk_parent_sel_name[s], | |
851 | (u32)id); | |
852 | #endif | |
853 | return sel[s].parent[p]; | |
854 | } | |
855 | ||
856 | pr_err("%s: no parents defined for clk id %d\n", | |
857 | __func__, (u32)id); | |
858 | ||
859 | return -EINVAL; | |
860 | } | |
861 | ||
6110503f PD |
862 | static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv, |
863 | int pll_id) | |
a6151916 PD |
864 | { |
865 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
6110503f PD |
866 | u32 selr; |
867 | int src; | |
868 | ulong refclk; | |
a6151916 | 869 | |
6110503f | 870 | /* Get current refclk */ |
a6151916 | 871 | selr = readl(priv->base + pll[pll_id].rckxselr); |
6110503f PD |
872 | src = selr & RCC_SELR_SRC_MASK; |
873 | ||
874 | refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); | |
6110503f PD |
875 | |
876 | return refclk; | |
877 | } | |
878 | ||
879 | /* | |
880 | * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL | |
881 | * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) | |
882 | * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) | |
883 | * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1) | |
884 | */ | |
885 | static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv, | |
886 | int pll_id) | |
887 | { | |
888 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
889 | int divm, divn; | |
890 | ulong refclk, fvco; | |
891 | u32 cfgr1, fracr; | |
892 | ||
a6151916 | 893 | cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1); |
a6151916 PD |
894 | fracr = readl(priv->base + pll[pll_id].pllxfracr); |
895 | ||
a6151916 PD |
896 | divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; |
897 | divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; | |
a6151916 | 898 | |
6110503f | 899 | refclk = pll_get_fref_ck(priv, pll_id); |
a6151916 | 900 | |
6110503f PD |
901 | /* with FRACV : |
902 | * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) | |
a6151916 | 903 | * without FRACV |
6110503f | 904 | * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) |
a6151916 PD |
905 | */ |
906 | if (fracr & RCC_PLLNFRACR_FRACLE) { | |
907 | u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) | |
908 | >> RCC_PLLNFRACR_FRACV_SHIFT; | |
6110503f | 909 | fvco = (ulong)lldiv((unsigned long long)refclk * |
a6151916 | 910 | (((divn + 1) << 13) + fracv), |
6110503f | 911 | ((unsigned long long)(divm + 1)) << 13); |
a6151916 | 912 | } else { |
6110503f | 913 | fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); |
a6151916 | 914 | } |
6110503f PD |
915 | |
916 | return fvco; | |
917 | } | |
918 | ||
919 | static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, | |
920 | int pll_id, int div_id) | |
921 | { | |
922 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
923 | int divy; | |
924 | ulong dfout; | |
925 | u32 cfgr2; | |
926 | ||
6110503f PD |
927 | if (div_id >= _DIV_NB) |
928 | return 0; | |
929 | ||
930 | cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); | |
931 | divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK; | |
932 | ||
6110503f | 933 | dfout = pll_get_fvco(priv, pll_id) / (divy + 1); |
a6151916 PD |
934 | |
935 | return dfout; | |
936 | } | |
937 | ||
938 | static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) | |
939 | { | |
940 | u32 reg; | |
941 | ulong clock = 0; | |
942 | ||
943 | switch (p) { | |
944 | case _CK_MPU: | |
945 | /* MPU sub system */ | |
946 | reg = readl(priv->base + RCC_MPCKSELR); | |
947 | switch (reg & RCC_SELR_SRC_MASK) { | |
948 | case RCC_MPCKSELR_HSI: | |
949 | clock = stm32mp1_clk_get_fixed(priv, _HSI); | |
950 | break; | |
951 | case RCC_MPCKSELR_HSE: | |
952 | clock = stm32mp1_clk_get_fixed(priv, _HSE); | |
953 | break; | |
954 | case RCC_MPCKSELR_PLL: | |
955 | case RCC_MPCKSELR_PLL_MPUDIV: | |
956 | clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); | |
957 | if (p == RCC_MPCKSELR_PLL_MPUDIV) { | |
958 | reg = readl(priv->base + RCC_MPCKDIVR); | |
959 | clock /= stm32mp1_mpu_div[reg & | |
960 | RCC_MPUDIV_MASK]; | |
961 | } | |
962 | break; | |
963 | } | |
964 | break; | |
965 | /* AXI sub system */ | |
966 | case _ACLK: | |
967 | case _HCLK2: | |
968 | case _HCLK6: | |
969 | case _PCLK4: | |
970 | case _PCLK5: | |
971 | reg = readl(priv->base + RCC_ASSCKSELR); | |
972 | switch (reg & RCC_SELR_SRC_MASK) { | |
973 | case RCC_ASSCKSELR_HSI: | |
974 | clock = stm32mp1_clk_get_fixed(priv, _HSI); | |
975 | break; | |
976 | case RCC_ASSCKSELR_HSE: | |
977 | clock = stm32mp1_clk_get_fixed(priv, _HSE); | |
978 | break; | |
979 | case RCC_ASSCKSELR_PLL: | |
980 | clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); | |
981 | break; | |
982 | } | |
983 | ||
984 | /* System clock divider */ | |
985 | reg = readl(priv->base + RCC_AXIDIVR); | |
986 | clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; | |
987 | ||
988 | switch (p) { | |
989 | case _PCLK4: | |
990 | reg = readl(priv->base + RCC_APB4DIVR); | |
991 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; | |
992 | break; | |
993 | case _PCLK5: | |
994 | reg = readl(priv->base + RCC_APB5DIVR); | |
995 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; | |
996 | break; | |
997 | default: | |
998 | break; | |
999 | } | |
1000 | break; | |
1001 | /* MCU sub system */ | |
1002 | case _CK_MCU: | |
1003 | case _PCLK1: | |
1004 | case _PCLK2: | |
1005 | case _PCLK3: | |
1006 | reg = readl(priv->base + RCC_MSSCKSELR); | |
1007 | switch (reg & RCC_SELR_SRC_MASK) { | |
1008 | case RCC_MSSCKSELR_HSI: | |
1009 | clock = stm32mp1_clk_get_fixed(priv, _HSI); | |
1010 | break; | |
1011 | case RCC_MSSCKSELR_HSE: | |
1012 | clock = stm32mp1_clk_get_fixed(priv, _HSE); | |
1013 | break; | |
1014 | case RCC_MSSCKSELR_CSI: | |
1015 | clock = stm32mp1_clk_get_fixed(priv, _CSI); | |
1016 | break; | |
1017 | case RCC_MSSCKSELR_PLL: | |
1018 | clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); | |
1019 | break; | |
1020 | } | |
1021 | ||
1022 | /* MCU clock divider */ | |
1023 | reg = readl(priv->base + RCC_MCUDIVR); | |
1024 | clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; | |
1025 | ||
1026 | switch (p) { | |
1027 | case _PCLK1: | |
1028 | reg = readl(priv->base + RCC_APB1DIVR); | |
1029 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; | |
1030 | break; | |
1031 | case _PCLK2: | |
1032 | reg = readl(priv->base + RCC_APB2DIVR); | |
1033 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; | |
1034 | break; | |
1035 | case _PCLK3: | |
1036 | reg = readl(priv->base + RCC_APB3DIVR); | |
1037 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; | |
1038 | break; | |
1039 | case _CK_MCU: | |
1040 | default: | |
1041 | break; | |
1042 | } | |
1043 | break; | |
1044 | case _CK_PER: | |
1045 | reg = readl(priv->base + RCC_CPERCKSELR); | |
1046 | switch (reg & RCC_SELR_SRC_MASK) { | |
1047 | case RCC_CPERCKSELR_HSI: | |
1048 | clock = stm32mp1_clk_get_fixed(priv, _HSI); | |
1049 | break; | |
1050 | case RCC_CPERCKSELR_HSE: | |
1051 | clock = stm32mp1_clk_get_fixed(priv, _HSE); | |
1052 | break; | |
1053 | case RCC_CPERCKSELR_CSI: | |
1054 | clock = stm32mp1_clk_get_fixed(priv, _CSI); | |
1055 | break; | |
1056 | } | |
1057 | break; | |
1058 | case _HSI: | |
1059 | case _HSI_KER: | |
1060 | clock = stm32mp1_clk_get_fixed(priv, _HSI); | |
1061 | break; | |
1062 | case _CSI: | |
1063 | case _CSI_KER: | |
1064 | clock = stm32mp1_clk_get_fixed(priv, _CSI); | |
1065 | break; | |
1066 | case _HSE: | |
1067 | case _HSE_KER: | |
1068 | case _HSE_KER_DIV2: | |
1069 | clock = stm32mp1_clk_get_fixed(priv, _HSE); | |
1070 | if (p == _HSE_KER_DIV2) | |
1071 | clock >>= 1; | |
1072 | break; | |
1073 | case _LSI: | |
1074 | clock = stm32mp1_clk_get_fixed(priv, _LSI); | |
1075 | break; | |
1076 | case _LSE: | |
1077 | clock = stm32mp1_clk_get_fixed(priv, _LSE); | |
1078 | break; | |
1079 | /* PLL */ | |
1080 | case _PLL1_P: | |
1081 | case _PLL1_Q: | |
1082 | case _PLL1_R: | |
1083 | clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P); | |
1084 | break; | |
1085 | case _PLL2_P: | |
1086 | case _PLL2_Q: | |
1087 | case _PLL2_R: | |
1088 | clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P); | |
1089 | break; | |
1090 | case _PLL3_P: | |
1091 | case _PLL3_Q: | |
1092 | case _PLL3_R: | |
1093 | clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P); | |
1094 | break; | |
1095 | case _PLL4_P: | |
1096 | case _PLL4_Q: | |
1097 | case _PLL4_R: | |
1098 | clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P); | |
1099 | break; | |
1100 | /* other */ | |
1101 | case _USB_PHY_48: | |
86617dd1 | 1102 | clock = 48000000; |
a6151916 | 1103 | break; |
88fa34df PD |
1104 | case _DSI_PHY: |
1105 | { | |
1106 | struct clk clk; | |
1107 | struct udevice *dev = NULL; | |
1108 | ||
1109 | if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy", | |
1110 | &dev)) { | |
1111 | if (clk_request(dev, &clk)) { | |
1112 | pr_err("ck_dsi_phy request"); | |
1113 | } else { | |
1114 | clk.id = 0; | |
1115 | clock = clk_get_rate(&clk); | |
1116 | } | |
1117 | } | |
1118 | break; | |
1119 | } | |
a6151916 PD |
1120 | default: |
1121 | break; | |
1122 | } | |
1123 | ||
1124 | debug("%s(%d) clock = %lx : %ld kHz\n", | |
1125 | __func__, p, clock, clock / 1000); | |
1126 | ||
1127 | return clock; | |
1128 | } | |
1129 | ||
1130 | static int stm32mp1_clk_enable(struct clk *clk) | |
1131 | { | |
1132 | struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); | |
1133 | const struct stm32mp1_clk_gate *gate = priv->data->gate; | |
1134 | int i = stm32mp1_clk_get_id(priv, clk->id); | |
1135 | ||
1136 | if (i < 0) | |
1137 | return i; | |
1138 | ||
1139 | if (gate[i].set_clr) | |
1140 | writel(BIT(gate[i].bit), priv->base + gate[i].offset); | |
1141 | else | |
1142 | setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); | |
1143 | ||
1144 | debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id); | |
1145 | ||
1146 | return 0; | |
1147 | } | |
1148 | ||
1149 | static int stm32mp1_clk_disable(struct clk *clk) | |
1150 | { | |
1151 | struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); | |
1152 | const struct stm32mp1_clk_gate *gate = priv->data->gate; | |
1153 | int i = stm32mp1_clk_get_id(priv, clk->id); | |
1154 | ||
1155 | if (i < 0) | |
1156 | return i; | |
1157 | ||
1158 | if (gate[i].set_clr) | |
1159 | writel(BIT(gate[i].bit), | |
1160 | priv->base + gate[i].offset | |
1161 | + RCC_MP_ENCLRR_OFFSET); | |
1162 | else | |
1163 | clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); | |
1164 | ||
1165 | debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id); | |
1166 | ||
1167 | return 0; | |
1168 | } | |
1169 | ||
1170 | static ulong stm32mp1_clk_get_rate(struct clk *clk) | |
1171 | { | |
1172 | struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); | |
1173 | int p = stm32mp1_clk_get_parent(priv, clk->id); | |
1174 | ulong rate; | |
1175 | ||
1176 | if (p < 0) | |
1177 | return 0; | |
1178 | ||
1179 | rate = stm32mp1_clk_get(priv, p); | |
1180 | ||
1181 | #ifdef DEBUG | |
1182 | debug("%s: computed rate for id clock %d is %d (parent is %s)\n", | |
1183 | __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]); | |
1184 | #endif | |
1185 | return rate; | |
1186 | } | |
1187 | ||
266fa4df PD |
1188 | #ifdef STM32MP1_CLOCK_TREE_INIT |
1189 | static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, | |
1190 | u32 mask_on) | |
1191 | { | |
1192 | u32 address = rcc + offset; | |
1193 | ||
1194 | if (enable) | |
1195 | setbits_le32(address, mask_on); | |
1196 | else | |
1197 | clrbits_le32(address, mask_on); | |
1198 | } | |
1199 | ||
1200 | static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) | |
1201 | { | |
63201281 | 1202 | writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); |
266fa4df PD |
1203 | } |
1204 | ||
1205 | static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, | |
1206 | u32 mask_rdy) | |
1207 | { | |
1208 | u32 mask_test = 0; | |
1209 | u32 address = rcc + offset; | |
1210 | u32 val; | |
1211 | int ret; | |
1212 | ||
1213 | if (enable) | |
1214 | mask_test = mask_rdy; | |
1215 | ||
1216 | ret = readl_poll_timeout(address, val, | |
1217 | (val & mask_rdy) == mask_test, | |
1218 | TIMEOUT_1S); | |
1219 | ||
1220 | if (ret) | |
1221 | pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", | |
1222 | mask_rdy, address, enable, readl(address)); | |
1223 | ||
1224 | return ret; | |
1225 | } | |
1226 | ||
d2194155 | 1227 | static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp, |
eb49dce0 | 1228 | u32 lsedrv) |
266fa4df PD |
1229 | { |
1230 | u32 value; | |
1231 | ||
d2194155 PD |
1232 | if (digbyp) |
1233 | setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP); | |
1234 | ||
1235 | if (bypass || digbyp) | |
266fa4df PD |
1236 | setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); |
1237 | ||
1238 | /* | |
1239 | * warning: not recommended to switch directly from "high drive" | |
1240 | * to "medium low drive", and vice-versa. | |
1241 | */ | |
1242 | value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) | |
1243 | >> RCC_BDCR_LSEDRV_SHIFT; | |
1244 | ||
1245 | while (value != lsedrv) { | |
1246 | if (value > lsedrv) | |
1247 | value--; | |
1248 | else | |
1249 | value++; | |
1250 | ||
1251 | clrsetbits_le32(rcc + RCC_BDCR, | |
1252 | RCC_BDCR_LSEDRV_MASK, | |
1253 | value << RCC_BDCR_LSEDRV_SHIFT); | |
1254 | } | |
1255 | ||
1256 | stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); | |
1257 | } | |
1258 | ||
1259 | static void stm32mp1_lse_wait(fdt_addr_t rcc) | |
1260 | { | |
1261 | stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY); | |
1262 | } | |
1263 | ||
1264 | static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable) | |
1265 | { | |
1266 | stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); | |
1267 | stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY); | |
1268 | } | |
1269 | ||
d2194155 | 1270 | static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css) |
266fa4df | 1271 | { |
d2194155 | 1272 | if (digbyp) |
63201281 | 1273 | writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR); |
d2194155 | 1274 | if (bypass || digbyp) |
63201281 | 1275 | writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR); |
266fa4df PD |
1276 | |
1277 | stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); | |
1278 | stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY); | |
1279 | ||
1280 | if (css) | |
63201281 | 1281 | writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR); |
266fa4df PD |
1282 | } |
1283 | ||
1284 | static void stm32mp1_csi_set(fdt_addr_t rcc, int enable) | |
1285 | { | |
63201281 | 1286 | stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION); |
266fa4df PD |
1287 | stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY); |
1288 | } | |
1289 | ||
1290 | static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable) | |
1291 | { | |
1292 | stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); | |
1293 | stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY); | |
1294 | } | |
1295 | ||
1296 | static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv) | |
1297 | { | |
1298 | u32 address = rcc + RCC_OCRDYR; | |
1299 | u32 val; | |
1300 | int ret; | |
1301 | ||
1302 | clrsetbits_le32(rcc + RCC_HSICFGR, | |
1303 | RCC_HSICFGR_HSIDIV_MASK, | |
1304 | RCC_HSICFGR_HSIDIV_MASK & hsidiv); | |
1305 | ||
1306 | ret = readl_poll_timeout(address, val, | |
1307 | val & RCC_OCRDYR_HSIDIVRDY, | |
1308 | TIMEOUT_200MS); | |
1309 | if (ret) | |
1310 | pr_err("HSIDIV failed @ 0x%x: 0x%x\n", | |
1311 | address, readl(address)); | |
1312 | ||
1313 | return ret; | |
1314 | } | |
1315 | ||
1316 | static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq) | |
1317 | { | |
1318 | u8 hsidiv; | |
1319 | u32 hsidivfreq = MAX_HSI_HZ; | |
1320 | ||
1321 | for (hsidiv = 0; hsidiv < 4; hsidiv++, | |
1322 | hsidivfreq = hsidivfreq / 2) | |
1323 | if (hsidivfreq == hsifreq) | |
1324 | break; | |
1325 | ||
1326 | if (hsidiv == 4) { | |
1327 | pr_err("clk-hsi frequency invalid"); | |
1328 | return -1; | |
1329 | } | |
1330 | ||
1331 | if (hsidiv > 0) | |
1332 | return stm32mp1_set_hsidiv(rcc, hsidiv); | |
1333 | ||
1334 | return 0; | |
1335 | } | |
1336 | ||
1337 | static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) | |
1338 | { | |
1339 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
1340 | ||
bbd108a0 PD |
1341 | clrsetbits_le32(priv->base + pll[pll_id].pllxcr, |
1342 | RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | | |
1343 | RCC_PLLNCR_DIVREN, | |
1344 | RCC_PLLNCR_PLLON); | |
266fa4df PD |
1345 | } |
1346 | ||
1347 | static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) | |
1348 | { | |
1349 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
1350 | u32 pllxcr = priv->base + pll[pll_id].pllxcr; | |
1351 | u32 val; | |
1352 | int ret; | |
1353 | ||
1354 | ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY, | |
1355 | TIMEOUT_200MS); | |
1356 | ||
1357 | if (ret) { | |
1358 | pr_err("PLL%d start failed @ 0x%x: 0x%x\n", | |
1359 | pll_id, pllxcr, readl(pllxcr)); | |
1360 | return ret; | |
1361 | } | |
1362 | ||
1363 | /* start the requested output */ | |
1364 | setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); | |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id) | |
1370 | { | |
1371 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
1372 | u32 pllxcr = priv->base + pll[pll_id].pllxcr; | |
1373 | u32 val; | |
1374 | ||
1375 | /* stop all output */ | |
1376 | clrbits_le32(pllxcr, | |
1377 | RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); | |
1378 | ||
1379 | /* stop PLL */ | |
1380 | clrbits_le32(pllxcr, RCC_PLLNCR_PLLON); | |
1381 | ||
1382 | /* wait PLL stopped */ | |
1383 | return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0, | |
1384 | TIMEOUT_200MS); | |
1385 | } | |
1386 | ||
1387 | static void pll_config_output(struct stm32mp1_clk_priv *priv, | |
1388 | int pll_id, u32 *pllcfg) | |
1389 | { | |
1390 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
1391 | fdt_addr_t rcc = priv->base; | |
1392 | u32 value; | |
1393 | ||
1394 | value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) | |
1395 | & RCC_PLLNCFGR2_DIVP_MASK; | |
1396 | value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) | |
1397 | & RCC_PLLNCFGR2_DIVQ_MASK; | |
1398 | value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) | |
1399 | & RCC_PLLNCFGR2_DIVR_MASK; | |
1400 | writel(value, rcc + pll[pll_id].pllxcfgr2); | |
1401 | } | |
1402 | ||
1403 | static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id, | |
1404 | u32 *pllcfg, u32 fracv) | |
1405 | { | |
1406 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
1407 | fdt_addr_t rcc = priv->base; | |
1408 | enum stm32mp1_plltype type = pll[pll_id].plltype; | |
1409 | int src; | |
1410 | ulong refclk; | |
1411 | u8 ifrge = 0; | |
1412 | u32 value; | |
1413 | ||
1414 | src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK; | |
1415 | ||
1416 | refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) / | |
1417 | (pllcfg[PLLCFG_M] + 1); | |
1418 | ||
1419 | if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) || | |
1420 | refclk > (stm32mp1_pll[type].refclk_max * 1000000)) { | |
1421 | debug("invalid refclk = %x\n", (u32)refclk); | |
1422 | return -EINVAL; | |
1423 | } | |
1424 | if (type == PLL_800 && refclk >= 8000000) | |
1425 | ifrge = 1; | |
1426 | ||
1427 | value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) | |
1428 | & RCC_PLLNCFGR1_DIVN_MASK; | |
1429 | value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) | |
1430 | & RCC_PLLNCFGR1_DIVM_MASK; | |
1431 | value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) | |
1432 | & RCC_PLLNCFGR1_IFRGE_MASK; | |
1433 | writel(value, rcc + pll[pll_id].pllxcfgr1); | |
1434 | ||
1435 | /* fractional configuration: load sigma-delta modulator (SDM) */ | |
1436 | ||
1437 | /* Write into FRACV the new fractional value , and FRACLE to 0 */ | |
1438 | writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT, | |
1439 | rcc + pll[pll_id].pllxfracr); | |
1440 | ||
1441 | /* Write FRACLE to 1 : FRACV value is loaded into the SDM */ | |
1442 | setbits_le32(rcc + pll[pll_id].pllxfracr, | |
1443 | RCC_PLLNFRACR_FRACLE); | |
1444 | ||
1445 | pll_config_output(priv, pll_id, pllcfg); | |
1446 | ||
1447 | return 0; | |
1448 | } | |
1449 | ||
1450 | static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) | |
1451 | { | |
1452 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
1453 | u32 pllxcsg; | |
1454 | ||
1455 | pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & | |
1456 | RCC_PLLNCSGR_MOD_PER_MASK) | | |
1457 | ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & | |
1458 | RCC_PLLNCSGR_INC_STEP_MASK) | | |
1459 | ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & | |
1460 | RCC_PLLNCSGR_SSCG_MODE_MASK); | |
1461 | ||
1462 | writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); | |
bbd108a0 PD |
1463 | |
1464 | setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL); | |
266fa4df PD |
1465 | } |
1466 | ||
c3e828bf PD |
1467 | static __maybe_unused int pll_set_rate(struct udevice *dev, |
1468 | int pll_id, | |
1469 | int div_id, | |
1470 | unsigned long clk_rate) | |
1471 | { | |
1472 | struct stm32mp1_clk_priv *priv = dev_get_priv(dev); | |
1473 | unsigned int pllcfg[PLLCFG_NB]; | |
1474 | ofnode plloff; | |
1475 | char name[12]; | |
1476 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
1477 | enum stm32mp1_plltype type = pll[pll_id].plltype; | |
1478 | int divm, divn, divy; | |
1479 | int ret; | |
1480 | ulong fck_ref; | |
1481 | u32 fracv; | |
1482 | u64 value; | |
1483 | ||
1484 | if (div_id > _DIV_NB) | |
1485 | return -EINVAL; | |
1486 | ||
1487 | sprintf(name, "st,pll@%d", pll_id); | |
1488 | plloff = dev_read_subnode(dev, name); | |
1489 | if (!ofnode_valid(plloff)) | |
1490 | return -FDT_ERR_NOTFOUND; | |
1491 | ||
1492 | ret = ofnode_read_u32_array(plloff, "cfg", | |
1493 | pllcfg, PLLCFG_NB); | |
1494 | if (ret < 0) | |
1495 | return -FDT_ERR_NOTFOUND; | |
1496 | ||
1497 | fck_ref = pll_get_fref_ck(priv, pll_id); | |
1498 | ||
1499 | divm = pllcfg[PLLCFG_M]; | |
1500 | /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */ | |
1501 | divy = pllcfg[PLLCFG_P + div_id]; | |
1502 | ||
1503 | /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2 | |
1504 | * So same final result than PLL2 et 4 | |
1505 | * with FRACV | |
1506 | * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13) | |
1507 | * / (DIVy + 1) * (DIVM + 1) | |
1508 | * value = (DIVN + 1) * 2^13 + FRACV / 2^13 | |
1509 | * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref | |
1510 | */ | |
1511 | value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13; | |
1512 | value = lldiv(value, fck_ref); | |
1513 | ||
1514 | divn = (value >> 13) - 1; | |
1515 | if (divn < DIVN_MIN || | |
1516 | divn > stm32mp1_pll[type].divn_max) { | |
1517 | pr_err("divn invalid = %d", divn); | |
1518 | return -EINVAL; | |
1519 | } | |
1520 | fracv = value - ((divn + 1) << 13); | |
1521 | pllcfg[PLLCFG_N] = divn; | |
1522 | ||
1523 | /* reconfigure PLL */ | |
1524 | pll_stop(priv, pll_id); | |
1525 | pll_config(priv, pll_id, pllcfg, fracv); | |
1526 | pll_start(priv, pll_id); | |
1527 | pll_output(priv, pll_id, pllcfg[PLLCFG_O]); | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
266fa4df PD |
1532 | static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) |
1533 | { | |
1534 | u32 address = priv->base + (clksrc >> 4); | |
1535 | u32 val; | |
1536 | int ret; | |
1537 | ||
1538 | clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK); | |
1539 | ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY, | |
1540 | TIMEOUT_200MS); | |
1541 | if (ret) | |
1542 | pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n", | |
1543 | clksrc, address, readl(address)); | |
1544 | ||
1545 | return ret; | |
1546 | } | |
1547 | ||
938e0e3f PD |
1548 | static void stgen_config(struct stm32mp1_clk_priv *priv) |
1549 | { | |
1550 | int p; | |
1551 | u32 stgenc, cntfid0; | |
1552 | ulong rate; | |
1553 | ||
dfda7d4c | 1554 | stgenc = STM32_STGEN_BASE; |
938e0e3f PD |
1555 | cntfid0 = readl(stgenc + STGENC_CNTFID0); |
1556 | p = stm32mp1_clk_get_parent(priv, STGEN_K); | |
1557 | rate = stm32mp1_clk_get(priv, p); | |
1558 | ||
1559 | if (cntfid0 != rate) { | |
f3a23c26 PD |
1560 | u64 counter; |
1561 | ||
938e0e3f PD |
1562 | pr_debug("System Generic Counter (STGEN) update\n"); |
1563 | clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); | |
f3a23c26 PD |
1564 | counter = (u64)readl(stgenc + STGENC_CNTCVL); |
1565 | counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32; | |
1566 | counter = lldiv(counter * (u64)rate, cntfid0); | |
1567 | writel((u32)counter, stgenc + STGENC_CNTCVL); | |
1568 | writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU); | |
938e0e3f PD |
1569 | writel(rate, stgenc + STGENC_CNTFID0); |
1570 | setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); | |
1571 | ||
1572 | __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate)); | |
1573 | ||
1574 | /* need to update gd->arch.timer_rate_hz with new frequency */ | |
1575 | timer_init(); | |
938e0e3f PD |
1576 | } |
1577 | } | |
1578 | ||
266fa4df PD |
1579 | static int set_clkdiv(unsigned int clkdiv, u32 address) |
1580 | { | |
1581 | u32 val; | |
1582 | int ret; | |
1583 | ||
1584 | clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK); | |
1585 | ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY, | |
1586 | TIMEOUT_200MS); | |
1587 | if (ret) | |
1588 | pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n", | |
1589 | clkdiv, address, readl(address)); | |
1590 | ||
1591 | return ret; | |
1592 | } | |
1593 | ||
1594 | static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, | |
1595 | u32 clksrc, u32 clkdiv) | |
1596 | { | |
1597 | u32 address = priv->base + (clksrc >> 4); | |
1598 | ||
1599 | /* | |
1600 | * binding clksrc : bit15-4 offset | |
1601 | * bit3: disable | |
1602 | * bit2-0: MCOSEL[2:0] | |
1603 | */ | |
1604 | if (clksrc & 0x8) { | |
1605 | clrbits_le32(address, RCC_MCOCFG_MCOON); | |
1606 | } else { | |
1607 | clrsetbits_le32(address, | |
1608 | RCC_MCOCFG_MCOSRC_MASK, | |
1609 | clksrc & RCC_MCOCFG_MCOSRC_MASK); | |
1610 | clrsetbits_le32(address, | |
1611 | RCC_MCOCFG_MCODIV_MASK, | |
1612 | clkdiv << RCC_MCOCFG_MCODIV_SHIFT); | |
1613 | setbits_le32(address, RCC_MCOCFG_MCOON); | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | static void set_rtcsrc(struct stm32mp1_clk_priv *priv, | |
1618 | unsigned int clksrc, | |
1619 | int lse_css) | |
1620 | { | |
1621 | u32 address = priv->base + RCC_BDCR; | |
1622 | ||
1623 | if (readl(address) & RCC_BDCR_RTCCKEN) | |
1624 | goto skip_rtc; | |
1625 | ||
1626 | if (clksrc == CLK_RTC_DISABLED) | |
1627 | goto skip_rtc; | |
1628 | ||
1629 | clrsetbits_le32(address, | |
1630 | RCC_BDCR_RTCSRC_MASK, | |
1631 | clksrc << RCC_BDCR_RTCSRC_SHIFT); | |
1632 | ||
1633 | setbits_le32(address, RCC_BDCR_RTCCKEN); | |
1634 | ||
1635 | skip_rtc: | |
1636 | if (lse_css) | |
1637 | setbits_le32(address, RCC_BDCR_LSECSSON); | |
1638 | } | |
1639 | ||
1640 | static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs) | |
1641 | { | |
1642 | u32 address = priv->base + ((pkcs >> 4) & 0xFFF); | |
1643 | u32 value = pkcs & 0xF; | |
1644 | u32 mask = 0xF; | |
1645 | ||
1646 | if (pkcs & BIT(31)) { | |
1647 | mask <<= 4; | |
1648 | value <<= 4; | |
1649 | } | |
1650 | clrsetbits_le32(address, mask, value); | |
1651 | } | |
1652 | ||
1653 | static int stm32mp1_clktree(struct udevice *dev) | |
1654 | { | |
1655 | struct stm32mp1_clk_priv *priv = dev_get_priv(dev); | |
1656 | fdt_addr_t rcc = priv->base; | |
1657 | unsigned int clksrc[CLKSRC_NB]; | |
1658 | unsigned int clkdiv[CLKDIV_NB]; | |
1659 | unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; | |
1660 | ofnode plloff[_PLL_NB]; | |
eb49dce0 PD |
1661 | int ret, len; |
1662 | uint i; | |
266fa4df PD |
1663 | int lse_css = 0; |
1664 | const u32 *pkcs_cell; | |
1665 | ||
1666 | /* check mandatory field */ | |
1667 | ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB); | |
1668 | if (ret < 0) { | |
1669 | debug("field st,clksrc invalid: error %d\n", ret); | |
1670 | return -FDT_ERR_NOTFOUND; | |
1671 | } | |
1672 | ||
1673 | ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB); | |
1674 | if (ret < 0) { | |
1675 | debug("field st,clkdiv invalid: error %d\n", ret); | |
1676 | return -FDT_ERR_NOTFOUND; | |
1677 | } | |
1678 | ||
1679 | /* check mandatory field in each pll */ | |
1680 | for (i = 0; i < _PLL_NB; i++) { | |
1681 | char name[12]; | |
1682 | ||
1683 | sprintf(name, "st,pll@%d", i); | |
1684 | plloff[i] = dev_read_subnode(dev, name); | |
1685 | if (!ofnode_valid(plloff[i])) | |
1686 | continue; | |
1687 | ret = ofnode_read_u32_array(plloff[i], "cfg", | |
1688 | pllcfg[i], PLLCFG_NB); | |
1689 | if (ret < 0) { | |
1690 | debug("field cfg invalid: error %d\n", ret); | |
1691 | return -FDT_ERR_NOTFOUND; | |
1692 | } | |
1693 | } | |
1694 | ||
1695 | debug("configuration MCO\n"); | |
1696 | stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); | |
1697 | stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); | |
1698 | ||
1699 | debug("switch ON osillator\n"); | |
1700 | /* | |
1701 | * switch ON oscillator found in device-tree, | |
1702 | * HSI already ON after bootrom | |
1703 | */ | |
1704 | if (priv->osc[_LSI]) | |
1705 | stm32mp1_lsi_set(rcc, 1); | |
1706 | ||
1707 | if (priv->osc[_LSE]) { | |
eb49dce0 PD |
1708 | int bypass, digbyp; |
1709 | u32 lsedrv; | |
266fa4df PD |
1710 | struct udevice *dev = priv->osc_dev[_LSE]; |
1711 | ||
1712 | bypass = dev_read_bool(dev, "st,bypass"); | |
d2194155 | 1713 | digbyp = dev_read_bool(dev, "st,digbypass"); |
266fa4df PD |
1714 | lse_css = dev_read_bool(dev, "st,css"); |
1715 | lsedrv = dev_read_u32_default(dev, "st,drive", | |
1716 | LSEDRV_MEDIUM_HIGH); | |
1717 | ||
d2194155 | 1718 | stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv); |
266fa4df PD |
1719 | } |
1720 | ||
1721 | if (priv->osc[_HSE]) { | |
d2194155 | 1722 | int bypass, digbyp, css; |
266fa4df PD |
1723 | struct udevice *dev = priv->osc_dev[_HSE]; |
1724 | ||
1725 | bypass = dev_read_bool(dev, "st,bypass"); | |
d2194155 | 1726 | digbyp = dev_read_bool(dev, "st,digbypass"); |
266fa4df PD |
1727 | css = dev_read_bool(dev, "st,css"); |
1728 | ||
d2194155 | 1729 | stm32mp1_hse_enable(rcc, bypass, digbyp, css); |
266fa4df PD |
1730 | } |
1731 | /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) | |
1732 | * => switch on CSI even if node is not present in device tree | |
1733 | */ | |
1734 | stm32mp1_csi_set(rcc, 1); | |
1735 | ||
1736 | /* come back to HSI */ | |
1737 | debug("come back to HSI\n"); | |
1738 | set_clksrc(priv, CLK_MPU_HSI); | |
1739 | set_clksrc(priv, CLK_AXI_HSI); | |
1740 | set_clksrc(priv, CLK_MCU_HSI); | |
1741 | ||
1742 | debug("pll stop\n"); | |
1743 | for (i = 0; i < _PLL_NB; i++) | |
1744 | pll_stop(priv, i); | |
1745 | ||
1746 | /* configure HSIDIV */ | |
1747 | debug("configure HSIDIV\n"); | |
938e0e3f | 1748 | if (priv->osc[_HSI]) { |
266fa4df | 1749 | stm32mp1_hsidiv(rcc, priv->osc[_HSI]); |
938e0e3f PD |
1750 | stgen_config(priv); |
1751 | } | |
266fa4df PD |
1752 | |
1753 | /* select DIV */ | |
1754 | debug("select DIV\n"); | |
1755 | /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ | |
1756 | writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR); | |
1757 | set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); | |
1758 | set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); | |
1759 | set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); | |
1760 | set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR); | |
1761 | set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); | |
1762 | set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); | |
1763 | set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); | |
1764 | ||
1765 | /* no ready bit for RTC */ | |
1766 | writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR); | |
1767 | ||
1768 | /* configure PLLs source */ | |
1769 | debug("configure PLLs source\n"); | |
1770 | set_clksrc(priv, clksrc[CLKSRC_PLL12]); | |
1771 | set_clksrc(priv, clksrc[CLKSRC_PLL3]); | |
1772 | set_clksrc(priv, clksrc[CLKSRC_PLL4]); | |
1773 | ||
1774 | /* configure and start PLLs */ | |
1775 | debug("configure PLLs\n"); | |
1776 | for (i = 0; i < _PLL_NB; i++) { | |
1777 | u32 fracv; | |
1778 | u32 csg[PLLCSG_NB]; | |
1779 | ||
1780 | debug("configure PLL %d @ %d\n", i, | |
1781 | ofnode_to_offset(plloff[i])); | |
1782 | if (!ofnode_valid(plloff[i])) | |
1783 | continue; | |
1784 | ||
1785 | fracv = ofnode_read_u32_default(plloff[i], "frac", 0); | |
1786 | pll_config(priv, i, pllcfg[i], fracv); | |
1787 | ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB); | |
1788 | if (!ret) { | |
1789 | pll_csg(priv, i, csg); | |
1790 | } else if (ret != -FDT_ERR_NOTFOUND) { | |
1791 | debug("invalid csg node for pll@%d res=%d\n", i, ret); | |
1792 | return ret; | |
1793 | } | |
1794 | pll_start(priv, i); | |
1795 | } | |
1796 | ||
1797 | /* wait and start PLLs ouptut when ready */ | |
1798 | for (i = 0; i < _PLL_NB; i++) { | |
1799 | if (!ofnode_valid(plloff[i])) | |
1800 | continue; | |
1801 | debug("output PLL %d\n", i); | |
1802 | pll_output(priv, i, pllcfg[i][PLLCFG_O]); | |
1803 | } | |
1804 | ||
1805 | /* wait LSE ready before to use it */ | |
1806 | if (priv->osc[_LSE]) | |
1807 | stm32mp1_lse_wait(rcc); | |
1808 | ||
1809 | /* configure with expected clock source */ | |
1810 | debug("CLKSRC\n"); | |
1811 | set_clksrc(priv, clksrc[CLKSRC_MPU]); | |
1812 | set_clksrc(priv, clksrc[CLKSRC_AXI]); | |
1813 | set_clksrc(priv, clksrc[CLKSRC_MCU]); | |
1814 | set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); | |
1815 | ||
1816 | /* configure PKCK */ | |
1817 | debug("PKCK\n"); | |
1818 | pkcs_cell = dev_read_prop(dev, "st,pkcs", &len); | |
1819 | if (pkcs_cell) { | |
1820 | bool ckper_disabled = false; | |
1821 | ||
1822 | for (i = 0; i < len / sizeof(u32); i++) { | |
1823 | u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]); | |
1824 | ||
1825 | if (pkcs == CLK_CKPER_DISABLED) { | |
1826 | ckper_disabled = true; | |
1827 | continue; | |
1828 | } | |
1829 | pkcs_config(priv, pkcs); | |
1830 | } | |
1831 | /* CKPER is source for some peripheral clock | |
1832 | * (FMC-NAND / QPSI-NOR) and switching source is allowed | |
1833 | * only if previous clock is still ON | |
1834 | * => deactivated CKPER only after switching clock | |
1835 | */ | |
1836 | if (ckper_disabled) | |
1837 | pkcs_config(priv, CLK_CKPER_DISABLED); | |
1838 | } | |
1839 | ||
938e0e3f PD |
1840 | /* STGEN clock source can change with CLK_STGEN_XXX */ |
1841 | stgen_config(priv); | |
1842 | ||
266fa4df PD |
1843 | debug("oscillator off\n"); |
1844 | /* switch OFF HSI if not found in device-tree */ | |
1845 | if (!priv->osc[_HSI]) | |
1846 | stm32mp1_hsi_set(rcc, 0); | |
1847 | ||
1848 | /* Software Self-Refresh mode (SSR) during DDR initilialization */ | |
1849 | clrsetbits_le32(priv->base + RCC_DDRITFCR, | |
1850 | RCC_DDRITFCR_DDRCKMOD_MASK, | |
1851 | RCC_DDRITFCR_DDRCKMOD_SSR << | |
1852 | RCC_DDRITFCR_DDRCKMOD_SHIFT); | |
1853 | ||
1854 | return 0; | |
1855 | } | |
1856 | #endif /* STM32MP1_CLOCK_TREE_INIT */ | |
1857 | ||
88fa34df PD |
1858 | static int pll_set_output_rate(struct udevice *dev, |
1859 | int pll_id, | |
1860 | int div_id, | |
1861 | unsigned long clk_rate) | |
1862 | { | |
1863 | struct stm32mp1_clk_priv *priv = dev_get_priv(dev); | |
1864 | const struct stm32mp1_clk_pll *pll = priv->data->pll; | |
1865 | u32 pllxcr = priv->base + pll[pll_id].pllxcr; | |
1866 | int div; | |
1867 | ulong fvco; | |
1868 | ||
1869 | if (div_id > _DIV_NB) | |
1870 | return -EINVAL; | |
1871 | ||
1872 | fvco = pll_get_fvco(priv, pll_id); | |
1873 | ||
1874 | if (fvco <= clk_rate) | |
1875 | div = 1; | |
1876 | else | |
1877 | div = DIV_ROUND_UP(fvco, clk_rate); | |
1878 | ||
1879 | if (div > 128) | |
1880 | div = 128; | |
1881 | ||
88fa34df PD |
1882 | /* stop the requested output */ |
1883 | clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT); | |
1884 | /* change divider */ | |
1885 | clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2, | |
1886 | RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id), | |
1887 | (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id)); | |
1888 | /* start the requested output */ | |
1889 | setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT); | |
1890 | ||
1891 | return 0; | |
1892 | } | |
1893 | ||
1894 | static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) | |
1895 | { | |
1896 | struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); | |
1897 | int p; | |
1898 | ||
1899 | switch (clk->id) { | |
c3e828bf PD |
1900 | #if defined(STM32MP1_CLOCK_TREE_INIT) && \ |
1901 | defined(CONFIG_STM32MP1_DDR_INTERACTIVE) | |
1902 | case DDRPHYC: | |
1903 | break; | |
1904 | #endif | |
88fa34df PD |
1905 | case LTDC_PX: |
1906 | case DSI_PX: | |
1907 | break; | |
1908 | default: | |
1909 | pr_err("not supported"); | |
1910 | return -EINVAL; | |
1911 | } | |
1912 | ||
1913 | p = stm32mp1_clk_get_parent(priv, clk->id); | |
7879a7d0 PD |
1914 | #ifdef DEBUG |
1915 | debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]); | |
1916 | #endif | |
88fa34df PD |
1917 | if (p < 0) |
1918 | return -EINVAL; | |
1919 | ||
1920 | switch (p) { | |
c3e828bf PD |
1921 | #if defined(STM32MP1_CLOCK_TREE_INIT) && \ |
1922 | defined(CONFIG_STM32MP1_DDR_INTERACTIVE) | |
1923 | case _PLL2_R: /* DDRPHYC */ | |
1924 | { | |
1925 | /* only for change DDR clock in interactive mode */ | |
1926 | ulong result; | |
1927 | ||
1928 | set_clksrc(priv, CLK_AXI_HSI); | |
1929 | result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate); | |
1930 | set_clksrc(priv, CLK_AXI_PLL2P); | |
1931 | return result; | |
1932 | } | |
1933 | #endif | |
7879a7d0 | 1934 | |
88fa34df PD |
1935 | case _PLL4_Q: |
1936 | /* for LTDC_PX and DSI_PX case */ | |
1937 | return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate); | |
1938 | } | |
1939 | ||
1940 | return -EINVAL; | |
1941 | } | |
1942 | ||
a6151916 PD |
1943 | static void stm32mp1_osc_clk_init(const char *name, |
1944 | struct stm32mp1_clk_priv *priv, | |
1945 | int index) | |
1946 | { | |
1947 | struct clk clk; | |
1948 | struct udevice *dev = NULL; | |
1949 | ||
1950 | priv->osc[index] = 0; | |
1951 | clk.id = 0; | |
1952 | if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { | |
1953 | if (clk_request(dev, &clk)) | |
1954 | pr_err("%s request", name); | |
1955 | else | |
1956 | priv->osc[index] = clk_get_rate(&clk); | |
1957 | } | |
1958 | priv->osc_dev[index] = dev; | |
1959 | } | |
1960 | ||
1961 | static void stm32mp1_osc_init(struct udevice *dev) | |
1962 | { | |
1963 | struct stm32mp1_clk_priv *priv = dev_get_priv(dev); | |
1964 | int i; | |
1965 | const char *name[NB_OSC] = { | |
1966 | [_LSI] = "clk-lsi", | |
1967 | [_LSE] = "clk-lse", | |
1968 | [_HSI] = "clk-hsi", | |
1969 | [_HSE] = "clk-hse", | |
1970 | [_CSI] = "clk-csi", | |
1971 | [_I2S_CKIN] = "i2s_ckin", | |
86617dd1 | 1972 | }; |
a6151916 PD |
1973 | |
1974 | for (i = 0; i < NB_OSC; i++) { | |
1975 | stm32mp1_osc_clk_init(name[i], priv, i); | |
1976 | debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); | |
1977 | } | |
1978 | } | |
1979 | ||
8d6310aa PD |
1980 | static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv) |
1981 | { | |
1982 | char buf[32]; | |
1983 | int i, s, p; | |
1984 | ||
1985 | printf("Clocks:\n"); | |
1986 | for (i = 0; i < _PARENT_NB; i++) { | |
1987 | printf("- %s : %s MHz\n", | |
1988 | stm32mp1_clk_parent_name[i], | |
1989 | strmhz(buf, stm32mp1_clk_get(priv, i))); | |
1990 | } | |
1991 | printf("Source Clocks:\n"); | |
1992 | for (i = 0; i < _PARENT_SEL_NB; i++) { | |
1993 | p = (readl(priv->base + priv->data->sel[i].offset) >> | |
1994 | priv->data->sel[i].src) & priv->data->sel[i].msk; | |
1995 | if (p < priv->data->sel[i].nb_parent) { | |
1996 | s = priv->data->sel[i].parent[p]; | |
1997 | printf("- %s(%d) => parent %s(%d)\n", | |
1998 | stm32mp1_clk_parent_sel_name[i], i, | |
1999 | stm32mp1_clk_parent_name[s], s); | |
2000 | } else { | |
2001 | printf("- %s(%d) => parent index %d is invalid\n", | |
2002 | stm32mp1_clk_parent_sel_name[i], i, p); | |
2003 | } | |
2004 | } | |
2005 | } | |
2006 | ||
2007 | #ifdef CONFIG_CMD_CLK | |
2008 | int soc_clk_dump(void) | |
2009 | { | |
2010 | struct udevice *dev; | |
2011 | struct stm32mp1_clk_priv *priv; | |
2012 | int ret; | |
2013 | ||
2014 | ret = uclass_get_device_by_driver(UCLASS_CLK, | |
2015 | DM_GET_DRIVER(stm32mp1_clock), | |
2016 | &dev); | |
2017 | if (ret) | |
2018 | return ret; | |
2019 | ||
2020 | priv = dev_get_priv(dev); | |
2021 | ||
2022 | stm32mp1_clk_dump(priv); | |
2023 | ||
2024 | return 0; | |
2025 | } | |
2026 | #endif | |
2027 | ||
a6151916 PD |
2028 | static int stm32mp1_clk_probe(struct udevice *dev) |
2029 | { | |
2030 | int result = 0; | |
2031 | struct stm32mp1_clk_priv *priv = dev_get_priv(dev); | |
2032 | ||
2033 | priv->base = dev_read_addr(dev->parent); | |
2034 | if (priv->base == FDT_ADDR_T_NONE) | |
2035 | return -EINVAL; | |
2036 | ||
2037 | priv->data = (void *)&stm32mp1_data; | |
2038 | ||
2039 | if (!priv->data->gate || !priv->data->sel || | |
2040 | !priv->data->pll) | |
2041 | return -EINVAL; | |
2042 | ||
2043 | stm32mp1_osc_init(dev); | |
2044 | ||
266fa4df PD |
2045 | #ifdef STM32MP1_CLOCK_TREE_INIT |
2046 | /* clock tree init is done only one time, before relocation */ | |
2047 | if (!(gd->flags & GD_FLG_RELOC)) | |
2048 | result = stm32mp1_clktree(dev); | |
2049 | #endif | |
2050 | ||
8d6310aa PD |
2051 | #ifndef CONFIG_SPL_BUILD |
2052 | #if defined(DEBUG) | |
2053 | /* display debug information for probe after relocation */ | |
2054 | if (gd->flags & GD_FLG_RELOC) | |
2055 | stm32mp1_clk_dump(priv); | |
2056 | #endif | |
2057 | ||
4de076ed PD |
2058 | gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU); |
2059 | gd->bus_clk = stm32mp1_clk_get(priv, _ACLK); | |
2060 | /* DDRPHYC father */ | |
2061 | gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R); | |
8d6310aa PD |
2062 | #if defined(CONFIG_DISPLAY_CPUINFO) |
2063 | if (gd->flags & GD_FLG_RELOC) { | |
2064 | char buf[32]; | |
2065 | ||
2066 | printf("Clocks:\n"); | |
4de076ed | 2067 | printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk)); |
8d6310aa PD |
2068 | printf("- MCU : %s MHz\n", |
2069 | strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU))); | |
4de076ed | 2070 | printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk)); |
8d6310aa PD |
2071 | printf("- PER : %s MHz\n", |
2072 | strmhz(buf, stm32mp1_clk_get(priv, _CK_PER))); | |
4de076ed | 2073 | printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk)); |
8d6310aa PD |
2074 | } |
2075 | #endif /* CONFIG_DISPLAY_CPUINFO */ | |
2076 | #endif | |
2077 | ||
a6151916 PD |
2078 | return result; |
2079 | } | |
2080 | ||
2081 | static const struct clk_ops stm32mp1_clk_ops = { | |
2082 | .enable = stm32mp1_clk_enable, | |
2083 | .disable = stm32mp1_clk_disable, | |
2084 | .get_rate = stm32mp1_clk_get_rate, | |
88fa34df | 2085 | .set_rate = stm32mp1_clk_set_rate, |
a6151916 PD |
2086 | }; |
2087 | ||
a6151916 PD |
2088 | U_BOOT_DRIVER(stm32mp1_clock) = { |
2089 | .name = "stm32mp1_clk", | |
2090 | .id = UCLASS_CLK, | |
a6151916 PD |
2091 | .ops = &stm32mp1_clk_ops, |
2092 | .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv), | |
2093 | .probe = stm32mp1_clk_probe, | |
2094 | }; |