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clk: stm32: add hardware spinlock clock
[thirdparty/u-boot.git] / drivers / clk / clk_stm32mp1.c
CommitLineData
4549e789 1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
a6151916
PD		 2/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
a6151916
PD		 4 */
5
6#include <common.h>
7#include <clk-uclass.h>
8#include <div64.h>
9#include <dm.h>
10#include <regmap.h>
11#include <spl.h>
12#include <syscon.h>
13#include <linux/io.h>
266fa4df 14#include <linux/iopoll.h>
a6151916 15#include <dt-bindings/clock/stm32mp1-clks.h>
266fa4df
PD		 16#include <dt-bindings/clock/stm32mp1-clksrc.h>
17
18#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
19/* activate clock tree initialization in the driver */
20#define STM32MP1_CLOCK_TREE_INIT
21#endif
a6151916
PD		 22
23#define MAX_HSI_HZ 64000000
24
266fa4df
PD		 25/* TIMEOUT */
26#define TIMEOUT_200MS 200000
27#define TIMEOUT_1S 1000000
28
938e0e3f
PD		 29/* STGEN registers */
30#define STGENC_CNTCR 0x00
31#define STGENC_CNTSR 0x04
32#define STGENC_CNTCVL 0x08
33#define STGENC_CNTCVU 0x0C
34#define STGENC_CNTFID0 0x20
35
36#define STGENC_CNTCR_EN BIT(0)
37
a6151916
PD		 38/* RCC registers */
39#define RCC_OCENSETR 0x0C
40#define RCC_OCENCLRR 0x10
41#define RCC_HSICFGR 0x18
42#define RCC_MPCKSELR 0x20
43#define RCC_ASSCKSELR 0x24
44#define RCC_RCK12SELR 0x28
45#define RCC_MPCKDIVR 0x2C
46#define RCC_AXIDIVR 0x30
47#define RCC_APB4DIVR 0x3C
48#define RCC_APB5DIVR 0x40
49#define RCC_RTCDIVR 0x44
50#define RCC_MSSCKSELR 0x48
51#define RCC_PLL1CR 0x80
52#define RCC_PLL1CFGR1 0x84
53#define RCC_PLL1CFGR2 0x88
54#define RCC_PLL1FRACR 0x8C
55#define RCC_PLL1CSGR 0x90
56#define RCC_PLL2CR 0x94
57#define RCC_PLL2CFGR1 0x98
58#define RCC_PLL2CFGR2 0x9C
59#define RCC_PLL2FRACR 0xA0
60#define RCC_PLL2CSGR 0xA4
61#define RCC_I2C46CKSELR 0xC0
62#define RCC_CPERCKSELR 0xD0
63#define RCC_STGENCKSELR 0xD4
64#define RCC_DDRITFCR 0xD8
65#define RCC_BDCR 0x140
66#define RCC_RDLSICR 0x144
67#define RCC_MP_APB4ENSETR 0x200
68#define RCC_MP_APB5ENSETR 0x208
69#define RCC_MP_AHB5ENSETR 0x210
70#define RCC_MP_AHB6ENSETR 0x218
71#define RCC_OCRDYR 0x808
72#define RCC_DBGCFGR 0x80C
73#define RCC_RCK3SELR 0x820
74#define RCC_RCK4SELR 0x824
75#define RCC_MCUDIVR 0x830
76#define RCC_APB1DIVR 0x834
77#define RCC_APB2DIVR 0x838
78#define RCC_APB3DIVR 0x83C
79#define RCC_PLL3CR 0x880
80#define RCC_PLL3CFGR1 0x884
81#define RCC_PLL3CFGR2 0x888
82#define RCC_PLL3FRACR 0x88C
83#define RCC_PLL3CSGR 0x890
84#define RCC_PLL4CR 0x894
85#define RCC_PLL4CFGR1 0x898
86#define RCC_PLL4CFGR2 0x89C
87#define RCC_PLL4FRACR 0x8A0
88#define RCC_PLL4CSGR 0x8A4
89#define RCC_I2C12CKSELR 0x8C0
90#define RCC_I2C35CKSELR 0x8C4
91#define RCC_UART6CKSELR 0x8E4
92#define RCC_UART24CKSELR 0x8E8
93#define RCC_UART35CKSELR 0x8EC
94#define RCC_UART78CKSELR 0x8F0
95#define RCC_SDMMC12CKSELR 0x8F4
96#define RCC_SDMMC3CKSELR 0x8F8
97#define RCC_ETHCKSELR 0x8FC
98#define RCC_QSPICKSELR 0x900
99#define RCC_FMCCKSELR 0x904
100#define RCC_USBCKSELR 0x91C
88fa34df 101#define RCC_DSICKSELR 0x924
5b25eb9f 102#define RCC_ADCCKSELR 0x928
a6151916
PD		 103#define RCC_MP_APB1ENSETR 0xA00
104#define RCC_MP_APB2ENSETR 0XA08
f198bbac 105#define RCC_MP_APB3ENSETR 0xA10
a6151916 106#define RCC_MP_AHB2ENSETR 0xA18
283bcd9a 107#define RCC_MP_AHB3ENSETR 0xA20
a6151916
PD		 108#define RCC_MP_AHB4ENSETR 0xA28
109
110/* used for most of SELR register */
111#define RCC_SELR_SRC_MASK GENMASK(2, 0)
112#define RCC_SELR_SRCRDY BIT(31)
113
114/* Values of RCC_MPCKSELR register */
115#define RCC_MPCKSELR_HSI 0
116#define RCC_MPCKSELR_HSE 1
117#define RCC_MPCKSELR_PLL 2
118#define RCC_MPCKSELR_PLL_MPUDIV 3
119
120/* Values of RCC_ASSCKSELR register */
121#define RCC_ASSCKSELR_HSI 0
122#define RCC_ASSCKSELR_HSE 1
123#define RCC_ASSCKSELR_PLL 2
124
125/* Values of RCC_MSSCKSELR register */
126#define RCC_MSSCKSELR_HSI 0
127#define RCC_MSSCKSELR_HSE 1
128#define RCC_MSSCKSELR_CSI 2
129#define RCC_MSSCKSELR_PLL 3
130
131/* Values of RCC_CPERCKSELR register */
132#define RCC_CPERCKSELR_HSI 0
133#define RCC_CPERCKSELR_CSI 1
134#define RCC_CPERCKSELR_HSE 2
135
136/* used for most of DIVR register : max div for RTC */
137#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
138#define RCC_DIVR_DIVRDY BIT(31)
139
140/* Masks for specific DIVR registers */
141#define RCC_APBXDIV_MASK GENMASK(2, 0)
142#define RCC_MPUDIV_MASK GENMASK(2, 0)
143#define RCC_AXIDIV_MASK GENMASK(2, 0)
144#define RCC_MCUDIV_MASK GENMASK(3, 0)
145
146/* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
147#define RCC_MP_ENCLRR_OFFSET 4
148
149/* Fields of RCC_BDCR register */
150#define RCC_BDCR_LSEON BIT(0)
151#define RCC_BDCR_LSEBYP BIT(1)
152#define RCC_BDCR_LSERDY BIT(2)
d2194155 153#define RCC_BDCR_DIGBYP BIT(3)
a6151916
PD		 154#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
155#define RCC_BDCR_LSEDRV_SHIFT 4
156#define RCC_BDCR_LSECSSON BIT(8)
157#define RCC_BDCR_RTCCKEN BIT(20)
158#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
159#define RCC_BDCR_RTCSRC_SHIFT 16
160
161/* Fields of RCC_RDLSICR register */
162#define RCC_RDLSICR_LSION BIT(0)
163#define RCC_RDLSICR_LSIRDY BIT(1)
164
165/* used for ALL PLLNCR registers */
166#define RCC_PLLNCR_PLLON BIT(0)
167#define RCC_PLLNCR_PLLRDY BIT(1)
168#define RCC_PLLNCR_DIVPEN BIT(4)
169#define RCC_PLLNCR_DIVQEN BIT(5)
170#define RCC_PLLNCR_DIVREN BIT(6)
171#define RCC_PLLNCR_DIVEN_SHIFT 4
172
173/* used for ALL PLLNCFGR1 registers */
174#define RCC_PLLNCFGR1_DIVM_SHIFT 16
175#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
176#define RCC_PLLNCFGR1_DIVN_SHIFT 0
177#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
178/* only for PLL3 and PLL4 */
179#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
180#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
181
c2fa5dc8
PD		 182/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
183#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
a6151916 184#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
c2fa5dc8 185#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
a6151916 186#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
c2fa5dc8 187#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
a6151916 188#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
c2fa5dc8 189#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
a6151916
PD		 190#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
191
192/* used for ALL PLLNFRACR registers */
193#define RCC_PLLNFRACR_FRACV_SHIFT 3
194#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
195#define RCC_PLLNFRACR_FRACLE BIT(16)
196
197/* used for ALL PLLNCSGR registers */
198#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
199#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
200#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
201#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
202#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
203#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
204
205/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
206#define RCC_OCENR_HSION BIT(0)
207#define RCC_OCENR_CSION BIT(4)
d2194155 208#define RCC_OCENR_DIGBYP BIT(7)
a6151916
PD		 209#define RCC_OCENR_HSEON BIT(8)
210#define RCC_OCENR_HSEBYP BIT(10)
211#define RCC_OCENR_HSECSSON BIT(11)
212
213/* Fields of RCC_OCRDYR register */
214#define RCC_OCRDYR_HSIRDY BIT(0)
215#define RCC_OCRDYR_HSIDIVRDY BIT(2)
216#define RCC_OCRDYR_CSIRDY BIT(4)
217#define RCC_OCRDYR_HSERDY BIT(8)
218
219/* Fields of DDRITFCR register */
220#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
221#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
222#define RCC_DDRITFCR_DDRCKMOD_SSR 0
223
224/* Fields of RCC_HSICFGR register */
225#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
226
227/* used for MCO related operations */
228#define RCC_MCOCFG_MCOON BIT(12)
229#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
230#define RCC_MCOCFG_MCODIV_SHIFT 4
231#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
232
233enum stm32mp1_parent_id {
234/*
235 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
236 * they are used as index in osc[] as entry point
237 */
238 _HSI,
239 _HSE,
240 _CSI,
241 _LSI,
242 _LSE,
243 _I2S_CKIN,
244 _USB_PHY_48,
245 NB_OSC,
246
247/* other parent source */
248 _HSI_KER = NB_OSC,
249 _HSE_KER,
250 _HSE_KER_DIV2,
251 _CSI_KER,
252 _PLL1_P,
253 _PLL1_Q,
254 _PLL1_R,
255 _PLL2_P,
256 _PLL2_Q,
257 _PLL2_R,
258 _PLL3_P,
259 _PLL3_Q,
260 _PLL3_R,
261 _PLL4_P,
262 _PLL4_Q,
263 _PLL4_R,
264 _ACLK,
265 _PCLK1,
266 _PCLK2,
267 _PCLK3,
268 _PCLK4,
269 _PCLK5,
270 _HCLK6,
271 _HCLK2,
272 _CK_PER,
273 _CK_MPU,
274 _CK_MCU,
88fa34df 275 _DSI_PHY,
a6151916
PD		 276 _PARENT_NB,
277 _UNKNOWN_ID = 0xff,
278};
279
280enum stm32mp1_parent_sel {
281 _I2C12_SEL,
282 _I2C35_SEL,
283 _I2C46_SEL,
284 _UART6_SEL,
285 _UART24_SEL,
286 _UART35_SEL,
287 _UART78_SEL,
288 _SDMMC12_SEL,
289 _SDMMC3_SEL,
290 _ETH_SEL,
291 _QSPI_SEL,
292 _FMC_SEL,
293 _USBPHY_SEL,
294 _USBO_SEL,
295 _STGEN_SEL,
88fa34df 296 _DSI_SEL,
5b25eb9f 297 _ADC12_SEL,
a6151916
PD		 298 _PARENT_SEL_NB,
299 _UNKNOWN_SEL = 0xff,
300};
301
302enum stm32mp1_pll_id {
303 _PLL1,
304 _PLL2,
305 _PLL3,
306 _PLL4,
307 _PLL_NB
308};
309
310enum stm32mp1_div_id {
311 _DIV_P,
312 _DIV_Q,
313 _DIV_R,
314 _DIV_NB,
315};
316
317enum stm32mp1_clksrc_id {
318 CLKSRC_MPU,
319 CLKSRC_AXI,
320 CLKSRC_MCU,
321 CLKSRC_PLL12,
322 CLKSRC_PLL3,
323 CLKSRC_PLL4,
324 CLKSRC_RTC,
325 CLKSRC_MCO1,
326 CLKSRC_MCO2,
327 CLKSRC_NB
328};
329
330enum stm32mp1_clkdiv_id {
331 CLKDIV_MPU,
332 CLKDIV_AXI,
333 CLKDIV_MCU,
334 CLKDIV_APB1,
335 CLKDIV_APB2,
336 CLKDIV_APB3,
337 CLKDIV_APB4,
338 CLKDIV_APB5,
339 CLKDIV_RTC,
340 CLKDIV_MCO1,
341 CLKDIV_MCO2,
342 CLKDIV_NB
343};
344
345enum stm32mp1_pllcfg {
346 PLLCFG_M,
347 PLLCFG_N,
348 PLLCFG_P,
349 PLLCFG_Q,
350 PLLCFG_R,
351 PLLCFG_O,
352 PLLCFG_NB
353};
354
355enum stm32mp1_pllcsg {
356 PLLCSG_MOD_PER,
357 PLLCSG_INC_STEP,
358 PLLCSG_SSCG_MODE,
359 PLLCSG_NB
360};
361
362enum stm32mp1_plltype {
363 PLL_800,
364 PLL_1600,
365 PLL_TYPE_NB
366};
367
368struct stm32mp1_pll {
369 u8 refclk_min;
370 u8 refclk_max;
371 u8 divn_max;
372};
373
374struct stm32mp1_clk_gate {
375 u16 offset;
376 u8 bit;
377 u8 index;
378 u8 set_clr;
379 u8 sel;
380 u8 fixed;
381};
382
383struct stm32mp1_clk_sel {
384 u16 offset;
385 u8 src;
386 u8 msk;
387 u8 nb_parent;
388 const u8 *parent;
389};
390
391#define REFCLK_SIZE 4
392struct stm32mp1_clk_pll {
393 enum stm32mp1_plltype plltype;
394 u16 rckxselr;
395 u16 pllxcfgr1;
396 u16 pllxcfgr2;
397 u16 pllxfracr;
398 u16 pllxcr;
399 u16 pllxcsgr;
400 u8 refclk[REFCLK_SIZE];
401};
402
403struct stm32mp1_clk_data {
404 const struct stm32mp1_clk_gate *gate;
405 const struct stm32mp1_clk_sel *sel;
406 const struct stm32mp1_clk_pll *pll;
407 const int nb_gate;
408};
409
410struct stm32mp1_clk_priv {
411 fdt_addr_t base;
412 const struct stm32mp1_clk_data *data;
413 ulong osc[NB_OSC];
414 struct udevice *osc_dev[NB_OSC];
415};
416
417#define STM32MP1_CLK(off, b, idx, s) \
418 { \
419 .offset = (off), \
420 .bit = (b), \
421 .index = (idx), \
422 .set_clr = 0, \
423 .sel = (s), \
424 .fixed = _UNKNOWN_ID, \
425 }
426
427#define STM32MP1_CLK_F(off, b, idx, f) \
428 { \
429 .offset = (off), \
430 .bit = (b), \
431 .index = (idx), \
432 .set_clr = 0, \
433 .sel = _UNKNOWN_SEL, \
434 .fixed = (f), \
435 }
436
437#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
438 { \
439 .offset = (off), \
440 .bit = (b), \
441 .index = (idx), \
442 .set_clr = 1, \
443 .sel = (s), \
444 .fixed = _UNKNOWN_ID, \
445 }
446
447#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
448 { \
449 .offset = (off), \
450 .bit = (b), \
451 .index = (idx), \
452 .set_clr = 1, \
453 .sel = _UNKNOWN_SEL, \
454 .fixed = (f), \
455 }
456
457#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
458 [(idx)] = { \
459 .offset = (off), \
460 .src = (s), \
461 .msk = (m), \
462 .parent = (p), \
463 .nb_parent = ARRAY_SIZE((p)) \
464 }
465
466#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
467 p1, p2, p3, p4) \
468 [(idx)] = { \
469 .plltype = (type), \
470 .rckxselr = (off1), \
471 .pllxcfgr1 = (off2), \
472 .pllxcfgr2 = (off3), \
473 .pllxfracr = (off4), \
474 .pllxcr = (off5), \
475 .pllxcsgr = (off6), \
476 .refclk[0] = (p1), \
477 .refclk[1] = (p2), \
478 .refclk[2] = (p3), \
479 .refclk[3] = (p4), \
480 }
481
482static const u8 stm32mp1_clks[][2] = {
483 {CK_PER, _CK_PER},
484 {CK_MPU, _CK_MPU},
485 {CK_AXI, _ACLK},
486 {CK_MCU, _CK_MCU},
487 {CK_HSE, _HSE},
488 {CK_CSI, _CSI},
489 {CK_LSI, _LSI},
490 {CK_LSE, _LSE},
491 {CK_HSI, _HSI},
492 {CK_HSE_DIV2, _HSE_KER_DIV2},
493};
494
495static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
496 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
497 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
498 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
499 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
500 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
501 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
502 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
503 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
504 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
505 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
506 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
507
508 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
509 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
510 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
511 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
512 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
513 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
514 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
515 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
516 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
517 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
518
519 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
520
f198bbac
FG		 521 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
522
88fa34df
PD		 523 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
524 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
525 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
a6151916
PD		 526 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
527 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
528 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
529
530 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
531 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
532
5b25eb9f
PD		 533 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
534 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
a6151916
PD		 535 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
536 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
537
283bcd9a
BG		 538 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
539
a6151916
PD		 540 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
541 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
542 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
543 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
544 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
545 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
546 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
547 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
548 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
549 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
550 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
551
552 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
553
04365530 554 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
a6151916
PD		 555 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
556 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
a6151916
PD		 557 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
558 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
559 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
560 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
561 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
562 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
563
564 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
565};
566
567static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
568static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
569static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
570static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
571 _HSE_KER};
572static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
573 _HSE_KER};
574static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
575 _HSE_KER};
576static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
577 _HSE_KER};
578static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
579static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
580static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
581static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
582static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
583static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
584static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
585static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
88fa34df 586static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
5b25eb9f 587static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
a6151916
PD		 588
589static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
590 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
591 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
592 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
593 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
594 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
595 uart24_parents),
596 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
597 uart35_parents),
598 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
599 uart78_parents),
600 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
601 sdmmc12_parents),
602 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
603 sdmmc3_parents),
604 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
605 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
606 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
607 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
608 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
609 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
88fa34df 610 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
5b25eb9f 611 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
a6151916
PD		 612};
613
614#ifdef STM32MP1_CLOCK_TREE_INIT
615/* define characteristic of PLL according type */
616#define DIVN_MIN 24
617static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
618 [PLL_800] = {
619 .refclk_min = 4,
620 .refclk_max = 16,
621 .divn_max = 99,
622 },
623 [PLL_1600] = {
624 .refclk_min = 8,
625 .refclk_max = 16,
626 .divn_max = 199,
627 },
628};
629#endif /* STM32MP1_CLOCK_TREE_INIT */
630
631static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
632 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
633 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
634 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
635 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
636 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
637 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
638 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
639 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
640 STM32MP1_CLK_PLL(_PLL3, PLL_800,
641 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
642 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
643 _HSI, _HSE, _CSI, _UNKNOWN_ID),
644 STM32MP1_CLK_PLL(_PLL4, PLL_800,
645 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
646 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
647 _HSI, _HSE, _CSI, _I2S_CKIN),
648};
649
650/* Prescaler table lookups for clock computation */
651/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
652static const u8 stm32mp1_mcu_div[16] = {
653 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
654};
655
656/* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
657#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
658#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
659static const u8 stm32mp1_mpu_apbx_div[8] = {
660 0, 1, 2, 3, 4, 4, 4, 4
661};
662
663/* div = /1 /2 /3 /4 */
664static const u8 stm32mp1_axi_div[8] = {
665 1, 2, 3, 4, 4, 4, 4, 4
666};
667
668#ifdef DEBUG
669static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
670 [_HSI] = "HSI",
671 [_HSE] = "HSE",
672 [_CSI] = "CSI",
673 [_LSI] = "LSI",
674 [_LSE] = "LSE",
675 [_I2S_CKIN] = "I2S_CKIN",
676 [_HSI_KER] = "HSI_KER",
677 [_HSE_KER] = "HSE_KER",
678 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
679 [_CSI_KER] = "CSI_KER",
680 [_PLL1_P] = "PLL1_P",
681 [_PLL1_Q] = "PLL1_Q",
682 [_PLL1_R] = "PLL1_R",
683 [_PLL2_P] = "PLL2_P",
684 [_PLL2_Q] = "PLL2_Q",
685 [_PLL2_R] = "PLL2_R",
686 [_PLL3_P] = "PLL3_P",
687 [_PLL3_Q] = "PLL3_Q",
688 [_PLL3_R] = "PLL3_R",
689 [_PLL4_P] = "PLL4_P",
690 [_PLL4_Q] = "PLL4_Q",
691 [_PLL4_R] = "PLL4_R",
692 [_ACLK] = "ACLK",
693 [_PCLK1] = "PCLK1",
694 [_PCLK2] = "PCLK2",
695 [_PCLK3] = "PCLK3",
696 [_PCLK4] = "PCLK4",
697 [_PCLK5] = "PCLK5",
698 [_HCLK6] = "KCLK6",
699 [_HCLK2] = "HCLK2",
700 [_CK_PER] = "CK_PER",
701 [_CK_MPU] = "CK_MPU",
702 [_CK_MCU] = "CK_MCU",
88fa34df
PD		 703 [_USB_PHY_48] = "USB_PHY_48",
704 [_DSI_PHY] = "DSI_PHY_PLL",
a6151916
PD		 705};
706
707static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
708 [_I2C12_SEL] = "I2C12",
709 [_I2C35_SEL] = "I2C35",
710 [_I2C46_SEL] = "I2C46",
711 [_UART6_SEL] = "UART6",
712 [_UART24_SEL] = "UART24",
713 [_UART35_SEL] = "UART35",
714 [_UART78_SEL] = "UART78",
715 [_SDMMC12_SEL] = "SDMMC12",
716 [_SDMMC3_SEL] = "SDMMC3",
717 [_ETH_SEL] = "ETH",
718 [_QSPI_SEL] = "QSPI",
719 [_FMC_SEL] = "FMC",
720 [_USBPHY_SEL] = "USBPHY",
721 [_USBO_SEL] = "USBO",
88fa34df
PD		 722 [_STGEN_SEL] = "STGEN",
723 [_DSI_SEL] = "DSI",
5b25eb9f 724 [_ADC12_SEL] = "ADC12",
a6151916
PD		 725};
726#endif
727
728static const struct stm32mp1_clk_data stm32mp1_data = {
729 .gate = stm32mp1_clk_gate,
730 .sel = stm32mp1_clk_sel,
731 .pll = stm32mp1_clk_pll,
732 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
733};
734
735static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
736{
737 if (idx >= NB_OSC) {
738 debug("%s: clk id %d not found\n", __func__, idx);
739 return 0;
740 }
741
742 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
743 (u32)priv->osc[idx], priv->osc[idx] / 1000);
744
745 return priv->osc[idx];
746}
747
748static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
749{
750 const struct stm32mp1_clk_gate *gate = priv->data->gate;
751 int i, nb_clks = priv->data->nb_gate;
752
753 for (i = 0; i < nb_clks; i++) {
754 if (gate[i].index == id)
755 break;
756 }
757
758 if (i == nb_clks) {
759 printf("%s: clk id %d not found\n", __func__, (u32)id);
760 return -EINVAL;
761 }
762
763 return i;
764}
765
766static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
767 int i)
768{
769 const struct stm32mp1_clk_gate *gate = priv->data->gate;
770
771 if (gate[i].sel > _PARENT_SEL_NB) {
772 printf("%s: parents for clk id %d not found\n",
773 __func__, i);
774 return -EINVAL;
775 }
776
777 return gate[i].sel;
778}
779
780static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
781 int i)
782{
783 const struct stm32mp1_clk_gate *gate = priv->data->gate;
784
785 if (gate[i].fixed == _UNKNOWN_ID)
786 return -ENOENT;
787
788 return gate[i].fixed;
789}
790
791static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
792 unsigned long id)
793{
794 const struct stm32mp1_clk_sel *sel = priv->data->sel;
795 int i;
796 int s, p;
797
798 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
799 if (stm32mp1_clks[i][0] == id)
800 return stm32mp1_clks[i][1];
801
802 i = stm32mp1_clk_get_id(priv, id);
803 if (i < 0)
804 return i;
805
806 p = stm32mp1_clk_get_fixed_parent(priv, i);
807 if (p >= 0 && p < _PARENT_NB)
808 return p;
809
810 s = stm32mp1_clk_get_sel(priv, i);
811 if (s < 0)
812 return s;
813
814 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
815
816 if (p < sel[s].nb_parent) {
817#ifdef DEBUG
818 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
819 stm32mp1_clk_parent_name[sel[s].parent[p]],
820 stm32mp1_clk_parent_sel_name[s],
821 (u32)id);
822#endif
823 return sel[s].parent[p];
824 }
825
826 pr_err("%s: no parents defined for clk id %d\n",
827 __func__, (u32)id);
828
829 return -EINVAL;
830}
831
6110503f
PD		 832static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
833 int pll_id)
a6151916
PD		 834{
835 const struct stm32mp1_clk_pll *pll = priv->data->pll;
6110503f
PD		 836 u32 selr;
837 int src;
838 ulong refclk;
a6151916 839
6110503f 840 /* Get current refclk */
a6151916 841 selr = readl(priv->base + pll[pll_id].rckxselr);
6110503f
PD		 842 src = selr & RCC_SELR_SRC_MASK;
843
844 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
845 debug("PLL%d : selr=%x refclk = %d kHz\n",
846 pll_id, selr, (u32)(refclk / 1000));
847
848 return refclk;
849}
850
851/*
852 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
853 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
854 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
855 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
856 */
857static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
858 int pll_id)
859{
860 const struct stm32mp1_clk_pll *pll = priv->data->pll;
861 int divm, divn;
862 ulong refclk, fvco;
863 u32 cfgr1, fracr;
864
a6151916 865 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
a6151916
PD		 866 fracr = readl(priv->base + pll[pll_id].pllxfracr);
867
a6151916
PD		 868 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
869 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
a6151916 870
6110503f
PD		 871 debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
872 pll_id, cfgr1, fracr, divn, divm);
a6151916 873
6110503f 874 refclk = pll_get_fref_ck(priv, pll_id);
a6151916 875
6110503f
PD		 876 /* with FRACV :
877 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
a6151916 878 * without FRACV
6110503f 879 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
a6151916
PD		 880 */
881 if (fracr & RCC_PLLNFRACR_FRACLE) {
882 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
883 >> RCC_PLLNFRACR_FRACV_SHIFT;
6110503f 884 fvco = (ulong)lldiv((unsigned long long)refclk *
a6151916 885 (((divn + 1) << 13) + fracv),
6110503f 886 ((unsigned long long)(divm + 1)) << 13);
a6151916 887 } else {
6110503f 888 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
a6151916 889 }
6110503f
PD		 890 debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
891
892 return fvco;
893}
894
895static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
896 int pll_id, int div_id)
897{
898 const struct stm32mp1_clk_pll *pll = priv->data->pll;
899 int divy;
900 ulong dfout;
901 u32 cfgr2;
902
903 debug("%s(%d, %d)\n", __func__, pll_id, div_id);
904 if (div_id >= _DIV_NB)
905 return 0;
906
907 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
908 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
909
910 debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
911
912 dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
a6151916
PD		 913 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
914
915 return dfout;
916}
917
918static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
919{
920 u32 reg;
921 ulong clock = 0;
922
923 switch (p) {
924 case _CK_MPU:
925 /* MPU sub system */
926 reg = readl(priv->base + RCC_MPCKSELR);
927 switch (reg & RCC_SELR_SRC_MASK) {
928 case RCC_MPCKSELR_HSI:
929 clock = stm32mp1_clk_get_fixed(priv, _HSI);
930 break;
931 case RCC_MPCKSELR_HSE:
932 clock = stm32mp1_clk_get_fixed(priv, _HSE);
933 break;
934 case RCC_MPCKSELR_PLL:
935 case RCC_MPCKSELR_PLL_MPUDIV:
936 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
937 if (p == RCC_MPCKSELR_PLL_MPUDIV) {
938 reg = readl(priv->base + RCC_MPCKDIVR);
939 clock /= stm32mp1_mpu_div[reg &
940 RCC_MPUDIV_MASK];
941 }
942 break;
943 }
944 break;
945 /* AXI sub system */
946 case _ACLK:
947 case _HCLK2:
948 case _HCLK6:
949 case _PCLK4:
950 case _PCLK5:
951 reg = readl(priv->base + RCC_ASSCKSELR);
952 switch (reg & RCC_SELR_SRC_MASK) {
953 case RCC_ASSCKSELR_HSI:
954 clock = stm32mp1_clk_get_fixed(priv, _HSI);
955 break;
956 case RCC_ASSCKSELR_HSE:
957 clock = stm32mp1_clk_get_fixed(priv, _HSE);
958 break;
959 case RCC_ASSCKSELR_PLL:
960 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
961 break;
962 }
963
964 /* System clock divider */
965 reg = readl(priv->base + RCC_AXIDIVR);
966 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
967
968 switch (p) {
969 case _PCLK4:
970 reg = readl(priv->base + RCC_APB4DIVR);
971 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
972 break;
973 case _PCLK5:
974 reg = readl(priv->base + RCC_APB5DIVR);
975 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
976 break;
977 default:
978 break;
979 }
980 break;
981 /* MCU sub system */
982 case _CK_MCU:
983 case _PCLK1:
984 case _PCLK2:
985 case _PCLK3:
986 reg = readl(priv->base + RCC_MSSCKSELR);
987 switch (reg & RCC_SELR_SRC_MASK) {
988 case RCC_MSSCKSELR_HSI:
989 clock = stm32mp1_clk_get_fixed(priv, _HSI);
990 break;
991 case RCC_MSSCKSELR_HSE:
992 clock = stm32mp1_clk_get_fixed(priv, _HSE);
993 break;
994 case RCC_MSSCKSELR_CSI:
995 clock = stm32mp1_clk_get_fixed(priv, _CSI);
996 break;
997 case RCC_MSSCKSELR_PLL:
998 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
999 break;
1000 }
1001
1002 /* MCU clock divider */
1003 reg = readl(priv->base + RCC_MCUDIVR);
1004 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1005
1006 switch (p) {
1007 case _PCLK1:
1008 reg = readl(priv->base + RCC_APB1DIVR);
1009 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1010 break;
1011 case _PCLK2:
1012 reg = readl(priv->base + RCC_APB2DIVR);
1013 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1014 break;
1015 case _PCLK3:
1016 reg = readl(priv->base + RCC_APB3DIVR);
1017 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1018 break;
1019 case _CK_MCU:
1020 default:
1021 break;
1022 }
1023 break;
1024 case _CK_PER:
1025 reg = readl(priv->base + RCC_CPERCKSELR);
1026 switch (reg & RCC_SELR_SRC_MASK) {
1027 case RCC_CPERCKSELR_HSI:
1028 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1029 break;
1030 case RCC_CPERCKSELR_HSE:
1031 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1032 break;
1033 case RCC_CPERCKSELR_CSI:
1034 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1035 break;
1036 }
1037 break;
1038 case _HSI:
1039 case _HSI_KER:
1040 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1041 break;
1042 case _CSI:
1043 case _CSI_KER:
1044 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1045 break;
1046 case _HSE:
1047 case _HSE_KER:
1048 case _HSE_KER_DIV2:
1049 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1050 if (p == _HSE_KER_DIV2)
1051 clock >>= 1;
1052 break;
1053 case _LSI:
1054 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1055 break;
1056 case _LSE:
1057 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1058 break;
1059 /* PLL */
1060 case _PLL1_P:
1061 case _PLL1_Q:
1062 case _PLL1_R:
1063 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1064 break;
1065 case _PLL2_P:
1066 case _PLL2_Q:
1067 case _PLL2_R:
1068 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1069 break;
1070 case _PLL3_P:
1071 case _PLL3_Q:
1072 case _PLL3_R:
1073 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1074 break;
1075 case _PLL4_P:
1076 case _PLL4_Q:
1077 case _PLL4_R:
1078 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1079 break;
1080 /* other */
1081 case _USB_PHY_48:
1082 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
1083 break;
88fa34df
PD		 1084 case _DSI_PHY:
1085 {
1086 struct clk clk;
1087 struct udevice *dev = NULL;
1088
1089 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1090 &dev)) {
1091 if (clk_request(dev, &clk)) {
1092 pr_err("ck_dsi_phy request");
1093 } else {
1094 clk.id = 0;
1095 clock = clk_get_rate(&clk);
1096 }
1097 }
1098 break;
1099 }
a6151916
PD		 1100 default:
1101 break;
1102 }
1103
1104 debug("%s(%d) clock = %lx : %ld kHz\n",
1105 __func__, p, clock, clock / 1000);
1106
1107 return clock;
1108}
1109
1110static int stm32mp1_clk_enable(struct clk *clk)
1111{
1112 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1113 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1114 int i = stm32mp1_clk_get_id(priv, clk->id);
1115
1116 if (i < 0)
1117 return i;
1118
1119 if (gate[i].set_clr)
1120 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1121 else
1122 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1123
1124 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1125
1126 return 0;
1127}
1128
1129static int stm32mp1_clk_disable(struct clk *clk)
1130{
1131 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1132 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1133 int i = stm32mp1_clk_get_id(priv, clk->id);
1134
1135 if (i < 0)
1136 return i;
1137
1138 if (gate[i].set_clr)
1139 writel(BIT(gate[i].bit),
1140 priv->base + gate[i].offset
1141 + RCC_MP_ENCLRR_OFFSET);
1142 else
1143 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1144
1145 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1146
1147 return 0;
1148}
1149
1150static ulong stm32mp1_clk_get_rate(struct clk *clk)
1151{
1152 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1153 int p = stm32mp1_clk_get_parent(priv, clk->id);
1154 ulong rate;
1155
1156 if (p < 0)
1157 return 0;
1158
1159 rate = stm32mp1_clk_get(priv, p);
1160
1161#ifdef DEBUG
1162 debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1163 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1164#endif
1165 return rate;
1166}
1167
266fa4df
PD		 1168#ifdef STM32MP1_CLOCK_TREE_INIT
1169static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1170 u32 mask_on)
1171{
1172 u32 address = rcc + offset;
1173
1174 if (enable)
1175 setbits_le32(address, mask_on);
1176 else
1177 clrbits_le32(address, mask_on);
1178}
1179
1180static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1181{
1182 if (enable)
1183 setbits_le32(rcc + RCC_OCENSETR, mask_on);
1184 else
1185 setbits_le32(rcc + RCC_OCENCLRR, mask_on);
1186}
1187
1188static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1189 u32 mask_rdy)
1190{
1191 u32 mask_test = 0;
1192 u32 address = rcc + offset;
1193 u32 val;
1194 int ret;
1195
1196 if (enable)
1197 mask_test = mask_rdy;
1198
1199 ret = readl_poll_timeout(address, val,
1200 (val & mask_rdy) == mask_test,
1201 TIMEOUT_1S);
1202
1203 if (ret)
1204 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1205 mask_rdy, address, enable, readl(address));
1206
1207 return ret;
1208}
1209
d2194155
PD		 1210static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1211 int lsedrv)
266fa4df
PD		 1212{
1213 u32 value;
1214
d2194155
PD		 1215 if (digbyp)
1216 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1217
1218 if (bypass || digbyp)
266fa4df
PD		 1219 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1220
1221 /*
1222 * warning: not recommended to switch directly from "high drive"
1223 * to "medium low drive", and vice-versa.
1224 */
1225 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1226 >> RCC_BDCR_LSEDRV_SHIFT;
1227
1228 while (value != lsedrv) {
1229 if (value > lsedrv)
1230 value--;
1231 else
1232 value++;
1233
1234 clrsetbits_le32(rcc + RCC_BDCR,
1235 RCC_BDCR_LSEDRV_MASK,
1236 value << RCC_BDCR_LSEDRV_SHIFT);
1237 }
1238
1239 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1240}
1241
1242static void stm32mp1_lse_wait(fdt_addr_t rcc)
1243{
1244 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1245}
1246
1247static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1248{
1249 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1250 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1251}
1252
d2194155 1253static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
266fa4df 1254{
d2194155
PD		 1255 if (digbyp)
1256 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_DIGBYP);
1257 if (bypass || digbyp)
266fa4df
PD		 1258 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1259
1260 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1261 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1262
1263 if (css)
1264 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1265}
1266
1267static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1268{
1269 stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
1270 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1271}
1272
1273static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1274{
1275 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1276 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1277}
1278
1279static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1280{
1281 u32 address = rcc + RCC_OCRDYR;
1282 u32 val;
1283 int ret;
1284
1285 clrsetbits_le32(rcc + RCC_HSICFGR,
1286 RCC_HSICFGR_HSIDIV_MASK,
1287 RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1288
1289 ret = readl_poll_timeout(address, val,
1290 val & RCC_OCRDYR_HSIDIVRDY,
1291 TIMEOUT_200MS);
1292 if (ret)
1293 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1294 address, readl(address));
1295
1296 return ret;
1297}
1298
1299static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1300{
1301 u8 hsidiv;
1302 u32 hsidivfreq = MAX_HSI_HZ;
1303
1304 for (hsidiv = 0; hsidiv < 4; hsidiv++,
1305 hsidivfreq = hsidivfreq / 2)
1306 if (hsidivfreq == hsifreq)
1307 break;
1308
1309 if (hsidiv == 4) {
1310 pr_err("clk-hsi frequency invalid");
1311 return -1;
1312 }
1313
1314 if (hsidiv > 0)
1315 return stm32mp1_set_hsidiv(rcc, hsidiv);
1316
1317 return 0;
1318}
1319
1320static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1321{
1322 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1323
1324 writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
1325}
1326
1327static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1328{
1329 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1330 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1331 u32 val;
1332 int ret;
1333
1334 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1335 TIMEOUT_200MS);
1336
1337 if (ret) {
1338 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1339 pll_id, pllxcr, readl(pllxcr));
1340 return ret;
1341 }
1342
1343 /* start the requested output */
1344 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1345
1346 return 0;
1347}
1348
1349static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1350{
1351 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1352 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1353 u32 val;
1354
1355 /* stop all output */
1356 clrbits_le32(pllxcr,
1357 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1358
1359 /* stop PLL */
1360 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1361
1362 /* wait PLL stopped */
1363 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1364 TIMEOUT_200MS);
1365}
1366
1367static void pll_config_output(struct stm32mp1_clk_priv *priv,
1368 int pll_id, u32 *pllcfg)
1369{
1370 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1371 fdt_addr_t rcc = priv->base;
1372 u32 value;
1373
1374 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1375 & RCC_PLLNCFGR2_DIVP_MASK;
1376 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1377 & RCC_PLLNCFGR2_DIVQ_MASK;
1378 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1379 & RCC_PLLNCFGR2_DIVR_MASK;
1380 writel(value, rcc + pll[pll_id].pllxcfgr2);
1381}
1382
1383static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1384 u32 *pllcfg, u32 fracv)
1385{
1386 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1387 fdt_addr_t rcc = priv->base;
1388 enum stm32mp1_plltype type = pll[pll_id].plltype;
1389 int src;
1390 ulong refclk;
1391 u8 ifrge = 0;
1392 u32 value;
1393
1394 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1395
1396 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1397 (pllcfg[PLLCFG_M] + 1);
1398
1399 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1400 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1401 debug("invalid refclk = %x\n", (u32)refclk);
1402 return -EINVAL;
1403 }
1404 if (type == PLL_800 && refclk >= 8000000)
1405 ifrge = 1;
1406
1407 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1408 & RCC_PLLNCFGR1_DIVN_MASK;
1409 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1410 & RCC_PLLNCFGR1_DIVM_MASK;
1411 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1412 & RCC_PLLNCFGR1_IFRGE_MASK;
1413 writel(value, rcc + pll[pll_id].pllxcfgr1);
1414
1415 /* fractional configuration: load sigma-delta modulator (SDM) */
1416
1417 /* Write into FRACV the new fractional value , and FRACLE to 0 */
1418 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1419 rcc + pll[pll_id].pllxfracr);
1420
1421 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1422 setbits_le32(rcc + pll[pll_id].pllxfracr,
1423 RCC_PLLNFRACR_FRACLE);
1424
1425 pll_config_output(priv, pll_id, pllcfg);
1426
1427 return 0;
1428}
1429
1430static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1431{
1432 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1433 u32 pllxcsg;
1434
1435 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1436 RCC_PLLNCSGR_MOD_PER_MASK) |
1437 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1438 RCC_PLLNCSGR_INC_STEP_MASK) |
1439 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1440 RCC_PLLNCSGR_SSCG_MODE_MASK);
1441
1442 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1443}
1444
1445static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1446{
1447 u32 address = priv->base + (clksrc >> 4);
1448 u32 val;
1449 int ret;
1450
1451 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1452 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1453 TIMEOUT_200MS);
1454 if (ret)
1455 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1456 clksrc, address, readl(address));
1457
1458 return ret;
1459}
1460
938e0e3f
PD		 1461static void stgen_config(struct stm32mp1_clk_priv *priv)
1462{
1463 int p;
1464 u32 stgenc, cntfid0;
1465 ulong rate;
1466
1467 stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1468
1469 cntfid0 = readl(stgenc + STGENC_CNTFID0);
1470 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1471 rate = stm32mp1_clk_get(priv, p);
1472
1473 if (cntfid0 != rate) {
1474 pr_debug("System Generic Counter (STGEN) update\n");
1475 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1476 writel(0x0, stgenc + STGENC_CNTCVL);
1477 writel(0x0, stgenc + STGENC_CNTCVU);
1478 writel(rate, stgenc + STGENC_CNTFID0);
1479 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1480
1481 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1482
1483 /* need to update gd->arch.timer_rate_hz with new frequency */
1484 timer_init();
1485 pr_debug("gd->arch.timer_rate_hz = %x\n",
1486 (u32)gd->arch.timer_rate_hz);
1487 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1488 }
1489}
1490
266fa4df
PD		 1491static int set_clkdiv(unsigned int clkdiv, u32 address)
1492{
1493 u32 val;
1494 int ret;
1495
1496 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1497 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1498 TIMEOUT_200MS);
1499 if (ret)
1500 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1501 clkdiv, address, readl(address));
1502
1503 return ret;
1504}
1505
1506static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1507 u32 clksrc, u32 clkdiv)
1508{
1509 u32 address = priv->base + (clksrc >> 4);
1510
1511 /*
1512 * binding clksrc : bit15-4 offset
1513 * bit3: disable
1514 * bit2-0: MCOSEL[2:0]
1515 */
1516 if (clksrc & 0x8) {
1517 clrbits_le32(address, RCC_MCOCFG_MCOON);
1518 } else {
1519 clrsetbits_le32(address,
1520 RCC_MCOCFG_MCOSRC_MASK,
1521 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1522 clrsetbits_le32(address,
1523 RCC_MCOCFG_MCODIV_MASK,
1524 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1525 setbits_le32(address, RCC_MCOCFG_MCOON);
1526 }
1527}
1528
1529static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1530 unsigned int clksrc,
1531 int lse_css)
1532{
1533 u32 address = priv->base + RCC_BDCR;
1534
1535 if (readl(address) & RCC_BDCR_RTCCKEN)
1536 goto skip_rtc;
1537
1538 if (clksrc == CLK_RTC_DISABLED)
1539 goto skip_rtc;
1540
1541 clrsetbits_le32(address,
1542 RCC_BDCR_RTCSRC_MASK,
1543 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1544
1545 setbits_le32(address, RCC_BDCR_RTCCKEN);
1546
1547skip_rtc:
1548 if (lse_css)
1549 setbits_le32(address, RCC_BDCR_LSECSSON);
1550}
1551
1552static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1553{
1554 u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1555 u32 value = pkcs & 0xF;
1556 u32 mask = 0xF;
1557
1558 if (pkcs & BIT(31)) {
1559 mask <<= 4;
1560 value <<= 4;
1561 }
1562 clrsetbits_le32(address, mask, value);
1563}
1564
1565static int stm32mp1_clktree(struct udevice *dev)
1566{
1567 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1568 fdt_addr_t rcc = priv->base;
1569 unsigned int clksrc[CLKSRC_NB];
1570 unsigned int clkdiv[CLKDIV_NB];
1571 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1572 ofnode plloff[_PLL_NB];
1573 int ret;
1574 int i, len;
1575 int lse_css = 0;
1576 const u32 *pkcs_cell;
1577
1578 /* check mandatory field */
1579 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1580 if (ret < 0) {
1581 debug("field st,clksrc invalid: error %d\n", ret);
1582 return -FDT_ERR_NOTFOUND;
1583 }
1584
1585 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1586 if (ret < 0) {
1587 debug("field st,clkdiv invalid: error %d\n", ret);
1588 return -FDT_ERR_NOTFOUND;
1589 }
1590
1591 /* check mandatory field in each pll */
1592 for (i = 0; i < _PLL_NB; i++) {
1593 char name[12];
1594
1595 sprintf(name, "st,pll@%d", i);
1596 plloff[i] = dev_read_subnode(dev, name);
1597 if (!ofnode_valid(plloff[i]))
1598 continue;
1599 ret = ofnode_read_u32_array(plloff[i], "cfg",
1600 pllcfg[i], PLLCFG_NB);
1601 if (ret < 0) {
1602 debug("field cfg invalid: error %d\n", ret);
1603 return -FDT_ERR_NOTFOUND;
1604 }
1605 }
1606
1607 debug("configuration MCO\n");
1608 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1609 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1610
1611 debug("switch ON osillator\n");
1612 /*
1613 * switch ON oscillator found in device-tree,
1614 * HSI already ON after bootrom
1615 */
1616 if (priv->osc[_LSI])
1617 stm32mp1_lsi_set(rcc, 1);
1618
1619 if (priv->osc[_LSE]) {
d2194155 1620 int bypass, digbyp, lsedrv;
266fa4df
PD		 1621 struct udevice *dev = priv->osc_dev[_LSE];
1622
1623 bypass = dev_read_bool(dev, "st,bypass");
d2194155 1624 digbyp = dev_read_bool(dev, "st,digbypass");
266fa4df
PD		 1625 lse_css = dev_read_bool(dev, "st,css");
1626 lsedrv = dev_read_u32_default(dev, "st,drive",
1627 LSEDRV_MEDIUM_HIGH);
1628
d2194155 1629 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
266fa4df
PD		 1630 }
1631
1632 if (priv->osc[_HSE]) {
d2194155 1633 int bypass, digbyp, css;
266fa4df
PD		 1634 struct udevice *dev = priv->osc_dev[_HSE];
1635
1636 bypass = dev_read_bool(dev, "st,bypass");
d2194155 1637 digbyp = dev_read_bool(dev, "st,digbypass");
266fa4df
PD		 1638 css = dev_read_bool(dev, "st,css");
1639
d2194155 1640 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
266fa4df
PD		 1641 }
1642 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1643 * => switch on CSI even if node is not present in device tree
1644 */
1645 stm32mp1_csi_set(rcc, 1);
1646
1647 /* come back to HSI */
1648 debug("come back to HSI\n");
1649 set_clksrc(priv, CLK_MPU_HSI);
1650 set_clksrc(priv, CLK_AXI_HSI);
1651 set_clksrc(priv, CLK_MCU_HSI);
1652
1653 debug("pll stop\n");
1654 for (i = 0; i < _PLL_NB; i++)
1655 pll_stop(priv, i);
1656
1657 /* configure HSIDIV */
1658 debug("configure HSIDIV\n");
938e0e3f 1659 if (priv->osc[_HSI]) {
266fa4df 1660 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
938e0e3f
PD		 1661 stgen_config(priv);
1662 }
266fa4df
PD		 1663
1664 /* select DIV */
1665 debug("select DIV\n");
1666 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1667 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1668 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1669 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1670 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1671 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1672 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1673 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1674 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1675
1676 /* no ready bit for RTC */
1677 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1678
1679 /* configure PLLs source */
1680 debug("configure PLLs source\n");
1681 set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1682 set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1683 set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1684
1685 /* configure and start PLLs */
1686 debug("configure PLLs\n");
1687 for (i = 0; i < _PLL_NB; i++) {
1688 u32 fracv;
1689 u32 csg[PLLCSG_NB];
1690
1691 debug("configure PLL %d @ %d\n", i,
1692 ofnode_to_offset(plloff[i]));
1693 if (!ofnode_valid(plloff[i]))
1694 continue;
1695
1696 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1697 pll_config(priv, i, pllcfg[i], fracv);
1698 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1699 if (!ret) {
1700 pll_csg(priv, i, csg);
1701 } else if (ret != -FDT_ERR_NOTFOUND) {
1702 debug("invalid csg node for pll@%d res=%d\n", i, ret);
1703 return ret;
1704 }
1705 pll_start(priv, i);
1706 }
1707
1708 /* wait and start PLLs ouptut when ready */
1709 for (i = 0; i < _PLL_NB; i++) {
1710 if (!ofnode_valid(plloff[i]))
1711 continue;
1712 debug("output PLL %d\n", i);
1713 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1714 }
1715
1716 /* wait LSE ready before to use it */
1717 if (priv->osc[_LSE])
1718 stm32mp1_lse_wait(rcc);
1719
1720 /* configure with expected clock source */
1721 debug("CLKSRC\n");
1722 set_clksrc(priv, clksrc[CLKSRC_MPU]);
1723 set_clksrc(priv, clksrc[CLKSRC_AXI]);
1724 set_clksrc(priv, clksrc[CLKSRC_MCU]);
1725 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1726
1727 /* configure PKCK */
1728 debug("PKCK\n");
1729 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1730 if (pkcs_cell) {
1731 bool ckper_disabled = false;
1732
1733 for (i = 0; i < len / sizeof(u32); i++) {
1734 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1735
1736 if (pkcs == CLK_CKPER_DISABLED) {
1737 ckper_disabled = true;
1738 continue;
1739 }
1740 pkcs_config(priv, pkcs);
1741 }
1742 /* CKPER is source for some peripheral clock
1743 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1744 * only if previous clock is still ON
1745 * => deactivated CKPER only after switching clock
1746 */
1747 if (ckper_disabled)
1748 pkcs_config(priv, CLK_CKPER_DISABLED);
1749 }
1750
938e0e3f
PD		 1751 /* STGEN clock source can change with CLK_STGEN_XXX */
1752 stgen_config(priv);
1753
266fa4df
PD		 1754 debug("oscillator off\n");
1755 /* switch OFF HSI if not found in device-tree */
1756 if (!priv->osc[_HSI])
1757 stm32mp1_hsi_set(rcc, 0);
1758
1759 /* Software Self-Refresh mode (SSR) during DDR initilialization */
1760 clrsetbits_le32(priv->base + RCC_DDRITFCR,
1761 RCC_DDRITFCR_DDRCKMOD_MASK,
1762 RCC_DDRITFCR_DDRCKMOD_SSR <<
1763 RCC_DDRITFCR_DDRCKMOD_SHIFT);
1764
1765 return 0;
1766}
1767#endif /* STM32MP1_CLOCK_TREE_INIT */
1768
88fa34df
PD		 1769static int pll_set_output_rate(struct udevice *dev,
1770 int pll_id,
1771 int div_id,
1772 unsigned long clk_rate)
1773{
1774 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1775 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1776 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1777 int div;
1778 ulong fvco;
1779
1780 if (div_id > _DIV_NB)
1781 return -EINVAL;
1782
1783 fvco = pll_get_fvco(priv, pll_id);
1784
1785 if (fvco <= clk_rate)
1786 div = 1;
1787 else
1788 div = DIV_ROUND_UP(fvco, clk_rate);
1789
1790 if (div > 128)
1791 div = 128;
1792
1793 debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1794 /* stop the requested output */
1795 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1796 /* change divider */
1797 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1798 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1799 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1800 /* start the requested output */
1801 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1802
1803 return 0;
1804}
1805
1806static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1807{
1808 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1809 int p;
1810
1811 switch (clk->id) {
1812 case LTDC_PX:
1813 case DSI_PX:
1814 break;
1815 default:
1816 pr_err("not supported");
1817 return -EINVAL;
1818 }
1819
1820 p = stm32mp1_clk_get_parent(priv, clk->id);
1821 if (p < 0)
1822 return -EINVAL;
1823
1824 switch (p) {
1825 case _PLL4_Q:
1826 /* for LTDC_PX and DSI_PX case */
1827 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1828 }
1829
1830 return -EINVAL;
1831}
1832
a6151916
PD		 1833static void stm32mp1_osc_clk_init(const char *name,
1834 struct stm32mp1_clk_priv *priv,
1835 int index)
1836{
1837 struct clk clk;
1838 struct udevice *dev = NULL;
1839
1840 priv->osc[index] = 0;
1841 clk.id = 0;
1842 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1843 if (clk_request(dev, &clk))
1844 pr_err("%s request", name);
1845 else
1846 priv->osc[index] = clk_get_rate(&clk);
1847 }
1848 priv->osc_dev[index] = dev;
1849}
1850
1851static void stm32mp1_osc_init(struct udevice *dev)
1852{
1853 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1854 int i;
1855 const char *name[NB_OSC] = {
1856 [_LSI] = "clk-lsi",
1857 [_LSE] = "clk-lse",
1858 [_HSI] = "clk-hsi",
1859 [_HSE] = "clk-hse",
1860 [_CSI] = "clk-csi",
1861 [_I2S_CKIN] = "i2s_ckin",
1862 [_USB_PHY_48] = "ck_usbo_48m"};
1863
1864 for (i = 0; i < NB_OSC; i++) {
1865 stm32mp1_osc_clk_init(name[i], priv, i);
1866 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1867 }
1868}
1869
1870static int stm32mp1_clk_probe(struct udevice *dev)
1871{
1872 int result = 0;
1873 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1874
1875 priv->base = dev_read_addr(dev->parent);
1876 if (priv->base == FDT_ADDR_T_NONE)
1877 return -EINVAL;
1878
1879 priv->data = (void *)&stm32mp1_data;
1880
1881 if (!priv->data->gate || !priv->data->sel ||
1882 !priv->data->pll)
1883 return -EINVAL;
1884
1885 stm32mp1_osc_init(dev);
1886
266fa4df
PD		 1887#ifdef STM32MP1_CLOCK_TREE_INIT
1888 /* clock tree init is done only one time, before relocation */
1889 if (!(gd->flags & GD_FLG_RELOC))
1890 result = stm32mp1_clktree(dev);
1891#endif
1892
a6151916
PD		 1893 return result;
1894}
1895
1896static const struct clk_ops stm32mp1_clk_ops = {
1897 .enable = stm32mp1_clk_enable,
1898 .disable = stm32mp1_clk_disable,
1899 .get_rate = stm32mp1_clk_get_rate,
88fa34df 1900 .set_rate = stm32mp1_clk_set_rate,
a6151916
PD		 1901};
1902
a6151916
PD		 1903U_BOOT_DRIVER(stm32mp1_clock) = {
1904 .name = "stm32mp1_clk",
1905 .id = UCLASS_CLK,
a6151916
PD		 1906 .ops = &stm32mp1_clk_ops,
1907 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1908 .probe = stm32mp1_clk_probe,
1909};
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