[thirdparty/u-boot.git] / drivers / clk / imx / clk.h

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2019 DENX Software Engineering
 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
 */
#ifndef __MACH_IMX_CLK_H
#define __MACH_IMX_CLK_H

#include <linux/clk-provider.h>

enum imx_pllv3_type {
	IMX_PLLV3_GENERIC,
	IMX_PLLV3_SYS,
	IMX_PLLV3_USB,
	IMX_PLLV3_USB_VF610,
	IMX_PLLV3_AV,
	IMX_PLLV3_ENET,
	IMX_PLLV3_ENET_IMX7,
	IMX_PLLV3_SYS_VF610,
	IMX_PLLV3_DDR_IMX7,
};

struct clk *clk_register_gate2(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 bit_idx, u8 cgr_val,
		u8 clk_gate_flags);

struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
			  const char *parent_name, void __iomem *base,
			  u32 div_mask);

static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
					void __iomem *reg, u8 shift)
{
	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
			shift, 0x3, 0);
}

static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
		void __iomem *reg, u8 shift)
{
	return clk_register_gate2(NULL, name, parent,
			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
			reg, shift, 0x3, 0);
}

static inline struct clk *imx_clk_gate4_flags(const char *name,
		const char *parent, void __iomem *reg, u8 shift,
		unsigned long flags)
{
	return clk_register_gate2(NULL, name, parent,
			flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
			reg, shift, 0x3, 0);
}

static inline struct clk *imx_clk_fixed_factor(const char *name,
		const char *parent, unsigned int mult, unsigned int div)
{
	return clk_register_fixed_factor(NULL, name, parent,
			CLK_SET_RATE_PARENT, mult, div);
}

static inline struct clk *imx_clk_divider(const char *name, const char *parent,
		void __iomem *reg, u8 shift, u8 width)
{
	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
			reg, shift, width, 0);
}

static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
		void __iomem *reg, u8 shift, u8 width)
{
	return clk_register_divider(NULL, name, parent,
			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
			reg, shift, width, 0);
}

struct clk *imx_clk_pfd(const char *name, const char *parent_name,
			void __iomem *reg, u8 idx);

struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
			      u8 shift, u8 width, const char * const *parents,
			      int num_parents, void (*fixup)(u32 *val));

static inline struct clk *imx_clk_mux_flags(const char *name,
			void __iomem *reg, u8 shift, u8 width,
			const char * const *parents, int num_parents,
			unsigned long flags)
{
	return clk_register_mux(NULL, name, parents, num_parents,
				flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
				width, 0);
}

static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
			u8 shift, u8 width, const char * const *parents,
			int num_parents)
{
	return clk_register_mux(NULL, name, parents, num_parents,
			CLK_SET_RATE_NO_REPARENT, reg, shift,
			width, 0);
}

static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
			u8 shift, u8 width, const char * const *parents,
			int num_parents)
{
	return clk_register_mux(NULL, name, parents, num_parents,
			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
			reg, shift, width, 0);
}

static inline struct clk *imx_clk_gate(const char *name, const char *parent,
		void __iomem *reg, u8 shift)
{
	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
			shift, 0, NULL);
}

static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
		void __iomem *reg, u8 shift, unsigned long flags)
{
	return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
			shift, 0, NULL);
}

static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
		void __iomem *reg, u8 shift)
{
	return clk_register_gate(NULL, name, parent,
			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
			reg, shift, 0, NULL);
}

struct clk *imx8m_clk_composite_flags(const char *name,
		const char * const *parent_names,
		int num_parents, void __iomem *reg, unsigned long flags);

#define __imx8m_clk_composite(name, parent_names, reg, flags) \
	imx8m_clk_composite_flags(name, parent_names, \
		ARRAY_SIZE(parent_names), reg, \
		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)

#define imx8m_clk_composite(name, parent_names, reg) \
	__imx8m_clk_composite(name, parent_names, reg, 0)

#define imx8m_clk_composite_critical(name, parent_names, reg) \
	__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)

#endif /* __MACH_IMX_CLK_H */
Commit	Line	Data
1d7993d1 LM	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2019 DENX Software Engineering
	4	* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
	5	*/
	6	#ifndef __MACH_IMX_CLK_H
	7	#define __MACH_IMX_CLK_H
	8
	9	#include <linux/clk-provider.h>
	10
	11	enum imx_pllv3_type {
	12	IMX_PLLV3_GENERIC,
	13	IMX_PLLV3_SYS,
	14	IMX_PLLV3_USB,
	15	IMX_PLLV3_USB_VF610,
	16	IMX_PLLV3_AV,
	17	IMX_PLLV3_ENET,
	18	IMX_PLLV3_ENET_IMX7,
	19	IMX_PLLV3_SYS_VF610,
	20	IMX_PLLV3_DDR_IMX7,
	21	};
	22
	23	struct clk clk_register_gate2(struct device dev, const char *name,
	24	const char *parent_name, unsigned long flags,
	25	void __iomem *reg, u8 bit_idx, u8 cgr_val,
	26	u8 clk_gate_flags);
	27
	28	struct clk imx_clk_pllv3(enum imx_pllv3_type type, const char name,
	29	const char parent_name, void __iomem base,
	30	u32 div_mask);
	31
	32	static inline struct clk imx_clk_gate2(const char name, const char *parent,
	33	void __iomem *reg, u8 shift)
	34	{
	35	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
	36	shift, 0x3, 0);
	37	}
	38
b6c56d90 PF	39	static inline struct clk imx_clk_gate4(const char name, const char *parent,
	40	void __iomem *reg, u8 shift)
	41	{
	42	return clk_register_gate2(NULL, name, parent,
	43	CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	44	reg, shift, 0x3, 0);
	45	}
	46
	47	static inline struct clk imx_clk_gate4_flags(const char name,
	48	const char parent, void __iomem reg, u8 shift,
	49	unsigned long flags)
	50	{
	51	return clk_register_gate2(NULL, name, parent,
	52	flags \| CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	53	reg, shift, 0x3, 0);
	54	}
	55
1d7993d1 LM	56	static inline struct clk imx_clk_fixed_factor(const char name,
	57	const char *parent, unsigned int mult, unsigned int div)
	58	{
	59	return clk_register_fixed_factor(NULL, name, parent,
	60	CLK_SET_RATE_PARENT, mult, div);
	61	}
	62
	63	static inline struct clk imx_clk_divider(const char name, const char *parent,
	64	void __iomem *reg, u8 shift, u8 width)
	65	{
	66	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
	67	reg, shift, width, 0);
	68	}
	69
b6c56d90 PF	70	static inline struct clk imx_clk_divider2(const char name, const char *parent,
	71	void __iomem *reg, u8 shift, u8 width)
	72	{
	73	return clk_register_divider(NULL, name, parent,
	74	CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	75	reg, shift, width, 0);
	76	}
	77
1d7993d1 LM	78	struct clk imx_clk_pfd(const char name, const char *parent_name,
	79	void __iomem *reg, u8 idx);
	80
	81	struct clk imx_clk_fixup_mux(const char name, void __iomem *reg,
	82	u8 shift, u8 width, const char * const *parents,
	83	int num_parents, void (fixup)(u32 val));
	84
b6c56d90 PF	85	static inline struct clk imx_clk_mux_flags(const char name,
	86	void __iomem *reg, u8 shift, u8 width,
	87	const char * const *parents, int num_parents,
	88	unsigned long flags)
	89	{
	90	return clk_register_mux(NULL, name, parents, num_parents,
	91	flags \| CLK_SET_RATE_NO_REPARENT, reg, shift,
	92	width, 0);
	93	}
	94
1d7993d1 LM	95	static inline struct clk imx_clk_mux(const char name, void __iomem *reg,
	96	u8 shift, u8 width, const char * const *parents,
	97	int num_parents)
	98	{
	99	return clk_register_mux(NULL, name, parents, num_parents,
	100	CLK_SET_RATE_NO_REPARENT, reg, shift,
	101	width, 0);
	102	}
	103
b6c56d90 PF	104	static inline struct clk imx_clk_mux2(const char name, void __iomem *reg,
	105	u8 shift, u8 width, const char * const *parents,
	106	int num_parents)
	107	{
	108	return clk_register_mux(NULL, name, parents, num_parents,
	109	CLK_SET_RATE_NO_REPARENT \| CLK_OPS_PARENT_ENABLE,
	110	reg, shift, width, 0);
	111	}
	112
	113	static inline struct clk imx_clk_gate(const char name, const char *parent,
	114	void __iomem *reg, u8 shift)
	115	{
	116	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
	117	shift, 0, NULL);
	118	}
	119
	120	static inline struct clk imx_clk_gate_flags(const char name, const char *parent,
	121	void __iomem *reg, u8 shift, unsigned long flags)
	122	{
	123	return clk_register_gate(NULL, name, parent, flags \| CLK_SET_RATE_PARENT, reg,
	124	shift, 0, NULL);
	125	}
	126
	127	static inline struct clk imx_clk_gate3(const char name, const char *parent,
	128	void __iomem *reg, u8 shift)
	129	{
	130	return clk_register_gate(NULL, name, parent,
	131	CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	132	reg, shift, 0, NULL);
	133	}
	134
	135	struct clk imx8m_clk_composite_flags(const char name,
	136	const char * const *parent_names,
	137	int num_parents, void __iomem *reg, unsigned long flags);
	138
	139	#define __imx8m_clk_composite(name, parent_names, reg, flags) \
	140	imx8m_clk_composite_flags(name, parent_names, \
	141	ARRAY_SIZE(parent_names), reg, \
	142	flags \| CLK_SET_RATE_NO_REPARENT \| CLK_OPS_PARENT_ENABLE)
	143
	144	#define imx8m_clk_composite(name, parent_names, reg) \
	145	__imx8m_clk_composite(name, parent_names, reg, 0)
	146
	147	#define imx8m_clk_composite_critical(name, parent_names, reg) \
	148	__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
	149
1d7993d1	150	#endif /* __MACH_IMX_CLK_H */