[people/ms/linux.git] / drivers / clk / pxa / clk-pxa25x.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Marvell PXA25x family clocks
 *
 * Copyright (C) 2014 Robert Jarzmik
 *
 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
 *
 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
 * should go away.
 */
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/soc/pxa/smemc.h>

#include <dt-bindings/clock/pxa-clock.h>
#include "clk-pxa.h"
#include "clk-pxa2xx.h"

#define KHz 1000
#define MHz (1000 * 1000)

enum {
	PXA_CORE_RUN = 0,
	PXA_CORE_TURBO,
};

#define PXA25x_CLKCFG(T)			\
	(CLKCFG_FCS |				\
	 ((T) ? CLKCFG_TURBO : 0))
#define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)

/* Define the refresh period in mSec for the SDRAM and the number of rows */
#define SDRAM_TREF	64	/* standard 64ms SDRAM */

/*
 * Various clock factors driven by the CCCR register.
 */
static void __iomem *clk_regs;

/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };

/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };

/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };

static const char * const get_freq_khz[] = {
	"core", "run", "cpll", "memory"
};

static u32 mdrefr_dri(unsigned int freq_khz)
{
	u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();

	return interval / 32;
}

/*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa25x_get_clk_frequency_khz(int info)
{
	struct clk *clk;
	unsigned long clks[5];
	int i;

	for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
		clk = clk_get(NULL, get_freq_khz[i]);
		if (IS_ERR(clk)) {
			clks[i] = 0;
		} else {
			clks[i] = clk_get_rate(clk);
			clk_put(clk);
		}
	}

	if (info) {
		pr_info("Run Mode clock: %ld.%02ldMHz\n",
			clks[1] / 1000000, (clks[1] % 1000000) / 10000);
		pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
			clks[2] / 1000000, (clks[2] % 1000000) / 10000);
		pr_info("Memory clock: %ld.%02ldMHz\n",
			clks[3] / 1000000, (clks[3] % 1000000) / 10000);
	}

	return (unsigned int)clks[0] / KHz;
}

static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	unsigned long cccr = readl(clk_regs + CCCR);
	unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];

	return parent_rate / m;
}
PARENTS(clk_pxa25x_memory) = { "run" };
RATE_RO_OPS(clk_pxa25x_memory, "memory");

PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };

#define PXA25X_CKEN(dev_id, con_id, parents, mult, div,			\
		    bit, is_lp, flags)					\
	PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div,	\
		 is_lp,  CKEN, CKEN_ ## bit, flags)
#define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)	\
	PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp,	\
		    div_hp, bit, NULL, 0)
#define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
	PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp,	\
		    div_hp, bit, NULL, 0)
#define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)	\
	PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp,	\
		    div_hp, bit, NULL, 0)

#define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)		\
	PXA_CKEN_1RATE(dev_id, con_id, bit, parents,			\
		       CKEN, CKEN_ ## bit, 0)
#define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)	\
	PXA_CKEN_1RATE(dev_id, con_id, bit, parents,			\
		       CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)

static struct desc_clk_cken pxa25x_clocks[] __initdata = {
	PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
	PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
	PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
	PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
	PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
	PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
	PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
	PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
	PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
	PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
	PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
	PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
	PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
	PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
	PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),

	PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
	PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
			     clk_pxa25x_memory_parents, 0),
};

/*
 * In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
 *   - freq_cpll = n * m * L * 3.6864 MHz
 *   - n = N2 / 2
 *   - m = 2^(M - 1), where 1 <= M <= 3
 *   - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
 */
static struct pxa2xx_freq pxa25x_freqs[] = {
	/* CPU  MEMBUS  CCCR                  DIV2 CCLKCFG      */
	{ 99532800, 99500, PXA25x_CCCR(2,  1, 1),  1, PXA25x_CLKCFG(1)},
	{199065600, 99500, PXA25x_CCCR(4,  1, 1),  0, PXA25x_CLKCFG(1)},
	{298598400, 99500, PXA25x_CCCR(3,  2, 1),  0, PXA25x_CLKCFG(1)},
	{398131200, 99500, PXA25x_CCCR(4,  2, 1),  0, PXA25x_CLKCFG(1)},
};

static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
{
	unsigned long clkcfg;
	unsigned int t;

	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	t  = clkcfg & (1 << 0);
	if (t)
		return PXA_CORE_TURBO;
	return PXA_CORE_RUN;
}

static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
{
	if (index > PXA_CORE_TURBO)
		return -EINVAL;

	pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);

	return 0;
}

static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
					  struct clk_rate_request *req)
{
	return __clk_mux_determine_rate(hw, req);
}

PARENTS(clk_pxa25x_core) = { "run", "cpll" };
MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);

static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
					     unsigned long parent_rate)
{
	unsigned long cccr = readl(clk_regs + CCCR);
	unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];

	return (parent_rate / n2) * 2;
}
PARENTS(clk_pxa25x_run) = { "cpll" };
RATE_RO_OPS(clk_pxa25x_run, "run");

static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
	unsigned long parent_rate)
{
	unsigned long clkcfg, cccr = readl(clk_regs + CCCR);
	unsigned int l, m, n2, t;

	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	t = clkcfg & (1 << 0);
	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
	m = M_clk_mult[(cccr >> 5) & 0x03];
	n2 = N2_clk_mult[(cccr >> 7) & 0x07];

	return m * l * n2 * parent_rate / 2;
}

static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
					  struct clk_rate_request *req)
{
	return pxa2xx_determine_rate(req, pxa25x_freqs,
				     ARRAY_SIZE(pxa25x_freqs));
}

static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate)
{
	int i;

	pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
	for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
		if (pxa25x_freqs[i].cpll == rate)
			break;

	if (i >= ARRAY_SIZE(pxa25x_freqs))
		return -EINVAL;

	pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR);

	return 0;
}
PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
RATE_OPS(clk_pxa25x_cpll, "cpll");

static void __init pxa25x_register_core(void)
{
	clkdev_pxa_register(CLK_NONE, "cpll", NULL,
			    clk_register_clk_pxa25x_cpll());
	clkdev_pxa_register(CLK_NONE, "run", NULL,
			    clk_register_clk_pxa25x_run());
	clkdev_pxa_register(CLK_CORE, "core", NULL,
			    clk_register_clk_pxa25x_core());
}

static void __init pxa25x_register_plls(void)
{
	clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
				CLK_GET_RATE_NOCACHE, 3686400);
	clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
			    clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
						    CLK_GET_RATE_NOCACHE,
						    32768));
	clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
	clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
				  0, 26, 1);
	clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
				  0, 40, 1);
}

static void __init pxa25x_base_clocks_init(void)
{
	pxa25x_register_plls();
	pxa25x_register_core();
	clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
			    clk_register_clk_pxa25x_memory());
}

#define DUMMY_CLK(_con_id, _dev_id, _parent) \
	{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
struct dummy_clk {
	const char *con_id;
	const char *dev_id;
	const char *parent;
};
static struct dummy_clk dummy_clks[] __initdata = {
	DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
	DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
	DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
	DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
	DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
	DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
	DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
};

static void __init pxa25x_dummy_clocks_init(void)
{
	struct clk *clk;
	struct dummy_clk *d;
	const char *name;
	int i;

	/*
	 * All pinctrl logic has been wiped out of the clock driver, especially
	 * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
	 * control (ie. pxa2xx_mfp_config() invocation).
	 */
	for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
		d = &dummy_clks[i];
		name = d->dev_id ? d->dev_id : d->con_id;
		clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
		clk_register_clkdev(clk, d->con_id, d->dev_id);
	}
}

int __init pxa25x_clocks_init(void __iomem *regs)
{
	clk_regs = regs;
	pxa25x_base_clocks_init();
	pxa25x_dummy_clocks_init();
	return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks), clk_regs);
}

static void __init pxa25x_dt_clocks_init(struct device_node *np)
{
	pxa25x_clocks_init(ioremap(0x41300000ul, 0x10));
	clk_pxa_dt_common_init(np);
}
CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
	       pxa25x_dt_clocks_init);
Commit	Line	Data
b886d83c	1	// SPDX-License-Identifier: GPL-2.0-only
fe7710fa RJ	2	/*
	3	* Marvell PXA25x family clocks
	4	*
	5	* Copyright (C) 2014 Robert Jarzmik
	6	*
	7	* Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
	8	*
fe7710fa RJ	9	* For non-devicetree platforms. Once pxa is fully converted to devicetree, this
	10	* should go away.
	11	*/
	12	#include <linux/clk-provider.h>
	13	#include <linux/clk.h>
	14	#include <linux/clkdev.h>
	15	#include <linux/io.h>
	16	#include <linux/of.h>
fd13f811	17	#include <linux/soc/pxa/smemc.h>
fe7710fa RJ	18
	19	#include <dt-bindings/clock/pxa-clock.h>
	20	#include "clk-pxa.h"
3c816d95	21	#include "clk-pxa2xx.h"
fe7710fa RJ	22
	23	#define KHz 1000
	24	#define MHz (1000 * 1000)
	25
	26	enum {
	27	PXA_CORE_RUN = 0,
	28	PXA_CORE_TURBO,
	29	};
	30
9fe69429 RJ	31	#define PXA25x_CLKCFG(T) \
	32	(CLKCFG_FCS \| \
	33	((T) ? CLKCFG_TURBO : 0))
	34	#define PXA25x_CCCR(N2, M, L) (N2 << 7 \| M << 5 \| L)
	35
9fe69429 RJ	36	/* Define the refresh period in mSec for the SDRAM and the number of rows */
	37	#define SDRAM_TREF 64 /* standard 64ms SDRAM */
	38
fe7710fa RJ	39	/*
	40	* Various clock factors driven by the CCCR register.
	41	*/
3c816d95	42	static void __iomem *clk_regs;
fe7710fa RJ	43
	44	/* Crystal Frequency to Memory Frequency Multiplier (L) */
	45	static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
	46
	47	/* Memory Frequency to Run Mode Frequency Multiplier (M) */
	48	static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
	49
	50	/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
	51	/* Note: we store the value N * 2 here. */
	52	static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
	53
	54	static const char * const get_freq_khz[] = {
	55	"core", "run", "cpll", "memory"
	56	};
	57
9fe69429 RJ	58	static u32 mdrefr_dri(unsigned int freq_khz)
9fe69429 RJ	59	{
fd13f811	60	u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
9fe69429 RJ	61
	62	return interval / 32;
	63	}
	64
fe7710fa RJ	65	/*
	66	* Get the clock frequency as reflected by CCCR and the turbo flag.
	67	* We assume these values have been applied via a fcs.
	68	* If info is not 0 we also display the current settings.
	69	*/
	70	unsigned int pxa25x_get_clk_frequency_khz(int info)
	71	{
	72	struct clk *clk;
	73	unsigned long clks[5];
	74	int i;
	75
	76	for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
	77	clk = clk_get(NULL, get_freq_khz[i]);
	78	if (IS_ERR(clk)) {
	79	clks[i] = 0;
	80	} else {
	81	clks[i] = clk_get_rate(clk);
	82	clk_put(clk);
	83	}
	84	}
	85
	86	if (info) {
	87	pr_info("Run Mode clock: %ld.%02ldMHz\n",
	88	clks[1] / 1000000, (clks[1] % 1000000) / 10000);
	89	pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
	90	clks[2] / 1000000, (clks[2] % 1000000) / 10000);
	91	pr_info("Memory clock: %ld.%02ldMHz\n",
	92	clks[3] / 1000000, (clks[3] % 1000000) / 10000);
	93	}
	94
4b5fb7dc	95	return (unsigned int)clks[0] / KHz;
fe7710fa RJ	96	}
	97
	98	static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
	99	unsigned long parent_rate)
	100	{
3c816d95	101	unsigned long cccr = readl(clk_regs + CCCR);
fe7710fa RJ	102	unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
	103
	104	return parent_rate / m;
	105	}
	106	PARENTS(clk_pxa25x_memory) = { "run" };
	107	RATE_RO_OPS(clk_pxa25x_memory, "memory");
	108
	109	PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
	110	PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
	111	PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
	112
	113	#define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \
	114	bit, is_lp, flags) \
	115	PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
ea7743e2	116	is_lp, CKEN, CKEN_ ## bit, flags)
fe7710fa RJ	117	#define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
	118	PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \
	119	div_hp, bit, NULL, 0)
	120	#define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
	121	PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \
	122	div_hp, bit, NULL, 0)
	123	#define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
	124	PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \
	125	div_hp, bit, NULL, 0)
	126
	127	#define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
	128	PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
ea7743e2	129	CKEN, CKEN_ ## bit, 0)
fe7710fa RJ	130	#define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
fe7710fa RJ	131	PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
ea7743e2	132	CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
fe7710fa RJ	133
	134	static struct desc_clk_cken pxa25x_clocks[] __initdata = {
	135	PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
	136	PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
	137	PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
	138	PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
	139	PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
	140	PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
	141	PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
	142	PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
	143	PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
	144	PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
	145	PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
	146	PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
	147	PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
	148	PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
	149	PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
	150
	151	PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
	152	PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
	153	clk_pxa25x_memory_parents, 0),
	154	};
	155
9fe69429 RJ	156	/*
	157	* In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
	158	* - freq_cpll = n * m * L * 3.6864 MHz
	159	* - n = N2 / 2
	160	* - m = 2^(M - 1), where 1 <= M <= 3
	161	* - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
	162	*/
	163	static struct pxa2xx_freq pxa25x_freqs[] = {
	164	/* CPU MEMBUS CCCR DIV2 CCLKCFG */
	165	{ 99532800, 99500, PXA25x_CCCR(2, 1, 1), 1, PXA25x_CLKCFG(1)},
	166	{199065600, 99500, PXA25x_CCCR(4, 1, 1), 0, PXA25x_CLKCFG(1)},
	167	{298598400, 99500, PXA25x_CCCR(3, 2, 1), 0, PXA25x_CLKCFG(1)},
	168	{398131200, 99500, PXA25x_CCCR(4, 2, 1), 0, PXA25x_CLKCFG(1)},
	169	};
	170
fe7710fa RJ	171	static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
	172	{
	173	unsigned long clkcfg;
	174	unsigned int t;
	175
	176	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	177	t = clkcfg & (1 << 0);
	178	if (t)
	179	return PXA_CORE_TURBO;
	180	return PXA_CORE_RUN;
	181	}
	182
9fe69429	183	static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
fe7710fa	184	{
9fe69429 RJ	185	if (index > PXA_CORE_TURBO)
	186	return -EINVAL;
	187
	188	pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
	189
	190	return 0;
fe7710fa	191	}
9fe69429 RJ	192
	193	static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
	194	struct clk_rate_request *req)
	195	{
	196	return __clk_mux_determine_rate(hw, req);
	197	}
	198
fe7710fa	199	PARENTS(clk_pxa25x_core) = { "run", "cpll" };
9fe69429	200	MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);
fe7710fa RJ	201
	202	static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
	203	unsigned long parent_rate)
	204	{
3c816d95	205	unsigned long cccr = readl(clk_regs + CCCR);
fe7710fa RJ	206	unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
	207
	208	return (parent_rate / n2) * 2;
	209	}
	210	PARENTS(clk_pxa25x_run) = { "cpll" };
	211	RATE_RO_OPS(clk_pxa25x_run, "run");
	212
	213	static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
	214	unsigned long parent_rate)
	215	{
3c816d95	216	unsigned long clkcfg, cccr = readl(clk_regs + CCCR);
fe7710fa RJ	217	unsigned int l, m, n2, t;
	218
	219	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
	220	t = clkcfg & (1 << 0);
	221	l = L_clk_mult[(cccr >> 0) & 0x1f];
	222	m = M_clk_mult[(cccr >> 5) & 0x03];
	223	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
	224
26bd423b	225	return m * l * n2 * parent_rate / 2;
fe7710fa	226	}
9fe69429 RJ	227
	228	static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
	229	struct clk_rate_request *req)
	230	{
	231	return pxa2xx_determine_rate(req, pxa25x_freqs,
	232	ARRAY_SIZE(pxa25x_freqs));
	233	}
	234
	235	static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
	236	unsigned long parent_rate)
	237	{
	238	int i;
	239
	240	pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
	241	for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
	242	if (pxa25x_freqs[i].cpll == rate)
	243	break;
	244
	245	if (i >= ARRAY_SIZE(pxa25x_freqs))
	246	return -EINVAL;
	247
3c816d95	248	pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR);
9fe69429 RJ	249
	250	return 0;
	251	}
fe7710fa	252	PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
9fe69429	253	RATE_OPS(clk_pxa25x_cpll, "cpll");
fe7710fa RJ	254
	255	static void __init pxa25x_register_core(void)
	256	{
fb16d9e5 RJ	257	clkdev_pxa_register(CLK_NONE, "cpll", NULL,
	258	clk_register_clk_pxa25x_cpll());
	259	clkdev_pxa_register(CLK_NONE, "run", NULL,
	260	clk_register_clk_pxa25x_run());
fe7710fa RJ	261	clkdev_pxa_register(CLK_CORE, "core", NULL,
	262	clk_register_clk_pxa25x_core());
	263	}
	264
	265	static void __init pxa25x_register_plls(void)
	266	{
	267	clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
2c63935d	268	CLK_GET_RATE_NOCACHE, 3686400);
fc206543 RJ	269	clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
	270	clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
	271	CLK_GET_RATE_NOCACHE,
	272	32768));
2c63935d	273	clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
fe7710fa RJ	274	clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
	275	0, 26, 1);
	276	clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
	277	0, 40, 1);
	278	}
	279
	280	static void __init pxa25x_base_clocks_init(void)
	281	{
	282	pxa25x_register_plls();
	283	pxa25x_register_core();
fb16d9e5 RJ	284	clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
fb16d9e5 RJ	285	clk_register_clk_pxa25x_memory());
fe7710fa RJ	286	}
	287
	288	#define DUMMY_CLK(_con_id, _dev_id, _parent) \
	289	{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
	290	struct dummy_clk {
	291	const char *con_id;
	292	const char *dev_id;
	293	const char *parent;
	294	};
	295	static struct dummy_clk dummy_clks[] __initdata = {
	296	DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
	297	DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
	298	DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
	299	DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
	300	DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
a758c9b9	301	DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
fe7710fa RJ	302	DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
	303	};
	304
	305	static void __init pxa25x_dummy_clocks_init(void)
	306	{
	307	struct clk *clk;
	308	struct dummy_clk *d;
	309	const char *name;
	310	int i;
	311
	312	/*
	313	* All pinctrl logic has been wiped out of the clock driver, especially
	314	* for gpio11 and gpio12 outputs. Machine code should ensure proper pin
	315	* control (ie. pxa2xx_mfp_config() invocation).
	316	*/
	317	for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
	318	d = &dummy_clks[i];
	319	name = d->dev_id ? d->dev_id : d->con_id;
	320	clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
	321	clk_register_clkdev(clk, d->con_id, d->dev_id);
	322	}
	323	}
	324
3c816d95	325	int __init pxa25x_clocks_init(void __iomem *regs)
fe7710fa	326	{
3c816d95	327	clk_regs = regs;
fe7710fa RJ	328	pxa25x_base_clocks_init();
fe7710fa RJ	329	pxa25x_dummy_clocks_init();
3c816d95	330	return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks), clk_regs);
fe7710fa RJ	331	}
	332
	333	static void __init pxa25x_dt_clocks_init(struct device_node *np)
	334	{
3c816d95	335	pxa25x_clocks_init(ioremap(0x41300000ul, 0x10));
fe7710fa RJ	336	clk_pxa_dt_common_init(np);
	337	}
	338	CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
	339	pxa25x_dt_clocks_init);