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clk: renesas: Split RCar Gen3 driver
[people/ms/u-boot.git] / drivers / clk / renesas / clk-rcar-gen3.c
CommitLineData
36c2ee4c 1/*
7691ff2a 2 * Renesas RCar Gen3 CPG MSSR driver
36c2ee4c
MV		 3 *
4 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
8 *
9 * Copyright (C) 2016 Glider bvba
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#include <common.h>
15#include <clk-uclass.h>
16#include <dm.h>
17#include <errno.h>
18#include <wait_bit.h>
19#include <asm/io.h>
20
f77b5a4c
MV		 21#include <dt-bindings/clock/renesas-cpg-mssr.h>
22
23#include "renesas-cpg-mssr.h"
36c2ee4c
MV		 24
25#define CPG_RST_MODEMR 0x0060
26
27#define CPG_PLL0CR 0x00d8
28#define CPG_PLL2CR 0x002c
29#define CPG_PLL4CR 0x01f4
30
849ab0a6
MV		 31#define CPG_RPC_PREDIV_MASK 0x3
32#define CPG_RPC_PREDIV_OFFSET 3
33#define CPG_RPC_POSTDIV_MASK 0x7
34#define CPG_RPC_POSTDIV_OFFSET 0
35
36c2ee4c
MV		 36/*
37 * Module Standby and Software Reset register offets.
38 *
39 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
40 * R-Car Gen2, R-Car Gen3, and RZ/G1.
41 * These are NOT valid for R-Car Gen1 and RZ/A1!
42 */
43
44/*
45 * Module Stop Status Register offsets
46 */
47
48static const u16 mstpsr[] = {
49 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
50 0x9A0, 0x9A4, 0x9A8, 0x9AC,
51};
52
53#define MSTPSR(i) mstpsr[i]
54
55
56/*
57 * System Module Stop Control Register offsets
58 */
59
60static const u16 smstpcr[] = {
61 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
62 0x990, 0x994, 0x998, 0x99C,
63};
64
65#define SMSTPCR(i) smstpcr[i]
66
67
68/* Realtime Module Stop Control Register offsets */
69#define RMSTPCR(i) (smstpcr[i] - 0x20)
70
71/* Modem Module Stop Control Register offsets (r8a73a4) */
72#define MMSTPCR(i) (smstpcr[i] + 0x20)
73
74/* Software Reset Clearing Register offsets */
75#define SRSTCLR(i) (0x940 + (i) * 4)
76
36c2ee4c
MV		 77/*
78 * CPG Clock Data
79 */
80
81/*
82 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
83 * 14 13 19 17 (MHz)
84 *-------------------------------------------------------------------
85 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
86 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
87 * 0 0 1 0 Prohibited setting
88 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
89 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
90 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
91 * 0 1 1 0 Prohibited setting
92 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
93 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
94 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
95 * 1 0 1 0 Prohibited setting
96 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
97 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
98 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
99 * 1 1 1 0 Prohibited setting
100 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
101 */
102#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
103 (((md) & BIT(13)) >> 11) | \
104 (((md) & BIT(19)) >> 18) | \
105 (((md) & BIT(17)) >> 17))
106
107static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
108 /* EXTAL div PLL1 mult PLL3 mult */
109 { 1, 192, 192, },
110 { 1, 192, 128, },
111 { 0, /* Prohibited setting */ },
112 { 1, 192, 192, },
113 { 1, 160, 160, },
114 { 1, 160, 106, },
115 { 0, /* Prohibited setting */ },
116 { 1, 160, 160, },
117 { 1, 128, 128, },
118 { 1, 128, 84, },
119 { 0, /* Prohibited setting */ },
120 { 1, 128, 128, },
121 { 2, 192, 192, },
122 { 2, 192, 128, },
123 { 0, /* Prohibited setting */ },
124 { 2, 192, 192, },
125};
126
127/*
128 * SDn Clock
129 */
130#define CPG_SD_STP_HCK BIT(9)
131#define CPG_SD_STP_CK BIT(8)
132
133#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
134#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
135
136#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
137{ \
138 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
139 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
140 ((sd_srcfc) << 2) | \
141 ((sd_fc) << 0), \
142 .div = (sd_div), \
143}
144
145struct sd_div_table {
146 u32 val;
147 unsigned int div;
148};
149
150/* SDn divider
151 * sd_srcfc sd_fc div
152 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
153 *-------------------------------------------------------------------
154 * 0 0 0 (1) 1 (4) 4
155 * 0 0 1 (2) 1 (4) 8
156 * 1 0 2 (4) 1 (4) 16
157 * 1 0 3 (8) 1 (4) 32
158 * 1 0 4 (16) 1 (4) 64
159 * 0 0 0 (1) 0 (2) 2
160 * 0 0 1 (2) 0 (2) 4
161 * 1 0 2 (4) 0 (2) 8
162 * 1 0 3 (8) 0 (2) 16
163 * 1 0 4 (16) 0 (2) 32
164 */
165static const struct sd_div_table cpg_sd_div_table[] = {
166/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
167 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
168 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
169 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
170 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
171 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
172 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
173 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
174 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
175 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
176 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
177};
178
179static bool gen3_clk_is_mod(struct clk *clk)
180{
181 return (clk->id >> 16) == CPG_MOD;
182}
183
184static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
185{
186 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
f77b5a4c 187 struct cpg_mssr_info *info = priv->info;
36c2ee4c
MV		 188 const unsigned long clkid = clk->id & 0xffff;
189 int i;
190
191 if (!gen3_clk_is_mod(clk))
192 return -EINVAL;
193
f77b5a4c
MV		 194 for (i = 0; i < info->mod_clk_size; i++) {
195 if (info->mod_clk[i].id != MOD_CLK_ID(clkid))
36c2ee4c
MV		 196 continue;
197
f77b5a4c 198 *mssr = &info->mod_clk[i];
36c2ee4c
MV		 199 return 0;
200 }
201
202 return -ENODEV;
203}
204
205static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core)
206{
fd8692b8 207 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
f77b5a4c 208 struct cpg_mssr_info *info = priv->info;
36c2ee4c
MV		 209 const unsigned long clkid = clk->id & 0xffff;
210 int i;
211
212 if (gen3_clk_is_mod(clk))
213 return -EINVAL;
214
f77b5a4c
MV		 215 for (i = 0; i < info->core_clk_size; i++) {
216 if (info->core_clk[i].id != clkid)
36c2ee4c
MV		 217 continue;
218
f77b5a4c 219 *core = &info->core_clk[i];
36c2ee4c
MV		 220 return 0;
221 }
222
223 return -ENODEV;
224}
225
226static int gen3_clk_get_parent(struct clk *clk, struct clk *parent)
227{
228 const struct cpg_core_clk *core;
229 const struct mssr_mod_clk *mssr;
230 int ret;
231
232 if (gen3_clk_is_mod(clk)) {
233 ret = gen3_clk_get_mod(clk, &mssr);
234 if (ret)
235 return ret;
236
237 parent->id = mssr->parent;
238 } else {
239 ret = gen3_clk_get_core(clk, &core);
240 if (ret)
241 return ret;
242
243 if (core->type == CLK_TYPE_IN)
244 parent->id = ~0; /* Top-level clock */
245 else
246 parent->id = core->parent;
247 }
248
249 parent->dev = clk->dev;
250
251 return 0;
252}
253
4b20eef3
MV		 254static int gen3_clk_setup_sdif_div(struct clk *clk)
255{
256 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
257 const struct cpg_core_clk *core;
258 struct clk parent;
259 int ret;
260
261 ret = gen3_clk_get_parent(clk, &parent);
262 if (ret) {
263 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
264 return ret;
265 }
266
267 if (gen3_clk_is_mod(&parent))
268 return 0;
269
270 ret = gen3_clk_get_core(&parent, &core);
271 if (ret)
272 return ret;
273
274 if (core->type != CLK_TYPE_GEN3_SD)
275 return 0;
276
277 debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
278
279 writel(1, priv->base + core->offset);
280
281 return 0;
282}
283
36c2ee4c
MV		 284static int gen3_clk_endisable(struct clk *clk, bool enable)
285{
286 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
287 const unsigned long clkid = clk->id & 0xffff;
288 const unsigned int reg = clkid / 100;
289 const unsigned int bit = clkid % 100;
290 const u32 bitmask = BIT(bit);
4b20eef3 291 int ret;
36c2ee4c
MV		 292
293 if (!gen3_clk_is_mod(clk))
294 return -EINVAL;
295
296 debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
297 clkid, reg, bit, enable ? "ON" : "OFF");
298
299 if (enable) {
4b20eef3
MV		 300 ret = gen3_clk_setup_sdif_div(clk);
301 if (ret)
302 return ret;
36c2ee4c
MV		 303 clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
304 return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
305 bitmask, 0, 100, 0);
306 } else {
307 setbits_le32(priv->base + SMSTPCR(reg), bitmask);
308 return 0;
309 }
310}
311
312static int gen3_clk_enable(struct clk *clk)
313{
314 return gen3_clk_endisable(clk, true);
315}
316
317static int gen3_clk_disable(struct clk *clk)
318{
319 return gen3_clk_endisable(clk, false);
320}
321
322static ulong gen3_clk_get_rate(struct clk *clk)
323{
324 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
325 struct clk parent;
326 const struct cpg_core_clk *core;
327 const struct rcar_gen3_cpg_pll_config *pll_config =
328 priv->cpg_pll_config;
849ab0a6 329 u32 value, mult, prediv, postdiv, rate = 0;
36c2ee4c
MV		 330 int i, ret;
331
332 debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
333
334 ret = gen3_clk_get_parent(clk, &parent);
335 if (ret) {
336 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
337 return ret;
338 }
339
340 if (gen3_clk_is_mod(clk)) {
341 rate = gen3_clk_get_rate(&parent);
342 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
343 __func__, __LINE__, parent.id, rate);
344 return rate;
345 }
346
347 ret = gen3_clk_get_core(clk, &core);
348 if (ret)
349 return ret;
350
351 switch (core->type) {
352 case CLK_TYPE_IN:
353 if (core->id == CLK_EXTAL) {
354 rate = clk_get_rate(&priv->clk_extal);
355 debug("%s[%i] EXTAL clk: rate=%u\n",
356 __func__, __LINE__, rate);
357 return rate;
358 }
359
360 if (core->id == CLK_EXTALR) {
361 rate = clk_get_rate(&priv->clk_extalr);
362 debug("%s[%i] EXTALR clk: rate=%u\n",
363 __func__, __LINE__, rate);
364 return rate;
365 }
366
367 return -EINVAL;
368
369 case CLK_TYPE_GEN3_MAIN:
370 rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
371 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
372 __func__, __LINE__,
373 core->parent, pll_config->extal_div, rate);
374 return rate;
375
376 case CLK_TYPE_GEN3_PLL0:
377 value = readl(priv->base + CPG_PLL0CR);
378 mult = (((value >> 24) & 0x7f) + 1) * 2;
379 rate = gen3_clk_get_rate(&parent) * mult;
380 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
381 __func__, __LINE__, core->parent, mult, rate);
382 return rate;
383
384 case CLK_TYPE_GEN3_PLL1:
385 rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
386 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
387 __func__, __LINE__,
388 core->parent, pll_config->pll1_mult, rate);
389 return rate;
390
391 case CLK_TYPE_GEN3_PLL2:
392 value = readl(priv->base + CPG_PLL2CR);
393 mult = (((value >> 24) & 0x7f) + 1) * 2;
394 rate = gen3_clk_get_rate(&parent) * mult;
395 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
396 __func__, __LINE__, core->parent, mult, rate);
397 return rate;
398
399 case CLK_TYPE_GEN3_PLL3:
400 rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
401 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
402 __func__, __LINE__,
403 core->parent, pll_config->pll3_mult, rate);
404 return rate;
405
406 case CLK_TYPE_GEN3_PLL4:
407 value = readl(priv->base + CPG_PLL4CR);
408 mult = (((value >> 24) & 0x7f) + 1) * 2;
409 rate = gen3_clk_get_rate(&parent) * mult;
410 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
411 __func__, __LINE__, core->parent, mult, rate);
412 return rate;
413
414 case CLK_TYPE_FF:
2c150950 415 case CLK_TYPE_GEN3_PE: /* FIXME */
36c2ee4c
MV		 416 rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
417 debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
418 __func__, __LINE__,
419 core->parent, core->mult, core->div, rate);
420 return rate;
421
422 case CLK_TYPE_GEN3_SD: /* FIXME */
423 value = readl(priv->base + core->offset);
424 value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
425
426 for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
427 if (cpg_sd_div_table[i].val != value)
428 continue;
429
430 rate = gen3_clk_get_rate(&parent) /
431 cpg_sd_div_table[i].div;
432 debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
433 __func__, __LINE__,
434 core->parent, cpg_sd_div_table[i].div, rate);
435
436 return rate;
437 }
438
439 return -EINVAL;
849ab0a6
MV		 440
441 case CLK_TYPE_GEN3_RPC:
442 rate = gen3_clk_get_rate(&parent);
443
444 value = readl(priv->base + core->offset);
445
446 prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
447 CPG_RPC_PREDIV_MASK;
448 if (prediv == 2)
449 rate /= 5;
450 else if (prediv == 3)
451 rate /= 6;
452 else
453 return -EINVAL;
454
455 postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
456 CPG_RPC_POSTDIV_MASK;
457 rate /= postdiv + 1;
458
459 debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
460 __func__, __LINE__,
461 core->parent, prediv, postdiv, rate);
462
463 return -EINVAL;
464
36c2ee4c
MV		 465 }
466
467 printf("%s[%i] unknown fail\n", __func__, __LINE__);
468
469 return -ENOENT;
470}
471
472static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
473{
474 return gen3_clk_get_rate(clk);
475}
476
477static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
478{
479 if (args->args_count != 2) {
480 debug("Invaild args_count: %d\n", args->args_count);
481 return -EINVAL;
482 }
483
484 clk->id = (args->args[0] << 16) | args->args[1];
485
486 return 0;
487}
488
f77b5a4c 489const struct clk_ops gen3_clk_ops = {
36c2ee4c
MV		 490 .enable = gen3_clk_enable,
491 .disable = gen3_clk_disable,
492 .get_rate = gen3_clk_get_rate,
493 .set_rate = gen3_clk_set_rate,
494 .of_xlate = gen3_clk_of_xlate,
495};
496
f77b5a4c 497int gen3_clk_probe(struct udevice *dev)
36c2ee4c
MV		 498{
499 struct gen3_clk_priv *priv = dev_get_priv(dev);
f77b5a4c
MV		 500 struct cpg_mssr_info *info =
501 (struct cpg_mssr_info *)dev_get_driver_data(dev);
36c2ee4c
MV		 502 fdt_addr_t rst_base;
503 u32 cpg_mode;
504 int ret;
505
506 priv->base = (struct gen3_base *)devfdt_get_addr(dev);
507 if (!priv->base)
508 return -EINVAL;
509
f77b5a4c
MV		 510 priv->info = info;
511 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
512 if (ret < 0)
513 return ret;
36c2ee4c
MV		 514
515 rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
516 if (rst_base == FDT_ADDR_T_NONE)
517 return -EINVAL;
518
519 cpg_mode = readl(rst_base + CPG_RST_MODEMR);
520
521 priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
522 if (!priv->cpg_pll_config->extal_div)
523 return -EINVAL;
524
525 ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
526 if (ret < 0)
527 return ret;
528
f77b5a4c
MV		 529 if (info->extalr_node) {
530 ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
2c150950
MV		 531 if (ret < 0)
532 return ret;
533 }
36c2ee4c
MV		 534
535 return 0;
536}
537
f77b5a4c 538int gen3_clk_remove(struct udevice *dev)
18cac5af
MV		 539{
540 struct gen3_clk_priv *priv = dev_get_priv(dev);
f77b5a4c
MV		 541 struct cpg_mssr_info *info = priv->info;
542 unsigned int i;
18cac5af
MV		 543
544 /* Stop TMU0 */
545 clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
546
547 /* Stop module clock */
f77b5a4c
MV		 548 for (i = 0; i < info->mstp_table_size; i++) {
549 clrsetbits_le32(priv->base + SMSTPCR(i),
550 info->mstp_table[i].dis,
551 info->mstp_table[i].en);
552 clrsetbits_le32(priv->base + RMSTPCR(i),
553 info->mstp_table[i].dis, 0x0);
18cac5af
MV		 554 }
555
556 return 0;
557}
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