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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
243229b1 EZ |
2 | /* |
3 | * Copyright (c) 2018 Rockchip Electronics Co. Ltd. | |
4 | * Author: Elaine Zhang<zhangqing@rock-chips.com> | |
243229b1 EZ |
5 | */ |
6 | ||
7 | #include <linux/clk-provider.h> | |
62e59c4e | 8 | #include <linux/io.h> |
243229b1 EZ |
9 | #include <linux/of.h> |
10 | #include <linux/of_address.h> | |
11 | #include <linux/syscore_ops.h> | |
12 | #include <dt-bindings/clock/px30-cru.h> | |
13 | #include "clk.h" | |
14 | ||
15 | #define PX30_GRF_SOC_STATUS0 0x480 | |
16 | ||
17 | enum px30_plls { | |
18 | apll, dpll, cpll, npll, apll_b_h, apll_b_l, | |
19 | }; | |
20 | ||
21 | enum px30_pmu_plls { | |
22 | gpll, | |
23 | }; | |
24 | ||
25 | static struct rockchip_pll_rate_table px30_pll_rates[] = { | |
26 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ | |
27 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), | |
28 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), | |
29 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), | |
30 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), | |
31 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), | |
32 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), | |
33 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), | |
34 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), | |
35 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), | |
36 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), | |
37 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), | |
38 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), | |
39 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), | |
40 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), | |
41 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), | |
42 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), | |
43 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), | |
44 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), | |
45 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), | |
46 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), | |
47 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), | |
48 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), | |
49 | RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), | |
50 | RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), | |
51 | RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), | |
52 | RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), | |
53 | RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), | |
54 | RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), | |
55 | RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), | |
56 | RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), | |
57 | RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), | |
58 | RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), | |
59 | RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), | |
60 | RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), | |
61 | RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0), | |
62 | RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), | |
63 | RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), | |
64 | RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), | |
65 | RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), | |
66 | RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), | |
67 | RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), | |
68 | RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), | |
69 | RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), | |
70 | { /* sentinel */ }, | |
71 | }; | |
72 | ||
73 | #define PX30_DIV_ACLKM_MASK 0x7 | |
74 | #define PX30_DIV_ACLKM_SHIFT 12 | |
75 | #define PX30_DIV_PCLK_DBG_MASK 0xf | |
76 | #define PX30_DIV_PCLK_DBG_SHIFT 8 | |
77 | ||
78 | #define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \ | |
79 | { \ | |
80 | .reg = PX30_CLKSEL_CON(0), \ | |
81 | .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \ | |
82 | PX30_DIV_ACLKM_SHIFT) | \ | |
83 | HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \ | |
84 | PX30_DIV_PCLK_DBG_SHIFT), \ | |
85 | } | |
86 | ||
87 | #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \ | |
88 | { \ | |
89 | .prate = _prate, \ | |
90 | .divs = { \ | |
91 | PX30_CLKSEL0(_aclk_core, _pclk_dbg), \ | |
92 | }, \ | |
93 | } | |
94 | ||
95 | static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = { | |
96 | PX30_CPUCLK_RATE(1608000000, 1, 7), | |
97 | PX30_CPUCLK_RATE(1584000000, 1, 7), | |
98 | PX30_CPUCLK_RATE(1560000000, 1, 7), | |
99 | PX30_CPUCLK_RATE(1536000000, 1, 7), | |
100 | PX30_CPUCLK_RATE(1512000000, 1, 7), | |
101 | PX30_CPUCLK_RATE(1488000000, 1, 5), | |
102 | PX30_CPUCLK_RATE(1464000000, 1, 5), | |
103 | PX30_CPUCLK_RATE(1440000000, 1, 5), | |
104 | PX30_CPUCLK_RATE(1416000000, 1, 5), | |
105 | PX30_CPUCLK_RATE(1392000000, 1, 5), | |
106 | PX30_CPUCLK_RATE(1368000000, 1, 5), | |
107 | PX30_CPUCLK_RATE(1344000000, 1, 5), | |
108 | PX30_CPUCLK_RATE(1320000000, 1, 5), | |
109 | PX30_CPUCLK_RATE(1296000000, 1, 5), | |
110 | PX30_CPUCLK_RATE(1272000000, 1, 5), | |
111 | PX30_CPUCLK_RATE(1248000000, 1, 5), | |
112 | PX30_CPUCLK_RATE(1224000000, 1, 5), | |
113 | PX30_CPUCLK_RATE(1200000000, 1, 5), | |
114 | PX30_CPUCLK_RATE(1104000000, 1, 5), | |
115 | PX30_CPUCLK_RATE(1008000000, 1, 5), | |
116 | PX30_CPUCLK_RATE(912000000, 1, 5), | |
117 | PX30_CPUCLK_RATE(816000000, 1, 3), | |
118 | PX30_CPUCLK_RATE(696000000, 1, 3), | |
119 | PX30_CPUCLK_RATE(600000000, 1, 3), | |
120 | PX30_CPUCLK_RATE(408000000, 1, 1), | |
121 | PX30_CPUCLK_RATE(312000000, 1, 1), | |
122 | PX30_CPUCLK_RATE(216000000, 1, 1), | |
123 | PX30_CPUCLK_RATE(96000000, 1, 1), | |
124 | }; | |
125 | ||
126 | static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = { | |
127 | .core_reg = PX30_CLKSEL_CON(0), | |
128 | .div_core_shift = 0, | |
129 | .div_core_mask = 0xf, | |
130 | .mux_core_alt = 1, | |
131 | .mux_core_main = 0, | |
132 | .mux_core_shift = 7, | |
133 | .mux_core_mask = 0x1, | |
134 | }; | |
135 | ||
136 | PNAME(mux_pll_p) = { "xin24m"}; | |
137 | PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" }; | |
138 | PNAME(mux_armclk_p) = { "apll_core", "gpll_core" }; | |
139 | PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; | |
140 | PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" }; | |
141 | PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" }; | |
142 | PNAME(mux_cpll_npll_p) = { "cpll", "npll" }; | |
143 | PNAME(mux_npll_cpll_p) = { "npll", "cpll" }; | |
144 | PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" }; | |
145 | PNAME(mux_gpll_npll_p) = { "gpll", "npll" }; | |
146 | PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"}; | |
147 | PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" }; | |
148 | PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" }; | |
149 | PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"}; | |
150 | PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" }; | |
151 | PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"}; | |
152 | PNAME(mux_i2s0_rx_p) = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"}; | |
153 | PNAME(mux_i2s1_p) = { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"}; | |
154 | PNAME(mux_i2s2_p) = { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"}; | |
155 | PNAME(mux_i2s0_tx_out_p) = { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"}; | |
156 | PNAME(mux_i2s0_rx_out_p) = { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"}; | |
157 | PNAME(mux_i2s1_out_p) = { "clk_i2s1", "xin12m"}; | |
158 | PNAME(mux_i2s2_out_p) = { "clk_i2s2", "xin12m"}; | |
159 | PNAME(mux_i2s0_tx_rx_p) = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"}; | |
160 | PNAME(mux_i2s0_rx_tx_p) = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"}; | |
161 | PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" }; | |
162 | PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" }; | |
163 | PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" }; | |
164 | PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" }; | |
165 | PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" }; | |
166 | PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" }; | |
167 | PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" }; | |
168 | PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" }; | |
169 | PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" }; | |
170 | PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" }; | |
171 | PNAME(mux_gmac_rmii_sel_p) = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" }; | |
172 | PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", }; | |
173 | PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" }; | |
174 | PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" }; | |
175 | PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; | |
176 | PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; | |
177 | PNAME(mux_gpu_p) = { "clk_gpu_div", "clk_gpu_np5" }; | |
178 | ||
179 | static struct rockchip_pll_clock px30_pll_clks[] __initdata = { | |
180 | [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, | |
181 | 0, PX30_PLL_CON(0), | |
182 | PX30_MODE_CON, 0, 0, 0, px30_pll_rates), | |
183 | [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, | |
184 | 0, PX30_PLL_CON(8), | |
185 | PX30_MODE_CON, 4, 1, 0, NULL), | |
186 | [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, | |
187 | 0, PX30_PLL_CON(16), | |
188 | PX30_MODE_CON, 2, 2, 0, px30_pll_rates), | |
189 | [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, | |
190 | 0, PX30_PLL_CON(24), | |
191 | PX30_MODE_CON, 6, 4, 0, px30_pll_rates), | |
192 | }; | |
193 | ||
194 | static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = { | |
195 | [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0), | |
196 | PX30_PMU_MODE, 0, 3, 0, px30_pll_rates), | |
197 | }; | |
198 | ||
199 | #define MFLAGS CLK_MUX_HIWORD_MASK | |
200 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK | |
201 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) | |
202 | ||
203 | static struct rockchip_clk_branch px30_pdm_fracmux __initdata = | |
204 | MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, | |
205 | PX30_CLKSEL_CON(26), 15, 1, MFLAGS); | |
206 | ||
207 | static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata = | |
208 | MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT, | |
209 | PX30_CLKSEL_CON(28), 10, 2, MFLAGS); | |
210 | ||
211 | static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata = | |
212 | MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT, | |
213 | PX30_CLKSEL_CON(58), 10, 2, MFLAGS); | |
214 | ||
215 | static struct rockchip_clk_branch px30_i2s1_fracmux __initdata = | |
216 | MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, | |
217 | PX30_CLKSEL_CON(30), 10, 2, MFLAGS); | |
218 | ||
219 | static struct rockchip_clk_branch px30_i2s2_fracmux __initdata = | |
220 | MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, | |
221 | PX30_CLKSEL_CON(32), 10, 2, MFLAGS); | |
222 | ||
223 | static struct rockchip_clk_branch px30_uart1_fracmux __initdata = | |
224 | MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, | |
225 | PX30_CLKSEL_CON(35), 14, 2, MFLAGS); | |
226 | ||
227 | static struct rockchip_clk_branch px30_uart2_fracmux __initdata = | |
228 | MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, | |
229 | PX30_CLKSEL_CON(38), 14, 2, MFLAGS); | |
230 | ||
231 | static struct rockchip_clk_branch px30_uart3_fracmux __initdata = | |
232 | MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, | |
233 | PX30_CLKSEL_CON(41), 14, 2, MFLAGS); | |
234 | ||
235 | static struct rockchip_clk_branch px30_uart4_fracmux __initdata = | |
236 | MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, | |
237 | PX30_CLKSEL_CON(44), 14, 2, MFLAGS); | |
238 | ||
239 | static struct rockchip_clk_branch px30_uart5_fracmux __initdata = | |
240 | MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, | |
241 | PX30_CLKSEL_CON(47), 14, 2, MFLAGS); | |
242 | ||
243 | static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata = | |
244 | MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT, | |
245 | PX30_CLKSEL_CON(5), 14, 2, MFLAGS); | |
246 | ||
247 | static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata = | |
248 | MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT, | |
249 | PX30_CLKSEL_CON(8), 14, 2, MFLAGS); | |
250 | ||
251 | static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata = | |
252 | MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT, | |
253 | PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS); | |
254 | ||
255 | static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata = | |
256 | MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT, | |
257 | PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS); | |
258 | ||
259 | static struct rockchip_clk_branch px30_clk_branches[] __initdata = { | |
260 | /* | |
261 | * Clock-Architecture Diagram 1 | |
262 | */ | |
263 | ||
264 | MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, | |
265 | PX30_MODE_CON, 8, 2, MFLAGS), | |
266 | FACTOR(0, "xin12m", "xin24m", 0, 1, 2), | |
267 | ||
268 | /* | |
269 | * Clock-Architecture Diagram 3 | |
270 | */ | |
271 | ||
272 | /* PD_CORE */ | |
273 | GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, | |
274 | PX30_CLKGATE_CON(0), 0, GFLAGS), | |
275 | GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, | |
276 | PX30_CLKGATE_CON(0), 0, GFLAGS), | |
277 | COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, | |
278 | PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
279 | PX30_CLKGATE_CON(0), 2, GFLAGS), | |
280 | COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, | |
281 | PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
282 | PX30_CLKGATE_CON(0), 1, GFLAGS), | |
283 | GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, | |
284 | PX30_CLKGATE_CON(0), 4, GFLAGS), | |
285 | GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED, | |
286 | PX30_CLKGATE_CON(17), 5, GFLAGS), | |
287 | GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED, | |
288 | PX30_CLKGATE_CON(0), 5, GFLAGS), | |
289 | GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED, | |
290 | PX30_CLKGATE_CON(0), 6, GFLAGS), | |
291 | GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED, | |
292 | PX30_CLKGATE_CON(17), 6, GFLAGS), | |
293 | ||
294 | GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED, | |
295 | PX30_CLKGATE_CON(0), 3, GFLAGS), | |
296 | GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0, | |
297 | PX30_CLKGATE_CON(17), 4, GFLAGS), | |
298 | ||
299 | /* PD_GPU */ | |
300 | COMPOSITE_NODIV(0, "clk_gpu_src", mux_4plls_p, 0, | |
301 | PX30_CLKSEL_CON(1), 6, 2, MFLAGS, | |
302 | PX30_CLKGATE_CON(0), 8, GFLAGS), | |
303 | COMPOSITE_NOMUX(0, "clk_gpu_div", "clk_gpu_src", 0, | |
304 | PX30_CLKSEL_CON(1), 0, 4, DFLAGS, | |
305 | PX30_CLKGATE_CON(0), 12, GFLAGS), | |
306 | COMPOSITE_NOMUX_HALFDIV(0, "clk_gpu_np5", "clk_gpu_src", 0, | |
307 | PX30_CLKSEL_CON(1), 8, 4, DFLAGS, | |
308 | PX30_CLKGATE_CON(0), 9, GFLAGS), | |
309 | COMPOSITE_NODIV(SCLK_GPU, "clk_gpu", mux_gpu_p, CLK_SET_RATE_PARENT, | |
310 | PX30_CLKSEL_CON(1), 15, 1, MFLAGS, | |
311 | PX30_CLKGATE_CON(0), 10, GFLAGS), | |
312 | COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED, | |
313 | PX30_CLKSEL_CON(1), 13, 2, DFLAGS, | |
314 | PX30_CLKGATE_CON(17), 10, GFLAGS), | |
315 | GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED, | |
316 | PX30_CLKGATE_CON(0), 11, GFLAGS), | |
317 | GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED, | |
318 | PX30_CLKGATE_CON(17), 8, GFLAGS), | |
319 | GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED, | |
320 | PX30_CLKGATE_CON(17), 9, GFLAGS), | |
321 | ||
322 | /* | |
323 | * Clock-Architecture Diagram 4 | |
324 | */ | |
325 | ||
326 | /* PD_DDR */ | |
327 | GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, | |
328 | PX30_CLKGATE_CON(0), 7, GFLAGS), | |
329 | GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, | |
330 | PX30_CLKGATE_CON(0), 13, GFLAGS), | |
331 | COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED, | |
332 | PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), | |
333 | COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, | |
334 | PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS), | |
335 | FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, | |
336 | PX30_CLKGATE_CON(0), 14, GFLAGS), | |
337 | FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, | |
338 | PX30_CLKGATE_CON(1), 0, GFLAGS), | |
339 | COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED, | |
340 | PX30_CLKSEL_CON(2), 4, 1, MFLAGS, | |
341 | PX30_CLKGATE_CON(1), 13, GFLAGS), | |
342 | GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED, | |
343 | PX30_CLKGATE_CON(1), 15, GFLAGS), | |
344 | GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED, | |
345 | PX30_CLKGATE_CON(1), 8, GFLAGS), | |
346 | GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, | |
347 | PX30_CLKGATE_CON(1), 5, GFLAGS), | |
348 | GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, | |
349 | PX30_CLKGATE_CON(1), 6, GFLAGS), | |
350 | GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED, | |
351 | PX30_CLKGATE_CON(1), 6, GFLAGS), | |
352 | GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED, | |
353 | PX30_CLKGATE_CON(1), 11, GFLAGS), | |
354 | ||
355 | GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED, | |
356 | PX30_CLKGATE_CON(0), 15, GFLAGS), | |
357 | ||
358 | COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED, | |
359 | PX30_CLKSEL_CON(2), 8, 5, DFLAGS, | |
360 | PX30_CLKGATE_CON(1), 1, GFLAGS), | |
361 | GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED, | |
362 | PX30_CLKGATE_CON(1), 10, GFLAGS), | |
363 | GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED, | |
364 | PX30_CLKGATE_CON(1), 7, GFLAGS), | |
365 | GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED, | |
366 | PX30_CLKGATE_CON(1), 9, GFLAGS), | |
367 | GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED, | |
368 | PX30_CLKGATE_CON(1), 12, GFLAGS), | |
369 | GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, | |
370 | PX30_CLKGATE_CON(1), 14, GFLAGS), | |
371 | GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED, | |
372 | PX30_CLKGATE_CON(1), 3, GFLAGS), | |
373 | ||
374 | /* | |
375 | * Clock-Architecture Diagram 5 | |
376 | */ | |
377 | ||
378 | /* PD_VI */ | |
379 | COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0, | |
380 | PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
381 | PX30_CLKGATE_CON(4), 8, GFLAGS), | |
382 | COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0, | |
383 | PX30_CLKSEL_CON(11), 8, 4, DFLAGS, | |
384 | PX30_CLKGATE_CON(4), 12, GFLAGS), | |
385 | COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0, | |
386 | PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
387 | PX30_CLKGATE_CON(4), 9, GFLAGS), | |
388 | COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0, | |
389 | PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS, | |
390 | PX30_CLKGATE_CON(4), 11, GFLAGS), | |
391 | GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0, | |
392 | PX30_CLKGATE_CON(4), 13, GFLAGS), | |
393 | GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0, | |
394 | PX30_CLKGATE_CON(4), 14, GFLAGS), | |
395 | ||
396 | /* | |
397 | * Clock-Architecture Diagram 6 | |
398 | */ | |
399 | ||
400 | /* PD_VO */ | |
401 | COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0, | |
402 | PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
403 | PX30_CLKGATE_CON(2), 0, GFLAGS), | |
404 | COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0, | |
405 | PX30_CLKSEL_CON(3), 8, 4, DFLAGS, | |
406 | PX30_CLKGATE_CON(2), 12, GFLAGS), | |
407 | COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0, | |
408 | PX30_CLKSEL_CON(3), 12, 4, DFLAGS, | |
409 | PX30_CLKGATE_CON(2), 13, GFLAGS), | |
410 | COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0, | |
411 | PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
412 | PX30_CLKGATE_CON(2), 1, GFLAGS), | |
413 | ||
414 | COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0, | |
415 | PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS, | |
416 | PX30_CLKGATE_CON(2), 5, GFLAGS), | |
417 | COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
418 | PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS, | |
419 | PX30_CLKGATE_CON(2), 2, GFLAGS), | |
420 | COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT, | |
421 | PX30_CLKSEL_CON(6), 0, | |
422 | PX30_CLKGATE_CON(2), 3, GFLAGS, | |
423 | &px30_dclk_vopb_fracmux), | |
424 | GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT, | |
425 | PX30_CLKGATE_CON(2), 4, GFLAGS), | |
426 | COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0, | |
427 | PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS, | |
428 | PX30_CLKGATE_CON(2), 6, GFLAGS), | |
429 | COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT, | |
430 | PX30_CLKSEL_CON(9), 0, | |
431 | PX30_CLKGATE_CON(2), 7, GFLAGS, | |
432 | &px30_dclk_vopl_fracmux), | |
433 | GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT, | |
434 | PX30_CLKGATE_CON(2), 8, GFLAGS), | |
435 | ||
436 | /* PD_VPU */ | |
437 | COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0, | |
438 | PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
439 | PX30_CLKGATE_CON(4), 0, GFLAGS), | |
440 | COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, | |
441 | PX30_CLKSEL_CON(10), 8, 4, DFLAGS, | |
442 | PX30_CLKGATE_CON(4), 2, GFLAGS), | |
443 | COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0, | |
444 | PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
445 | PX30_CLKGATE_CON(4), 1, GFLAGS), | |
446 | ||
447 | /* | |
448 | * Clock-Architecture Diagram 7 | |
449 | */ | |
450 | ||
451 | COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0, | |
452 | PX30_CLKSEL_CON(14), 15, 1, MFLAGS, | |
453 | PX30_CLKGATE_CON(5), 7, GFLAGS), | |
454 | COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED, | |
455 | PX30_CLKSEL_CON(14), 0, 5, DFLAGS, | |
456 | PX30_CLKGATE_CON(5), 8, GFLAGS), | |
457 | DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED, | |
458 | PX30_CLKSEL_CON(14), 8, 5, DFLAGS), | |
459 | ||
460 | /* PD_MMC_NAND */ | |
461 | GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0, | |
462 | PX30_CLKGATE_CON(6), 0, GFLAGS), | |
463 | COMPOSITE(SCLK_NANDC, "clk_nandc", mux_gpll_cpll_npll_p, 0, | |
464 | PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
465 | PX30_CLKGATE_CON(5), 13, GFLAGS), | |
466 | ||
467 | COMPOSITE(SCLK_SDIO, "clk_sdio", mux_gpll_cpll_npll_xin24m_p, 0, | |
468 | PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS, | |
469 | PX30_CLKGATE_CON(6), 3, GFLAGS), | |
470 | ||
471 | COMPOSITE(SCLK_EMMC, "clk_emmc", mux_gpll_cpll_npll_xin24m_p, 0, | |
472 | PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS, | |
473 | PX30_CLKGATE_CON(6), 6, GFLAGS), | |
474 | ||
475 | COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0, | |
476 | PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS, | |
477 | PX30_CLKGATE_CON(6), 7, GFLAGS), | |
478 | ||
479 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", | |
480 | PX30_SDMMC_CON0, 1), | |
481 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", | |
482 | PX30_SDMMC_CON1, 1), | |
483 | ||
484 | MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", | |
485 | PX30_SDIO_CON0, 1), | |
486 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", | |
487 | PX30_SDIO_CON1, 1), | |
488 | ||
489 | MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", | |
490 | PX30_EMMC_CON0, 1), | |
491 | MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", | |
492 | PX30_EMMC_CON1, 1), | |
493 | ||
494 | /* PD_SDCARD */ | |
495 | GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0, | |
496 | PX30_CLKGATE_CON(6), 12, GFLAGS), | |
497 | COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_npll_xin24m_p, 0, | |
498 | PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS, | |
499 | PX30_CLKGATE_CON(6), 15, GFLAGS), | |
500 | ||
501 | /* PD_USB */ | |
502 | GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", 0, | |
503 | PX30_CLKGATE_CON(7), 2, GFLAGS), | |
504 | GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0, | |
505 | PX30_CLKGATE_CON(7), 3, GFLAGS), | |
506 | ||
507 | /* PD_GMAC */ | |
508 | COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0, | |
509 | PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
510 | PX30_CLKGATE_CON(7), 11, GFLAGS), | |
511 | MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT, | |
512 | PX30_CLKSEL_CON(23), 6, 1, MFLAGS), | |
513 | GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0, | |
514 | PX30_CLKGATE_CON(7), 15, GFLAGS), | |
515 | GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0, | |
516 | PX30_CLKGATE_CON(7), 13, GFLAGS), | |
517 | FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2), | |
518 | FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20), | |
519 | MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT, | |
520 | PX30_CLKSEL_CON(23), 7, 1, MFLAGS), | |
521 | ||
522 | GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0, | |
523 | PX30_CLKGATE_CON(7), 10, GFLAGS), | |
524 | COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, | |
525 | PX30_CLKSEL_CON(23), 0, 4, DFLAGS, | |
526 | PX30_CLKGATE_CON(7), 12, GFLAGS), | |
527 | ||
528 | COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0, | |
529 | PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
530 | PX30_CLKGATE_CON(8), 5, GFLAGS), | |
531 | ||
532 | /* | |
533 | * Clock-Architecture Diagram 8 | |
534 | */ | |
535 | ||
536 | /* PD_BUS */ | |
537 | COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED, | |
538 | PX30_CLKSEL_CON(23), 15, 1, MFLAGS, | |
539 | PX30_CLKGATE_CON(8), 6, GFLAGS), | |
540 | COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED, | |
541 | PX30_CLKSEL_CON(24), 0, 5, DFLAGS, | |
542 | PX30_CLKGATE_CON(8), 8, GFLAGS), | |
543 | COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED, | |
544 | PX30_CLKSEL_CON(23), 8, 5, DFLAGS, | |
545 | PX30_CLKGATE_CON(8), 7, GFLAGS), | |
546 | COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IGNORE_UNUSED, | |
547 | PX30_CLKSEL_CON(24), 8, 2, DFLAGS, | |
548 | PX30_CLKGATE_CON(8), 9, GFLAGS), | |
549 | GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, | |
550 | PX30_CLKGATE_CON(8), 10, GFLAGS), | |
551 | ||
552 | COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0, | |
553 | PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS, | |
554 | PX30_CLKGATE_CON(9), 9, GFLAGS), | |
555 | COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT, | |
556 | PX30_CLKSEL_CON(27), 0, | |
557 | PX30_CLKGATE_CON(9), 10, GFLAGS, | |
558 | &px30_pdm_fracmux), | |
559 | GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT, | |
560 | PX30_CLKGATE_CON(9), 11, GFLAGS), | |
561 | ||
562 | COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0, | |
563 | PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS, | |
564 | PX30_CLKGATE_CON(9), 12, GFLAGS), | |
565 | COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT, | |
566 | PX30_CLKSEL_CON(29), 0, | |
567 | PX30_CLKGATE_CON(9), 13, GFLAGS, | |
568 | &px30_i2s0_tx_fracmux), | |
569 | COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT, | |
570 | PX30_CLKSEL_CON(28), 12, 1, MFLAGS, | |
571 | PX30_CLKGATE_CON(9), 14, GFLAGS), | |
572 | COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0, | |
573 | PX30_CLKSEL_CON(28), 14, 2, MFLAGS, | |
574 | PX30_CLKGATE_CON(9), 15, GFLAGS), | |
575 | GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT, | |
576 | PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK), | |
577 | ||
578 | COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0, | |
579 | PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS, | |
580 | PX30_CLKGATE_CON(17), 0, GFLAGS), | |
581 | COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT, | |
582 | PX30_CLKSEL_CON(59), 0, | |
583 | PX30_CLKGATE_CON(17), 1, GFLAGS, | |
584 | &px30_i2s0_rx_fracmux), | |
585 | COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT, | |
586 | PX30_CLKSEL_CON(58), 12, 1, MFLAGS, | |
587 | PX30_CLKGATE_CON(17), 2, GFLAGS), | |
588 | COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0, | |
589 | PX30_CLKSEL_CON(58), 14, 2, MFLAGS, | |
590 | PX30_CLKGATE_CON(17), 3, GFLAGS), | |
591 | GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT, | |
592 | PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK), | |
593 | ||
594 | COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0, | |
595 | PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS, | |
596 | PX30_CLKGATE_CON(10), 0, GFLAGS), | |
597 | COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT, | |
598 | PX30_CLKSEL_CON(31), 0, | |
599 | PX30_CLKGATE_CON(10), 1, GFLAGS, | |
600 | &px30_i2s1_fracmux), | |
601 | GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, | |
602 | PX30_CLKGATE_CON(10), 2, GFLAGS), | |
603 | COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0, | |
604 | PX30_CLKSEL_CON(30), 15, 1, MFLAGS, | |
605 | PX30_CLKGATE_CON(10), 3, GFLAGS), | |
606 | GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT, | |
607 | PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK), | |
608 | ||
609 | COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0, | |
610 | PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS, | |
611 | PX30_CLKGATE_CON(10), 4, GFLAGS), | |
612 | COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT, | |
613 | PX30_CLKSEL_CON(33), 0, | |
614 | PX30_CLKGATE_CON(10), 5, GFLAGS, | |
615 | &px30_i2s2_fracmux), | |
616 | GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, | |
617 | PX30_CLKGATE_CON(10), 6, GFLAGS), | |
618 | COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0, | |
619 | PX30_CLKSEL_CON(32), 15, 1, MFLAGS, | |
620 | PX30_CLKGATE_CON(10), 7, GFLAGS), | |
621 | GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT, | |
622 | PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK), | |
623 | ||
624 | COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT, | |
625 | PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS, | |
626 | PX30_CLKGATE_CON(10), 12, GFLAGS), | |
627 | COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0, | |
628 | PX30_CLKSEL_CON(35), 0, 5, DFLAGS, | |
629 | PX30_CLKGATE_CON(10), 13, GFLAGS), | |
630 | COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, | |
631 | PX30_CLKSEL_CON(36), 0, | |
632 | PX30_CLKGATE_CON(10), 14, GFLAGS, | |
633 | &px30_uart1_fracmux), | |
634 | GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT, | |
635 | PX30_CLKGATE_CON(10), 15, GFLAGS), | |
636 | ||
637 | COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0, | |
638 | PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS, | |
639 | PX30_CLKGATE_CON(11), 0, GFLAGS), | |
640 | COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0, | |
641 | PX30_CLKSEL_CON(38), 0, 5, DFLAGS, | |
642 | PX30_CLKGATE_CON(11), 1, GFLAGS), | |
643 | COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, | |
644 | PX30_CLKSEL_CON(39), 0, | |
645 | PX30_CLKGATE_CON(11), 2, GFLAGS, | |
646 | &px30_uart2_fracmux), | |
647 | GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT, | |
648 | PX30_CLKGATE_CON(11), 3, GFLAGS), | |
649 | ||
650 | COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0, | |
651 | PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS, | |
652 | PX30_CLKGATE_CON(11), 4, GFLAGS), | |
653 | COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0, | |
654 | PX30_CLKSEL_CON(41), 0, 5, DFLAGS, | |
655 | PX30_CLKGATE_CON(11), 5, GFLAGS), | |
656 | COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, | |
657 | PX30_CLKSEL_CON(42), 0, | |
658 | PX30_CLKGATE_CON(11), 6, GFLAGS, | |
659 | &px30_uart3_fracmux), | |
660 | GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT, | |
661 | PX30_CLKGATE_CON(11), 7, GFLAGS), | |
662 | ||
663 | COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0, | |
664 | PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS, | |
665 | PX30_CLKGATE_CON(11), 8, GFLAGS), | |
666 | COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0, | |
667 | PX30_CLKSEL_CON(44), 0, 5, DFLAGS, | |
668 | PX30_CLKGATE_CON(11), 9, GFLAGS), | |
669 | COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, | |
670 | PX30_CLKSEL_CON(45), 0, | |
671 | PX30_CLKGATE_CON(11), 10, GFLAGS, | |
672 | &px30_uart4_fracmux), | |
673 | GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT, | |
674 | PX30_CLKGATE_CON(11), 11, GFLAGS), | |
675 | ||
676 | COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0, | |
677 | PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS, | |
678 | PX30_CLKGATE_CON(11), 12, GFLAGS), | |
679 | COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0, | |
680 | PX30_CLKSEL_CON(47), 0, 5, DFLAGS, | |
681 | PX30_CLKGATE_CON(11), 13, GFLAGS), | |
682 | COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, | |
683 | PX30_CLKSEL_CON(48), 0, | |
684 | PX30_CLKGATE_CON(11), 14, GFLAGS, | |
685 | &px30_uart5_fracmux), | |
686 | GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT, | |
687 | PX30_CLKGATE_CON(11), 15, GFLAGS), | |
688 | ||
689 | COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0, | |
690 | PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS, | |
691 | PX30_CLKGATE_CON(12), 0, GFLAGS), | |
692 | COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0, | |
693 | PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS, | |
694 | PX30_CLKGATE_CON(12), 1, GFLAGS), | |
695 | COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0, | |
696 | PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS, | |
697 | PX30_CLKGATE_CON(12), 2, GFLAGS), | |
698 | COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0, | |
699 | PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS, | |
700 | PX30_CLKGATE_CON(12), 3, GFLAGS), | |
701 | COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, | |
702 | PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS, | |
703 | PX30_CLKGATE_CON(12), 5, GFLAGS), | |
704 | COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0, | |
705 | PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS, | |
706 | PX30_CLKGATE_CON(12), 6, GFLAGS), | |
707 | COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, | |
708 | PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS, | |
709 | PX30_CLKGATE_CON(12), 7, GFLAGS), | |
710 | COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0, | |
711 | PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS, | |
712 | PX30_CLKGATE_CON(12), 8, GFLAGS), | |
713 | ||
714 | GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, | |
715 | PX30_CLKGATE_CON(13), 0, GFLAGS), | |
716 | GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, | |
717 | PX30_CLKGATE_CON(13), 1, GFLAGS), | |
718 | GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, | |
719 | PX30_CLKGATE_CON(13), 2, GFLAGS), | |
720 | GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, | |
721 | PX30_CLKGATE_CON(13), 3, GFLAGS), | |
722 | GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, | |
723 | PX30_CLKGATE_CON(13), 4, GFLAGS), | |
724 | GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, | |
725 | PX30_CLKGATE_CON(13), 5, GFLAGS), | |
726 | ||
727 | COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0, | |
728 | PX30_CLKSEL_CON(54), 0, 11, DFLAGS, | |
729 | PX30_CLKGATE_CON(12), 9, GFLAGS), | |
730 | COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, | |
731 | PX30_CLKSEL_CON(55), 0, 11, DFLAGS, | |
732 | PX30_CLKGATE_CON(12), 10, GFLAGS), | |
733 | COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0, | |
734 | PX30_CLKSEL_CON(56), 0, 3, DFLAGS, | |
735 | PX30_CLKGATE_CON(12), 11, GFLAGS), | |
736 | COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0, | |
737 | PX30_CLKSEL_CON(56), 4, 2, DFLAGS, | |
738 | PX30_CLKGATE_CON(13), 6, GFLAGS), | |
739 | ||
740 | GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED, | |
741 | PX30_CLKGATE_CON(12), 12, GFLAGS), | |
742 | ||
743 | /* PD_CRYPTO */ | |
744 | GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0, | |
745 | PX30_CLKGATE_CON(8), 12, GFLAGS), | |
746 | GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0, | |
747 | PX30_CLKGATE_CON(8), 13, GFLAGS), | |
748 | COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0, | |
749 | PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS, | |
750 | PX30_CLKGATE_CON(8), 14, GFLAGS), | |
751 | COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0, | |
752 | PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
753 | PX30_CLKGATE_CON(8), 15, GFLAGS), | |
754 | ||
755 | /* | |
756 | * Clock-Architecture Diagram 9 | |
757 | */ | |
758 | ||
759 | /* PD_BUS_TOP */ | |
760 | GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS), | |
761 | GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS), | |
762 | GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS), | |
763 | GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS), | |
764 | GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS), | |
765 | GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS), | |
766 | GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 6, GFLAGS), | |
767 | GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS), | |
768 | ||
769 | /* PD_VI */ | |
770 | GATE(0, "aclk_vi_niu", "aclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 15, GFLAGS), | |
771 | GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS), | |
772 | GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS), | |
773 | GATE(0, "hclk_vi_niu", "hclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 0, GFLAGS), | |
774 | GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS), | |
775 | GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS), | |
776 | ||
777 | /* PD_VO */ | |
778 | GATE(0, "aclk_vo_niu", "aclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 0, GFLAGS), | |
779 | GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS), | |
780 | GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS), | |
781 | GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS), | |
782 | ||
783 | GATE(0, "hclk_vo_niu", "hclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 1, GFLAGS), | |
784 | GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS), | |
785 | GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS), | |
786 | GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS), | |
787 | ||
788 | GATE(0, "pclk_vo_niu", "pclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 2, GFLAGS), | |
789 | GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS), | |
790 | ||
791 | /* PD_BUS */ | |
792 | GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS), | |
793 | GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS), | |
794 | GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS), | |
795 | GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS), | |
796 | ||
797 | GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS), | |
798 | GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS), | |
799 | GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS), | |
800 | GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS), | |
801 | GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS), | |
802 | GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS), | |
803 | ||
804 | GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS), | |
805 | GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS), | |
806 | GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS), | |
807 | GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS), | |
808 | GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS), | |
809 | GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS), | |
810 | GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS), | |
811 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS), | |
812 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS), | |
813 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS), | |
814 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS), | |
815 | GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS), | |
816 | GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS), | |
817 | GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS), | |
818 | GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS), | |
819 | GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS), | |
820 | GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS), | |
821 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS), | |
822 | GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS), | |
823 | GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS), | |
824 | GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS), | |
825 | GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS), | |
826 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS), | |
827 | GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS), | |
828 | GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS), | |
829 | GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS), | |
830 | ||
831 | /* PD_VPU */ | |
832 | GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS), | |
833 | GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS), | |
834 | GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS), | |
835 | GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS), | |
836 | ||
837 | /* PD_CRYPTO */ | |
838 | GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS), | |
839 | GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS), | |
840 | GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS), | |
841 | GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS), | |
842 | ||
843 | /* PD_SDCARD */ | |
844 | GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS), | |
845 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS), | |
846 | ||
847 | /* PD_PERI */ | |
848 | GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 9, GFLAGS), | |
849 | ||
850 | /* PD_MMC_NAND */ | |
851 | GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS), | |
852 | GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS), | |
853 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS), | |
854 | GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS), | |
855 | GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS), | |
856 | ||
857 | /* PD_USB */ | |
858 | GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS), | |
859 | GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS), | |
860 | GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS), | |
861 | GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS), | |
862 | ||
863 | /* PD_GMAC */ | |
864 | GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED, | |
865 | PX30_CLKGATE_CON(8), 0, GFLAGS), | |
866 | GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, | |
867 | PX30_CLKGATE_CON(8), 2, GFLAGS), | |
868 | GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED, | |
869 | PX30_CLKGATE_CON(8), 1, GFLAGS), | |
870 | GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, | |
871 | PX30_CLKGATE_CON(8), 3, GFLAGS), | |
872 | }; | |
873 | ||
874 | static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = { | |
875 | /* | |
876 | * Clock-Architecture Diagram 2 | |
877 | */ | |
878 | ||
879 | COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, | |
880 | PX30_PMU_CLKSEL_CON(1), 0, | |
881 | PX30_PMU_CLKGATE_CON(0), 13, GFLAGS, | |
882 | &px30_rtc32k_pmu_fracmux), | |
883 | ||
884 | COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED, | |
885 | PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS, | |
886 | PX30_PMU_CLKGATE_CON(0), 12, GFLAGS), | |
887 | ||
888 | COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0, | |
889 | PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS, | |
890 | PX30_PMU_CLKGATE_CON(0), 14, GFLAGS), | |
891 | COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, | |
892 | PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS, | |
893 | PX30_PMU_CLKGATE_CON(0), 15, GFLAGS), | |
894 | ||
895 | COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0, | |
896 | PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS, | |
897 | PX30_PMU_CLKGATE_CON(1), 0, GFLAGS), | |
898 | COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0, | |
899 | PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS, | |
900 | PX30_PMU_CLKGATE_CON(1), 1, GFLAGS), | |
901 | COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT, | |
902 | PX30_PMU_CLKSEL_CON(5), 0, | |
903 | PX30_PMU_CLKGATE_CON(1), 2, GFLAGS, | |
904 | &px30_uart0_pmu_fracmux), | |
905 | GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT, | |
906 | PX30_PMU_CLKGATE_CON(1), 3, GFLAGS), | |
907 | ||
908 | GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, | |
909 | PX30_PMU_CLKGATE_CON(1), 4, GFLAGS), | |
910 | ||
911 | COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0, | |
912 | PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, | |
913 | PX30_PMU_CLKGATE_CON(0), 0, GFLAGS), | |
914 | ||
915 | COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0, | |
916 | PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS, | |
917 | PX30_PMU_CLKGATE_CON(1), 8, GFLAGS), | |
918 | COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT, | |
919 | PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, | |
920 | PX30_PMU_CLKGATE_CON(1), 9, GFLAGS), | |
921 | COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT, | |
922 | PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS, | |
923 | PX30_PMU_CLKGATE_CON(1), 10, GFLAGS), | |
924 | ||
925 | /* | |
926 | * Clock-Architecture Diagram 9 | |
927 | */ | |
928 | ||
929 | /* PD_PMU */ | |
930 | GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS), | |
931 | GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS), | |
932 | GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS), | |
933 | GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS), | |
934 | GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS), | |
935 | GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS), | |
936 | GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS), | |
937 | GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS), | |
938 | }; | |
939 | ||
940 | static const char *const px30_pmucru_critical_clocks[] __initconst = { | |
941 | "aclk_bus_pre", | |
942 | "pclk_bus_pre", | |
943 | "hclk_bus_pre", | |
944 | "aclk_peri_pre", | |
945 | "hclk_peri_pre", | |
946 | "aclk_gpu_niu", | |
947 | "pclk_top_pre", | |
948 | "pclk_pmu_pre", | |
949 | "hclk_usb_niu", | |
950 | "pll_npll", | |
951 | "usb480m", | |
952 | "clk_uart2", | |
953 | "pclk_uart2", | |
954 | }; | |
955 | ||
956 | static void __init px30_clk_init(struct device_node *np) | |
957 | { | |
958 | struct rockchip_clk_provider *ctx; | |
959 | void __iomem *reg_base; | |
960 | struct clk *clk; | |
961 | ||
962 | reg_base = of_iomap(np, 0); | |
963 | if (!reg_base) { | |
964 | pr_err("%s: could not map cru region\n", __func__); | |
965 | return; | |
966 | } | |
967 | ||
968 | ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); | |
969 | if (IS_ERR(ctx)) { | |
970 | pr_err("%s: rockchip clk init failed\n", __func__); | |
971 | iounmap(reg_base); | |
972 | return; | |
973 | } | |
974 | ||
975 | /* aclk_dmac is controlled by sgrf_soc_con1[11]. */ | |
976 | clk = clk_register_fixed_factor(NULL, "aclk_dmac", "aclk_bus_pre", 0, 1, 1); | |
977 | if (IS_ERR(clk)) | |
978 | pr_warn("%s: could not register clock aclk_dmac: %ld\n", | |
979 | __func__, PTR_ERR(clk)); | |
980 | else | |
981 | rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC); | |
982 | ||
983 | rockchip_clk_register_plls(ctx, px30_pll_clks, | |
984 | ARRAY_SIZE(px30_pll_clks), | |
985 | PX30_GRF_SOC_STATUS0); | |
986 | rockchip_clk_register_branches(ctx, px30_clk_branches, | |
987 | ARRAY_SIZE(px30_clk_branches)); | |
988 | ||
989 | rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", | |
990 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), | |
991 | &px30_cpuclk_data, px30_cpuclk_rates, | |
992 | ARRAY_SIZE(px30_cpuclk_rates)); | |
993 | ||
994 | rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0), | |
995 | ROCKCHIP_SOFTRST_HIWORD_MASK); | |
996 | ||
997 | rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL); | |
998 | ||
999 | rockchip_clk_of_add_provider(np, ctx); | |
1000 | } | |
1001 | CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init); | |
1002 | ||
1003 | static void __init px30_pmu_clk_init(struct device_node *np) | |
1004 | { | |
1005 | struct rockchip_clk_provider *ctx; | |
1006 | void __iomem *reg_base; | |
1007 | ||
1008 | reg_base = of_iomap(np, 0); | |
1009 | if (!reg_base) { | |
1010 | pr_err("%s: could not map cru pmu region\n", __func__); | |
1011 | return; | |
1012 | } | |
1013 | ||
1014 | ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); | |
1015 | if (IS_ERR(ctx)) { | |
1016 | pr_err("%s: rockchip pmu clk init failed\n", __func__); | |
1017 | return; | |
1018 | } | |
1019 | ||
1020 | rockchip_clk_register_plls(ctx, px30_pmu_pll_clks, | |
1021 | ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0); | |
1022 | ||
1023 | rockchip_clk_register_branches(ctx, px30_clk_pmu_branches, | |
1024 | ARRAY_SIZE(px30_clk_pmu_branches)); | |
1025 | ||
1026 | rockchip_clk_protect_critical(px30_pmucru_critical_clocks, | |
1027 | ARRAY_SIZE(px30_pmucru_critical_clocks)); | |
1028 | ||
1029 | rockchip_clk_of_add_provider(np, ctx); | |
1030 | } | |
1031 | CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init); |