[thirdparty/u-boot.git] / drivers / clk / rockchip / clk_rk322x.c

// SPDX-License-Identifier: GPL-2.0
/*
 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/log2.h>

enum {
	VCO_MAX_HZ	= 3200U * 1000000,
	VCO_MIN_HZ	= 800 * 1000000,
	OUTPUT_MAX_HZ	= 3200U * 1000000,
	OUTPUT_MIN_HZ	= 24 * 1000000,
};

#define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))

#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
	.refdiv = _refdiv,\
	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
			 #hz "Hz cannot be hit with PLL "\
			 "divisors on line " __stringify(__LINE__));

/* use integer mode*/
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);

static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
			 const struct pll_div *div)
{
	int pll_id = rk_pll_id(clk_id);
	struct rk322x_pll *pll = &cru->pll[pll_id];

	/* All PLLs have same VCO and output frequency range restrictions. */
	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;

	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
	      pll, div->fbdiv, div->refdiv, div->postdiv1,
	      div->postdiv2, vco_hz, output_hz);
	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);

	/* use integer mode */
	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
	/* Power down */
	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);

	rk_clrsetreg(&pll->con0,
		     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
		     (div->postdiv2 << PLL_POSTDIV2_SHIFT |
		     div->refdiv << PLL_REFDIV_SHIFT));

	/* Power Up */
	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);

	/* waiting for pll lock */
	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
		udelay(1);

	return 0;
}

static void rkclk_init(struct rk322x_cru *cru)
{
	u32 aclk_div;
	u32 hclk_div;
	u32 pclk_div;

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK | APLL_MODE_MASK,
		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
		     APLL_MODE_SLOW << APLL_MODE_SHIFT);

	/* init pll */
	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);

	/*
	 * select apll as cpu/core clock pll source and
	 * set up dependent divisors for PERI and ACLK clocks.
	 * core hz : apll = 1:1
	 */
	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);

	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);

	rk_clrsetreg(&cru->cru_clksel_con[0],
		     CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
		     CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
		     0 << CORE_DIV_CON_SHIFT);

	rk_clrsetreg(&cru->cru_clksel_con[1],
		     CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
		     aclk_div << CORE_ACLK_DIV_SHIFT |
		     pclk_div << CORE_PERI_DIV_SHIFT);

	/*
	 * select gpll as pd_bus bus clock source and
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);

	pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
	assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);

	hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
	assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);

	rk_clrsetreg(&cru->cru_clksel_con[0],
		     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
		     BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
		     aclk_div << BUS_ACLK_DIV_SHIFT);

	rk_clrsetreg(&cru->cru_clksel_con[1],
		     BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
		     pclk_div << BUS_PCLK_DIV_SHIFT |
		     hclk_div << BUS_HCLK_DIV_SHIFT);

	/*
	 * select gpll as pd_peri bus clock source and
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);

	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
	assert((1 << hclk_div) * PERI_HCLK_HZ ==
		PERI_ACLK_HZ && (hclk_div < 0x4));

	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
	assert((1 << pclk_div) * PERI_PCLK_HZ ==
		PERI_ACLK_HZ && pclk_div < 0x8);

	rk_clrsetreg(&cru->cru_clksel_con[10],
		     PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
		     PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
		     PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
		     pclk_div << PERI_PCLK_DIV_SHIFT |
		     hclk_div << PERI_HCLK_DIV_SHIFT |
		     aclk_div << PERI_ACLK_DIV_SHIFT);

	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK | APLL_MODE_MASK,
		     GPLL_MODE_NORM << GPLL_MODE_SHIFT |
		     APLL_MODE_NORM << APLL_MODE_SHIFT);
}

/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
				   enum rk_clk_id clk_id)
{
	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
	uint32_t con;
	int pll_id = rk_pll_id(clk_id);
	struct rk322x_pll *pll = &cru->pll[pll_id];
	static u8 clk_shift[CLK_COUNT] = {
		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
		GPLL_MODE_SHIFT, 0xff
	};
	static u32 clk_mask[CLK_COUNT] = {
		0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
		GPLL_MODE_MASK, 0xff
	};
	uint shift;
	uint mask;

	con = readl(&cru->cru_mode_con);
	shift = clk_shift[clk_id];
	mask = clk_mask[clk_id];

	switch ((con & mask) >> shift) {
	case GPLL_MODE_SLOW:
		return OSC_HZ;
	case GPLL_MODE_NORM:

		/* normal mode */
		con = readl(&pll->con0);
		postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
		fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
		con = readl(&pll->con1);
		postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
		refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
		return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
	default:
		return 32768;
	}
}

static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
				  int periph)
{
	uint src_rate;
	uint div, mux;
	u32 con;

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case SCLK_EMMC_SAMPLE:
		con = readl(&cru->cru_clksel_con[11]);
		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
		con = readl(&cru->cru_clksel_con[12]);
		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		con = readl(&cru->cru_clksel_con[11]);
		mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
		break;
	default:
		return -EINVAL;
	}

	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
	return DIV_TO_RATE(src_rate, div) / 2;
}

static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
{
	ulong ret;

	/*
	 * The gmac clock can be derived either from an external clock
	 * or can be generated from internally by a divider from SCLK_MAC.
	 */
	if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
		/* An external clock will always generate the right rate... */
		ret = freq;
	} else {
		u32 con = readl(&cru->cru_clksel_con[5]);
		ulong pll_rate;
		u8 div;

		if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
			pll_rate = GPLL_HZ;
		else
			/* CPLL is not set */
			return -EPERM;

		div = DIV_ROUND_UP(pll_rate, freq) - 1;
		if (div <= 0x1f)
			rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
				     div << CLK_MAC_DIV_SHIFT);
		else
			debug("Unsupported div for gmac:%d\n", div);

		return DIV_TO_RATE(pll_rate, div);
	}

	return ret;
}

static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
				  int periph, uint freq)
{
	int src_clk_div;
	int mux;

	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);

	/* mmc clock defaulg div 2 internal, need provide double in cru */
	src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);

	if (src_clk_div > 128) {
		src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
		assert(src_clk_div - 1 < 128);
		mux = EMMC_SEL_24M;
	} else {
		mux = EMMC_SEL_GPLL;
	}

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case SCLK_EMMC_SAMPLE:
		rk_clrsetreg(&cru->cru_clksel_con[11],
			     EMMC_PLL_MASK,
			     mux << EMMC_PLL_SHIFT);
		rk_clrsetreg(&cru->cru_clksel_con[12],
			     EMMC_DIV_MASK,
			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		rk_clrsetreg(&cru->cru_clksel_con[11],
			     MMC0_PLL_MASK | MMC0_DIV_MASK,
			     mux << MMC0_PLL_SHIFT |
			     (src_clk_div - 1) << MMC0_DIV_SHIFT);
		break;
	default:
		return -EINVAL;
	}

	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
}

static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
{
	struct pll_div dpll_cfg;

	/*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
	switch (set_rate) {
	case 400*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
		break;
	case 600*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
		break;
	case 800*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
		break;
	}

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
		     DPLL_MODE_NORM << DPLL_MODE_SHIFT);

	return set_rate;
}
static ulong rk322x_clk_get_rate(struct clk *clk)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	ulong rate, gclk_rate;

	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	switch (clk->id) {
	case 0 ... 63:
		rate = rkclk_pll_get_rate(priv->cru, clk->id);
		break;
	case HCLK_EMMC:
	case SCLK_EMMC:
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
		break;
	default:
		return -ENOENT;
	}

	return rate;
}

static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	ulong new_rate, gclk_rate;

	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	switch (clk->id) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
						clk->id, rate);
		break;
	case CLK_DDR:
		new_rate = rk322x_ddr_set_clk(priv->cru, rate);
		break;
	case SCLK_MAC:
		new_rate = rk322x_mac_set_clk(priv->cru, rate);
		break;
	case PLL_GPLL:
		return 0;
	default:
		return -ENOENT;
	}

	return new_rate;
}

static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	struct rk322x_cru *cru = priv->cru;

	/*
	 * If the requested parent is in the same clock-controller and the id
	 * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
	 */
	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
		debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
		return 0;
	}

	/*
	 * If the requested parent is in the same clock-controller and the id
	 * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
	 */
	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
		debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
		return 0;
	}

	return -EINVAL;
}

static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	const char *clock_output_name;
	struct rk322x_cru *cru = priv->cru;
	int ret;

	ret = dev_read_string_index(parent->dev, "clock-output-names",
				    parent->id, &clock_output_name);
	if (ret < 0)
		return -ENODATA;

	if (!strcmp(clock_output_name, "ext_gmac")) {
		debug("%s: switching gmac extclk to ext_gmac\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
		return 0;
	} else if (!strcmp(clock_output_name, "phy_50m_out")) {
		debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
		return 0;
	}

	return -EINVAL;
}

static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
{
	switch (clk->id) {
	case SCLK_MAC:
		return rk322x_gmac_set_parent(clk, parent);
	case SCLK_MAC_EXTCLK:
		return rk322x_gmac_extclk_set_parent(clk, parent);
	}

	debug("%s: unsupported clk %ld\n", __func__, clk->id);
	return -ENOENT;
}

static struct clk_ops rk322x_clk_ops = {
	.get_rate	= rk322x_clk_get_rate,
	.set_rate	= rk322x_clk_set_rate,
	.set_parent	= rk322x_clk_set_parent,
};

static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
{
	struct rk322x_clk_priv *priv = dev_get_priv(dev);

	priv->cru = dev_read_addr_ptr(dev);

	return 0;
}

static int rk322x_clk_probe(struct udevice *dev)
{
	struct rk322x_clk_priv *priv = dev_get_priv(dev);

	rkclk_init(priv->cru);

	return 0;
}

static int rk322x_clk_bind(struct udevice *dev)
{
	int ret;
	struct udevice *sys_child;
	struct sysreset_reg *priv;

	/* The reset driver does not have a device node, so bind it here */
	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
				 &sys_child);
	if (ret) {
		debug("Warning: No sysreset driver: ret=%d\n", ret);
	} else {
		priv = malloc(sizeof(struct sysreset_reg));
		priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
						    cru_glb_srst_fst_value);
		priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
						    cru_glb_srst_snd_value);
		sys_child->priv = priv;
	}

#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
	ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
	ret = rockchip_reset_bind(dev, ret, 9);
	if (ret)
		debug("Warning: software reset driver bind faile\n");
#endif

	return 0;
}

static const struct udevice_id rk322x_clk_ids[] = {
	{ .compatible = "rockchip,rk3228-cru" },
	{ }
};

U_BOOT_DRIVER(rockchip_rk322x_cru) = {
	.name		= "clk_rk322x",
	.id		= UCLASS_CLK,
	.of_match	= rk322x_clk_ids,
	.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
	.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
	.ops		= &rk322x_clk_ops,
	.bind		= rk322x_clk_bind,
	.probe		= rk322x_clk_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
045029cb KY	2	/*
045029cb KY	3	* (C) Copyright 2017 Rockchip Electronics Co., Ltd
045029cb KY	4	*/
	5
	6	#include <common.h>
	7	#include <clk-uclass.h>
	8	#include <dm.h>
	9	#include <errno.h>
336d4615	10	#include <malloc.h>
045029cb KY	11	#include <syscon.h>
045029cb KY	12	#include <asm/io.h>
15f09a1a KY	13	#include <asm/arch-rockchip/clock.h>
	14	#include <asm/arch-rockchip/cru_rk322x.h>
	15	#include <asm/arch-rockchip/hardware.h>
045029cb KY	16	#include <dm/lists.h>
	17	#include <dt-bindings/clock/rk3228-cru.h>
	18	#include <linux/log2.h>
	19
045029cb KY	20	enum {
	21	VCO_MAX_HZ = 3200U * 1000000,
	22	VCO_MIN_HZ = 800 * 1000000,
	23	OUTPUT_MAX_HZ = 3200U * 1000000,
	24	OUTPUT_MIN_HZ = 24 * 1000000,
	25	};
	26
045029cb KY	27	#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
	28
	29	#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
	30	.refdiv = _refdiv,\
	31	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
	32	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
	33	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
	34	OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
	35	#hz "Hz cannot be hit with PLL "\
	36	"divisors on line " __stringify(__LINE__));
	37
	38	/* use integer mode*/
	39	static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
	40	static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
	41
	42	static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
	43	const struct pll_div *div)
	44	{
	45	int pll_id = rk_pll_id(clk_id);
	46	struct rk322x_pll *pll = &cru->pll[pll_id];
	47
	48	/* All PLLs have same VCO and output frequency range restrictions. */
	49	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
	50	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
	51
	52	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
	53	pll, div->fbdiv, div->refdiv, div->postdiv1,
	54	div->postdiv2, vco_hz, output_hz);
	55	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	56	output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
	57
	58	/* use integer mode */
	59	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
	60	/* Power down */
	61	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
	62
	63	rk_clrsetreg(&pll->con0,
	64	PLL_POSTDIV1_MASK \| PLL_FBDIV_MASK,
	65	(div->postdiv1 << PLL_POSTDIV1_SHIFT) \| div->fbdiv);
	66	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK \| PLL_REFDIV_MASK,
	67	(div->postdiv2 << PLL_POSTDIV2_SHIFT \|
	68	div->refdiv << PLL_REFDIV_SHIFT));
	69
	70	/* Power Up */
	71	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
	72
	73	/* waiting for pll lock */
	74	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
	75	udelay(1);
	76
	77	return 0;
	78	}
	79
	80	static void rkclk_init(struct rk322x_cru *cru)
	81	{
	82	u32 aclk_div;
	83	u32 hclk_div;
	84	u32 pclk_div;
	85
	86	/* pll enter slow-mode */
	87	rk_clrsetreg(&cru->cru_mode_con,
	88	GPLL_MODE_MASK \| APLL_MODE_MASK,
	89	GPLL_MODE_SLOW << GPLL_MODE_SHIFT \|
	90	APLL_MODE_SLOW << APLL_MODE_SHIFT);
91
92	/* init pll */
93	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
94	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
95
96	/*
97	* select apll as cpu/core clock pll source and
98	* set up dependent divisors for PERI and ACLK clocks.
99	* core hz : apll = 1:1
100	*/
101	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
102	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
103
104	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
105	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
106
107	rk_clrsetreg(&cru->cru_clksel_con[0],
108	CORE_CLK_PLL_SEL_MASK \| CORE_DIV_CON_MASK,
109	CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT \|
110	0 << CORE_DIV_CON_SHIFT);
111
112	rk_clrsetreg(&cru->cru_clksel_con[1],
113	CORE_ACLK_DIV_MASK \| CORE_PERI_DIV_MASK,
114	aclk_div << CORE_ACLK_DIV_SHIFT \|
115	pclk_div << CORE_PERI_DIV_SHIFT);
116
117	/*
f3f6591c	118	* select gpll as pd_bus bus clock source and
045029cb KY	119	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
	120	*/
	121	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
	122	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
	123
f3f6591c	124	pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
5793e8c2	125	assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
045029cb	126
f3f6591c	127	hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
5793e8c2	128	assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
045029cb KY	129
	130	rk_clrsetreg(&cru->cru_clksel_con[0],
	131	BUS_ACLK_PLL_SEL_MASK \| BUS_ACLK_DIV_MASK,
	132	BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT \|
	133	aclk_div << BUS_ACLK_DIV_SHIFT);
	134
	135	rk_clrsetreg(&cru->cru_clksel_con[1],
	136	BUS_PCLK_DIV_MASK \| BUS_HCLK_DIV_MASK,
	137	pclk_div << BUS_PCLK_DIV_SHIFT \|
	138	hclk_div << BUS_HCLK_DIV_SHIFT);
	139
	140	/*
	141	* select gpll as pd_peri bus clock source and
	142	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
	143	*/
	144	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
	145	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
	146
	147	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
	148	assert((1 << hclk_div) * PERI_HCLK_HZ ==
	149	PERI_ACLK_HZ && (hclk_div < 0x4));
	150
	151	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
	152	assert((1 << pclk_div) * PERI_PCLK_HZ ==
	153	PERI_ACLK_HZ && pclk_div < 0x8);
	154
	155	rk_clrsetreg(&cru->cru_clksel_con[10],
	156	PERI_PLL_SEL_MASK \| PERI_PCLK_DIV_MASK \|
	157	PERI_HCLK_DIV_MASK \| PERI_ACLK_DIV_MASK,
	158	PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT \|
	159	pclk_div << PERI_PCLK_DIV_SHIFT \|
	160	hclk_div << PERI_HCLK_DIV_SHIFT \|
	161	aclk_div << PERI_ACLK_DIV_SHIFT);
	162
	163	/* PLL enter normal-mode */
	164	rk_clrsetreg(&cru->cru_mode_con,
	165	GPLL_MODE_MASK \| APLL_MODE_MASK,
	166	GPLL_MODE_NORM << GPLL_MODE_SHIFT \|
	167	APLL_MODE_NORM << APLL_MODE_SHIFT);
	168	}
	169
	170	/* Get pll rate by id */
	171	static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
	172	enum rk_clk_id clk_id)
	173	{
	174	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
	175	uint32_t con;
	176	int pll_id = rk_pll_id(clk_id);
	177	struct rk322x_pll *pll = &cru->pll[pll_id];
	178	static u8 clk_shift[CLK_COUNT] = {
	179	0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
	180	GPLL_MODE_SHIFT, 0xff
	181	};
	182	static u32 clk_mask[CLK_COUNT] = {
	183	0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
	184	GPLL_MODE_MASK, 0xff
	185	};
	186	uint shift;
	187	uint mask;
	188
	189	con = readl(&cru->cru_mode_con);
	190	shift = clk_shift[clk_id];
	191	mask = clk_mask[clk_id];
	192
193	switch ((con & mask) >> shift) {
194	case GPLL_MODE_SLOW:
195	return OSC_HZ;
196	case GPLL_MODE_NORM:
197
198	/* normal mode */
199	con = readl(&pll->con0);
200	postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
201	fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
202	con = readl(&pll->con1);
203	postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
204	refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
205	return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
206	default:
207	return 32768;
208	}
209	}
210
211	static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
212	int periph)
213	{
214	uint src_rate;
215	uint div, mux;
216	u32 con;
217
218	switch (periph) {
219	case HCLK_EMMC:
220	case SCLK_EMMC:
e4d0d612	221	case SCLK_EMMC_SAMPLE:
045029cb KY	222	con = readl(&cru->cru_clksel_con[11]);
	223	mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
	224	con = readl(&cru->cru_clksel_con[12]);
	225	div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
	226	break;
	227	case HCLK_SDMMC:
	228	case SCLK_SDMMC:
	229	con = readl(&cru->cru_clksel_con[11]);
	230	mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
	231	div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
	232	break;
	233	default:
	234	return -EINVAL;
	235	}
	236
	237	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
3a94d75d	238	return DIV_TO_RATE(src_rate, div) / 2;
045029cb KY	239	}
045029cb KY	240
5bb616c6 DW	241	static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
	242	{
	243	ulong ret;
	244
	245	/*
	246	* The gmac clock can be derived either from an external clock
	247	* or can be generated from internally by a divider from SCLK_MAC.
	248	*/
	249	if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
	250	/* An external clock will always generate the right rate... */
	251	ret = freq;
	252	} else {
	253	u32 con = readl(&cru->cru_clksel_con[5]);
	254	ulong pll_rate;
	255	u8 div;
	256
	257	if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
	258	pll_rate = GPLL_HZ;
	259	else
	260	/* CPLL is not set */
	261	return -EPERM;
	262
	263	div = DIV_ROUND_UP(pll_rate, freq) - 1;
	264	if (div <= 0x1f)
	265	rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
	266	div << CLK_MAC_DIV_SHIFT);
	267	else
	268	debug("Unsupported div for gmac:%d\n", div);
	269
	270	return DIV_TO_RATE(pll_rate, div);
	271	}
	272
	273	return ret;
	274	}
	275
045029cb KY	276	static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
	277	int periph, uint freq)
	278	{
	279	int src_clk_div;
	280	int mux;
	281
	282	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
	283
3a94d75d KY	284	/* mmc clock defaulg div 2 internal, need provide double in cru */
3a94d75d KY	285	src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
045029cb	286
217273cd	287	if (src_clk_div > 128) {
3a94d75d	288	src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
217273cd	289	assert(src_clk_div - 1 < 128);
045029cb KY	290	mux = EMMC_SEL_24M;
	291	} else {
	292	mux = EMMC_SEL_GPLL;
	293	}
	294
	295	switch (periph) {
	296	case HCLK_EMMC:
	297	case SCLK_EMMC:
e4d0d612	298	case SCLK_EMMC_SAMPLE:
045029cb KY	299	rk_clrsetreg(&cru->cru_clksel_con[11],
	300	EMMC_PLL_MASK,
	301	mux << EMMC_PLL_SHIFT);
	302	rk_clrsetreg(&cru->cru_clksel_con[12],
	303	EMMC_DIV_MASK,
	304	(src_clk_div - 1) << EMMC_DIV_SHIFT);
	305	break;
	306	case HCLK_SDMMC:
	307	case SCLK_SDMMC:
	308	rk_clrsetreg(&cru->cru_clksel_con[11],
	309	MMC0_PLL_MASK \| MMC0_DIV_MASK,
	310	mux << MMC0_PLL_SHIFT \|
	311	(src_clk_div - 1) << MMC0_DIV_SHIFT);
	312	break;
	313	default:
	314	return -EINVAL;
	315	}
	316
	317	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
	318	}
	319
	320	static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
	321	{
	322	struct pll_div dpll_cfg;
	323
	324	/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
	325	switch (set_rate) {
	326	case 400*MHz:
	327	dpll_cfg = (struct pll_div)
	328	{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
	329	break;
	330	case 600*MHz:
	331	dpll_cfg = (struct pll_div)
	332	{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
	333	break;
	334	case 800*MHz:
	335	dpll_cfg = (struct pll_div)
	336	{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
	337	break;
	338	}
	339
	340	/* pll enter slow-mode */
	341	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
	342	DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
	343	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
	344	/* PLL enter normal-mode */
	345	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
	346	DPLL_MODE_NORM << DPLL_MODE_SHIFT);
	347
	348	return set_rate;
	349	}
	350	static ulong rk322x_clk_get_rate(struct clk *clk)
	351	{
	352	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	353	ulong rate, gclk_rate;
	354
	355	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	356	switch (clk->id) {
	357	case 0 ... 63:
	358	rate = rkclk_pll_get_rate(priv->cru, clk->id);
	359	break;
	360	case HCLK_EMMC:
	361	case SCLK_EMMC:
	362	case HCLK_SDMMC:
363	case SCLK_SDMMC:
364	rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
365	break;
366	default:
367	return -ENOENT;
368	}
369
370	return rate;
371	}
372
373	static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
374	{
375	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
376	ulong new_rate, gclk_rate;
377
378	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
379	switch (clk->id) {
380	case HCLK_EMMC:
381	case SCLK_EMMC:
382	case HCLK_SDMMC:
383	case SCLK_SDMMC:
384	new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
385	clk->id, rate);
386	break;
387	case CLK_DDR:
388	new_rate = rk322x_ddr_set_clk(priv->cru, rate);
389	break;
5bb616c6 DW	390	case SCLK_MAC:
	391	new_rate = rk322x_mac_set_clk(priv->cru, rate);
	392	break;
	393	case PLL_GPLL:
	394	return 0;
045029cb KY	395	default:
	396	return -ENOENT;
	397	}
	398
	399	return new_rate;
	400	}
	401
5bb616c6 DW	402	static int rk322x_gmac_set_parent(struct clk clk, struct clk parent)
	403	{
	404	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	405	struct rk322x_cru *cru = priv->cru;
	406
	407	/*
	408	* If the requested parent is in the same clock-controller and the id
	409	* is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
	410	*/
	411	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
	412	debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
	413	rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
	414	return 0;
	415	}
	416
	417	/*
	418	* If the requested parent is in the same clock-controller and the id
	419	* is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
	420	*/
	421	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
	422	debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
	423	rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
	424	return 0;
	425	}
	426
	427	return -EINVAL;
	428	}
	429
	430	static int rk322x_gmac_extclk_set_parent(struct clk clk, struct clk parent)
	431	{
	432	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	433	const char *clock_output_name;
	434	struct rk322x_cru *cru = priv->cru;
	435	int ret;
	436
	437	ret = dev_read_string_index(parent->dev, "clock-output-names",
	438	parent->id, &clock_output_name);
	439	if (ret < 0)
	440	return -ENODATA;
	441
	442	if (!strcmp(clock_output_name, "ext_gmac")) {
	443	debug("%s: switching gmac extclk to ext_gmac\n", __func__);
	444	rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
	445	return 0;
	446	} else if (!strcmp(clock_output_name, "phy_50m_out")) {
	447	debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
	448	rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
	449	return 0;
	450	}
	451
	452	return -EINVAL;
	453	}
	454
	455	static int rk322x_clk_set_parent(struct clk clk, struct clk parent)
	456	{
	457	switch (clk->id) {
	458	case SCLK_MAC:
	459	return rk322x_gmac_set_parent(clk, parent);
	460	case SCLK_MAC_EXTCLK:
	461	return rk322x_gmac_extclk_set_parent(clk, parent);
	462	}
	463
	464	debug("%s: unsupported clk %ld\n", __func__, clk->id);
	465	return -ENOENT;
466	}
467
045029cb KY	468	static struct clk_ops rk322x_clk_ops = {
	469	.get_rate = rk322x_clk_get_rate,
	470	.set_rate = rk322x_clk_set_rate,
5bb616c6	471	.set_parent = rk322x_clk_set_parent,
045029cb KY	472	};
	473
	474	static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
	475	{
	476	struct rk322x_clk_priv *priv = dev_get_priv(dev);
	477
99b8553c	478	priv->cru = dev_read_addr_ptr(dev);
045029cb KY	479
	480	return 0;
	481	}
	482
	483	static int rk322x_clk_probe(struct udevice *dev)
	484	{
	485	struct rk322x_clk_priv *priv = dev_get_priv(dev);
	486
	487	rkclk_init(priv->cru);
	488
	489	return 0;
	490	}
	491
	492	static int rk322x_clk_bind(struct udevice *dev)
	493	{
	494	int ret;
f24e36da KY	495	struct udevice *sys_child;
f24e36da KY	496	struct sysreset_reg *priv;
045029cb KY	497
045029cb KY	498	/* The reset driver does not have a device node, so bind it here */
f24e36da KY	499	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
	500	&sys_child);
	501	if (ret) {
	502	debug("Warning: No sysreset driver: ret=%d\n", ret);
	503	} else {
	504	priv = malloc(sizeof(struct sysreset_reg));
	505	priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
	506	cru_glb_srst_fst_value);
	507	priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
	508	cru_glb_srst_snd_value);
	509	sys_child->priv = priv;
	510	}
045029cb	511
a5ada25e	512	#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
538f67c3 EZ	513	ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
	514	ret = rockchip_reset_bind(dev, ret, 9);
	515	if (ret)
	516	debug("Warning: software reset driver bind faile\n");
	517	#endif
	518
045029cb KY	519	return 0;
	520	}
	521
	522	static const struct udevice_id rk322x_clk_ids[] = {
	523	{ .compatible = "rockchip,rk3228-cru" },
	524	{ }
	525	};
	526
	527	U_BOOT_DRIVER(rockchip_rk322x_cru) = {
	528	.name = "clk_rk322x",
	529	.id = UCLASS_CLK,
	530	.of_match = rk322x_clk_ids,
	531	.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
	532	.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
	533	.ops = &rk322x_clk_ops,
	534	.bind = rk322x_clk_bind,
	535	.probe = rk322x_clk_probe,
	536	};