[thirdparty/u-boot.git] / drivers / clk / rockchip / clk_rk322x.c

// SPDX-License-Identifier: GPL-2.0
/*
 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/log2.h>

enum {
	VCO_MAX_HZ	= 3200U * 1000000,
	VCO_MIN_HZ	= 800 * 1000000,
	OUTPUT_MAX_HZ	= 3200U * 1000000,
	OUTPUT_MIN_HZ	= 24 * 1000000,
};

#define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))

#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
	.refdiv = _refdiv,\
	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
			 #hz "Hz cannot be hit with PLL "\
			 "divisors on line " __stringify(__LINE__));

/* use integer mode*/
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);

static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
			 const struct pll_div *div)
{
	int pll_id = rk_pll_id(clk_id);
	struct rk322x_pll *pll = &cru->pll[pll_id];

	/* All PLLs have same VCO and output frequency range restrictions. */
	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;

	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
	      pll, div->fbdiv, div->refdiv, div->postdiv1,
	      div->postdiv2, vco_hz, output_hz);
	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);

	/* use integer mode */
	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
	/* Power down */
	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);

	rk_clrsetreg(&pll->con0,
		     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
		     (div->postdiv2 << PLL_POSTDIV2_SHIFT |
		     div->refdiv << PLL_REFDIV_SHIFT));

	/* Power Up */
	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);

	/* waiting for pll lock */
	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
		udelay(1);

	return 0;
}

static void rkclk_init(struct rk322x_cru *cru)
{
	u32 aclk_div;
	u32 hclk_div;
	u32 pclk_div;

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK | APLL_MODE_MASK,
		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
		     APLL_MODE_SLOW << APLL_MODE_SHIFT);

	/* init pll */
	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);

	/*
	 * select apll as cpu/core clock pll source and
	 * set up dependent divisors for PERI and ACLK clocks.
	 * core hz : apll = 1:1
	 */
	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);

	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);

	rk_clrsetreg(&cru->cru_clksel_con[0],
		     CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
		     CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
		     0 << CORE_DIV_CON_SHIFT);

	rk_clrsetreg(&cru->cru_clksel_con[1],
		     CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
		     aclk_div << CORE_ACLK_DIV_SHIFT |
		     pclk_div << CORE_PERI_DIV_SHIFT);

	/*
	 * select gpll as pd_bus bus clock source and
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);

	pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
	assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);

	hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
	assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);

	rk_clrsetreg(&cru->cru_clksel_con[0],
		     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
		     BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
		     aclk_div << BUS_ACLK_DIV_SHIFT);

	rk_clrsetreg(&cru->cru_clksel_con[1],
		     BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
		     pclk_div << BUS_PCLK_DIV_SHIFT |
		     hclk_div << BUS_HCLK_DIV_SHIFT);

	/*
	 * select gpll as pd_peri bus clock source and
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);

	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
	assert((1 << hclk_div) * PERI_HCLK_HZ ==
		PERI_ACLK_HZ && (hclk_div < 0x4));

	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
	assert((1 << pclk_div) * PERI_PCLK_HZ ==
		PERI_ACLK_HZ && pclk_div < 0x8);

	rk_clrsetreg(&cru->cru_clksel_con[10],
		     PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
		     PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
		     PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
		     pclk_div << PERI_PCLK_DIV_SHIFT |
		     hclk_div << PERI_HCLK_DIV_SHIFT |
		     aclk_div << PERI_ACLK_DIV_SHIFT);

	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK | APLL_MODE_MASK,
		     GPLL_MODE_NORM << GPLL_MODE_SHIFT |
		     APLL_MODE_NORM << APLL_MODE_SHIFT);
}

/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
				   enum rk_clk_id clk_id)
{
	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
	uint32_t con;
	int pll_id = rk_pll_id(clk_id);
	struct rk322x_pll *pll = &cru->pll[pll_id];
	static u8 clk_shift[CLK_COUNT] = {
		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
		GPLL_MODE_SHIFT, 0xff
	};
	static u32 clk_mask[CLK_COUNT] = {
		0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
		GPLL_MODE_MASK, 0xff
	};
	uint shift;
	uint mask;

	con = readl(&cru->cru_mode_con);
	shift = clk_shift[clk_id];
	mask = clk_mask[clk_id];

	switch ((con & mask) >> shift) {
	case GPLL_MODE_SLOW:
		return OSC_HZ;
	case GPLL_MODE_NORM:

		/* normal mode */
		con = readl(&pll->con0);
		postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
		fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
		con = readl(&pll->con1);
		postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
		refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
		return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
	default:
		return 32768;
	}
}

static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
				  int periph)
{
	uint src_rate;
	uint div, mux;
	u32 con;

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case SCLK_EMMC_SAMPLE:
		con = readl(&cru->cru_clksel_con[11]);
		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
		con = readl(&cru->cru_clksel_con[12]);
		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		con = readl(&cru->cru_clksel_con[11]);
		mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
		break;
	default:
		return -EINVAL;
	}

	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
	return DIV_TO_RATE(src_rate, div) / 2;
}

static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
{
	ulong ret;

	/*
	 * The gmac clock can be derived either from an external clock
	 * or can be generated from internally by a divider from SCLK_MAC.
	 */
	if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
		/* An external clock will always generate the right rate... */
		ret = freq;
	} else {
		u32 con = readl(&cru->cru_clksel_con[5]);
		ulong pll_rate;
		u8 div;

		if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
			pll_rate = GPLL_HZ;
		else
			/* CPLL is not set */
			return -EPERM;

		div = DIV_ROUND_UP(pll_rate, freq) - 1;
		if (div <= 0x1f)
			rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
				     div << CLK_MAC_DIV_SHIFT);
		else
			debug("Unsupported div for gmac:%d\n", div);

		return DIV_TO_RATE(pll_rate, div);
	}

	return ret;
}

static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
				  int periph, uint freq)
{
	int src_clk_div;
	int mux;

	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);

	/* mmc clock defaulg div 2 internal, need provide double in cru */
	src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);

	if (src_clk_div > 128) {
		src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
		assert(src_clk_div - 1 < 128);
		mux = EMMC_SEL_24M;
	} else {
		mux = EMMC_SEL_GPLL;
	}

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case SCLK_EMMC_SAMPLE:
		rk_clrsetreg(&cru->cru_clksel_con[11],
			     EMMC_PLL_MASK,
			     mux << EMMC_PLL_SHIFT);
		rk_clrsetreg(&cru->cru_clksel_con[12],
			     EMMC_DIV_MASK,
			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		rk_clrsetreg(&cru->cru_clksel_con[11],
			     MMC0_PLL_MASK | MMC0_DIV_MASK,
			     mux << MMC0_PLL_SHIFT |
			     (src_clk_div - 1) << MMC0_DIV_SHIFT);
		break;
	default:
		return -EINVAL;
	}

	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
}

static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
{
	struct pll_div dpll_cfg;

	/*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
	switch (set_rate) {
	case 400*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
		break;
	case 600*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
		break;
	case 800*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
		break;
	}

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
		     DPLL_MODE_NORM << DPLL_MODE_SHIFT);

	return set_rate;
}
static ulong rk322x_clk_get_rate(struct clk *clk)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	ulong rate, gclk_rate;

	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	switch (clk->id) {
	case 0 ... 63:
		rate = rkclk_pll_get_rate(priv->cru, clk->id);
		break;
	case HCLK_EMMC:
	case SCLK_EMMC:
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
		break;
	default:
		return -ENOENT;
	}

	return rate;
}

static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	ulong new_rate, gclk_rate;

	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	switch (clk->id) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
						clk->id, rate);
		break;
	case CLK_DDR:
		new_rate = rk322x_ddr_set_clk(priv->cru, rate);
		break;
	case SCLK_MAC:
		new_rate = rk322x_mac_set_clk(priv->cru, rate);
		break;
	case PLL_GPLL:
		return 0;
	default:
		return -ENOENT;
	}

	return new_rate;
}

static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	struct rk322x_cru *cru = priv->cru;

	/*
	 * If the requested parent is in the same clock-controller and the id
	 * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
	 */
	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
		debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
		return 0;
	}

	/*
	 * If the requested parent is in the same clock-controller and the id
	 * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
	 */
	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
		debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
		return 0;
	}

	return -EINVAL;
}

static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	const char *clock_output_name;
	struct rk322x_cru *cru = priv->cru;
	int ret;

	ret = dev_read_string_index(parent->dev, "clock-output-names",
				    parent->id, &clock_output_name);
	if (ret < 0)
		return -ENODATA;

	if (!strcmp(clock_output_name, "ext_gmac")) {
		debug("%s: switching gmac extclk to ext_gmac\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
		return 0;
	} else if (!strcmp(clock_output_name, "phy_50m_out")) {
		debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
		return 0;
	}

	return -EINVAL;
}

static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
{
	switch (clk->id) {
	case SCLK_MAC:
		return rk322x_gmac_set_parent(clk, parent);
	case SCLK_MAC_EXTCLK:
		return rk322x_gmac_extclk_set_parent(clk, parent);
	}

	debug("%s: unsupported clk %ld\n", __func__, clk->id);
	return -ENOENT;
}

static struct clk_ops rk322x_clk_ops = {
	.get_rate	= rk322x_clk_get_rate,
	.set_rate	= rk322x_clk_set_rate,
	.set_parent	= rk322x_clk_set_parent,
};

static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
{
	struct rk322x_clk_priv *priv = dev_get_priv(dev);

	priv->cru = dev_read_addr_ptr(dev);

	return 0;
}

static int rk322x_clk_probe(struct udevice *dev)
{
	struct rk322x_clk_priv *priv = dev_get_priv(dev);

	rkclk_init(priv->cru);

	return 0;
}

static int rk322x_clk_bind(struct udevice *dev)
{
	int ret;
	struct udevice *sys_child;
	struct sysreset_reg *priv;

	/* The reset driver does not have a device node, so bind it here */
	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
				 &sys_child);
	if (ret) {
		debug("Warning: No sysreset driver: ret=%d\n", ret);
	} else {
		priv = malloc(sizeof(struct sysreset_reg));
		priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
						    cru_glb_srst_fst_value);
		priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
						    cru_glb_srst_snd_value);
		sys_child->priv = priv;
	}

#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
	ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
	ret = rockchip_reset_bind(dev, ret, 9);
	if (ret)
		debug("Warning: software reset driver bind faile\n");
#endif

	return 0;
}

static const struct udevice_id rk322x_clk_ids[] = {
	{ .compatible = "rockchip,rk3228-cru" },
	{ }
};

U_BOOT_DRIVER(rockchip_rk322x_cru) = {
	.name		= "clk_rk322x",
	.id		= UCLASS_CLK,
	.of_match	= rk322x_clk_ids,
	.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
	.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
	.ops		= &rk322x_clk_ops,
	.bind		= rk322x_clk_bind,
	.probe		= rk322x_clk_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
045029cb KY	2	/*
045029cb KY	3	* (C) Copyright 2017 Rockchip Electronics Co., Ltd
045029cb KY	4	*/
	5
	6	#include <common.h>
	7	#include <clk-uclass.h>
	8	#include <dm.h>
	9	#include <errno.h>
f7ae49fc	10	#include <log.h>
336d4615	11	#include <malloc.h>
045029cb KY	12	#include <syscon.h>
045029cb KY	13	#include <asm/io.h>
15f09a1a KY	14	#include <asm/arch-rockchip/clock.h>
	15	#include <asm/arch-rockchip/cru_rk322x.h>
	16	#include <asm/arch-rockchip/hardware.h>
045029cb KY	17	#include <dm/lists.h>
	18	#include <dt-bindings/clock/rk3228-cru.h>
	19	#include <linux/log2.h>
	20
045029cb KY	21	enum {
	22	VCO_MAX_HZ = 3200U * 1000000,
	23	VCO_MIN_HZ = 800 * 1000000,
	24	OUTPUT_MAX_HZ = 3200U * 1000000,
	25	OUTPUT_MIN_HZ = 24 * 1000000,
	26	};
	27
045029cb KY	28	#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
	29
	30	#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
	31	.refdiv = _refdiv,\
	32	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
	33	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
	34	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
	35	OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
	36	#hz "Hz cannot be hit with PLL "\
	37	"divisors on line " __stringify(__LINE__));
	38
	39	/* use integer mode*/
	40	static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
	41	static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
	42
	43	static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
	44	const struct pll_div *div)
	45	{
	46	int pll_id = rk_pll_id(clk_id);
	47	struct rk322x_pll *pll = &cru->pll[pll_id];
	48
	49	/* All PLLs have same VCO and output frequency range restrictions. */
	50	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
	51	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
	52
	53	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
	54	pll, div->fbdiv, div->refdiv, div->postdiv1,
	55	div->postdiv2, vco_hz, output_hz);
	56	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	57	output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
	58
	59	/* use integer mode */
	60	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
	61	/* Power down */
	62	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
	63
	64	rk_clrsetreg(&pll->con0,
	65	PLL_POSTDIV1_MASK \| PLL_FBDIV_MASK,
	66	(div->postdiv1 << PLL_POSTDIV1_SHIFT) \| div->fbdiv);
	67	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK \| PLL_REFDIV_MASK,
	68	(div->postdiv2 << PLL_POSTDIV2_SHIFT \|
	69	div->refdiv << PLL_REFDIV_SHIFT));
	70
	71	/* Power Up */
	72	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
	73
	74	/* waiting for pll lock */
	75	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
	76	udelay(1);
	77
	78	return 0;
	79	}
	80
	81	static void rkclk_init(struct rk322x_cru *cru)
	82	{
	83	u32 aclk_div;
	84	u32 hclk_div;
	85	u32 pclk_div;
	86
	87	/* pll enter slow-mode */
	88	rk_clrsetreg(&cru->cru_mode_con,
	89	GPLL_MODE_MASK \| APLL_MODE_MASK,
	90	GPLL_MODE_SLOW << GPLL_MODE_SHIFT \|
	91	APLL_MODE_SLOW << APLL_MODE_SHIFT);
92
93	/* init pll */
94	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
95	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
96
97	/*
98	* select apll as cpu/core clock pll source and
99	* set up dependent divisors for PERI and ACLK clocks.
100	* core hz : apll = 1:1
101	*/
102	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
103	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
104
105	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
106	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
107
108	rk_clrsetreg(&cru->cru_clksel_con[0],
109	CORE_CLK_PLL_SEL_MASK \| CORE_DIV_CON_MASK,
110	CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT \|
111	0 << CORE_DIV_CON_SHIFT);
112
113	rk_clrsetreg(&cru->cru_clksel_con[1],
114	CORE_ACLK_DIV_MASK \| CORE_PERI_DIV_MASK,
115	aclk_div << CORE_ACLK_DIV_SHIFT \|
116	pclk_div << CORE_PERI_DIV_SHIFT);
117
118	/*
f3f6591c	119	* select gpll as pd_bus bus clock source and
045029cb KY	120	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
	121	*/
	122	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
	123	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
	124
f3f6591c	125	pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
5793e8c2	126	assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
045029cb	127
f3f6591c	128	hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
5793e8c2	129	assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
045029cb KY	130
	131	rk_clrsetreg(&cru->cru_clksel_con[0],
	132	BUS_ACLK_PLL_SEL_MASK \| BUS_ACLK_DIV_MASK,
	133	BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT \|
	134	aclk_div << BUS_ACLK_DIV_SHIFT);
	135
	136	rk_clrsetreg(&cru->cru_clksel_con[1],
	137	BUS_PCLK_DIV_MASK \| BUS_HCLK_DIV_MASK,
	138	pclk_div << BUS_PCLK_DIV_SHIFT \|
	139	hclk_div << BUS_HCLK_DIV_SHIFT);
	140
	141	/*
	142	* select gpll as pd_peri bus clock source and
	143	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
	144	*/
	145	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
	146	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
	147
	148	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
	149	assert((1 << hclk_div) * PERI_HCLK_HZ ==
	150	PERI_ACLK_HZ && (hclk_div < 0x4));
	151
	152	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
	153	assert((1 << pclk_div) * PERI_PCLK_HZ ==
	154	PERI_ACLK_HZ && pclk_div < 0x8);
	155
	156	rk_clrsetreg(&cru->cru_clksel_con[10],
	157	PERI_PLL_SEL_MASK \| PERI_PCLK_DIV_MASK \|
	158	PERI_HCLK_DIV_MASK \| PERI_ACLK_DIV_MASK,
	159	PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT \|
	160	pclk_div << PERI_PCLK_DIV_SHIFT \|
	161	hclk_div << PERI_HCLK_DIV_SHIFT \|
	162	aclk_div << PERI_ACLK_DIV_SHIFT);
	163
	164	/* PLL enter normal-mode */
	165	rk_clrsetreg(&cru->cru_mode_con,
	166	GPLL_MODE_MASK \| APLL_MODE_MASK,
	167	GPLL_MODE_NORM << GPLL_MODE_SHIFT \|
	168	APLL_MODE_NORM << APLL_MODE_SHIFT);
	169	}
	170
	171	/* Get pll rate by id */
	172	static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
	173	enum rk_clk_id clk_id)
	174	{
	175	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
	176	uint32_t con;
	177	int pll_id = rk_pll_id(clk_id);
	178	struct rk322x_pll *pll = &cru->pll[pll_id];
	179	static u8 clk_shift[CLK_COUNT] = {
	180	0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
	181	GPLL_MODE_SHIFT, 0xff
	182	};
	183	static u32 clk_mask[CLK_COUNT] = {
	184	0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
	185	GPLL_MODE_MASK, 0xff
	186	};
	187	uint shift;
	188	uint mask;
	189
	190	con = readl(&cru->cru_mode_con);
	191	shift = clk_shift[clk_id];
	192	mask = clk_mask[clk_id];
	193
194	switch ((con & mask) >> shift) {
195	case GPLL_MODE_SLOW:
196	return OSC_HZ;
197	case GPLL_MODE_NORM:
198
199	/* normal mode */
200	con = readl(&pll->con0);
201	postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
202	fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
203	con = readl(&pll->con1);
204	postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
205	refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
206	return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
207	default:
208	return 32768;
209	}
210	}
211
212	static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
213	int periph)
214	{
215	uint src_rate;
216	uint div, mux;
217	u32 con;
218
219	switch (periph) {
220	case HCLK_EMMC:
221	case SCLK_EMMC:
e4d0d612	222	case SCLK_EMMC_SAMPLE:
045029cb KY	223	con = readl(&cru->cru_clksel_con[11]);
	224	mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
	225	con = readl(&cru->cru_clksel_con[12]);
	226	div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
	227	break;
	228	case HCLK_SDMMC:
	229	case SCLK_SDMMC:
	230	con = readl(&cru->cru_clksel_con[11]);
	231	mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
	232	div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
	233	break;
	234	default:
	235	return -EINVAL;
	236	}
	237
	238	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
3a94d75d	239	return DIV_TO_RATE(src_rate, div) / 2;
045029cb KY	240	}
045029cb KY	241
5bb616c6 DW	242	static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
	243	{
	244	ulong ret;
	245
	246	/*
	247	* The gmac clock can be derived either from an external clock
	248	* or can be generated from internally by a divider from SCLK_MAC.
	249	*/
	250	if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
	251	/* An external clock will always generate the right rate... */
	252	ret = freq;
	253	} else {
	254	u32 con = readl(&cru->cru_clksel_con[5]);
	255	ulong pll_rate;
	256	u8 div;
	257
	258	if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
	259	pll_rate = GPLL_HZ;
	260	else
	261	/* CPLL is not set */
	262	return -EPERM;
	263
	264	div = DIV_ROUND_UP(pll_rate, freq) - 1;
	265	if (div <= 0x1f)
	266	rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
	267	div << CLK_MAC_DIV_SHIFT);
	268	else
	269	debug("Unsupported div for gmac:%d\n", div);
	270
	271	return DIV_TO_RATE(pll_rate, div);
	272	}
	273
	274	return ret;
	275	}
	276
045029cb KY	277	static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
	278	int periph, uint freq)
	279	{
	280	int src_clk_div;
	281	int mux;
	282
	283	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
	284
3a94d75d KY	285	/* mmc clock defaulg div 2 internal, need provide double in cru */
3a94d75d KY	286	src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
045029cb	287
217273cd	288	if (src_clk_div > 128) {
3a94d75d	289	src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
217273cd	290	assert(src_clk_div - 1 < 128);
045029cb KY	291	mux = EMMC_SEL_24M;
	292	} else {
	293	mux = EMMC_SEL_GPLL;
	294	}
	295
	296	switch (periph) {
	297	case HCLK_EMMC:
	298	case SCLK_EMMC:
e4d0d612	299	case SCLK_EMMC_SAMPLE:
045029cb KY	300	rk_clrsetreg(&cru->cru_clksel_con[11],
	301	EMMC_PLL_MASK,
	302	mux << EMMC_PLL_SHIFT);
	303	rk_clrsetreg(&cru->cru_clksel_con[12],
	304	EMMC_DIV_MASK,
	305	(src_clk_div - 1) << EMMC_DIV_SHIFT);
	306	break;
	307	case HCLK_SDMMC:
	308	case SCLK_SDMMC:
	309	rk_clrsetreg(&cru->cru_clksel_con[11],
	310	MMC0_PLL_MASK \| MMC0_DIV_MASK,
	311	mux << MMC0_PLL_SHIFT \|
	312	(src_clk_div - 1) << MMC0_DIV_SHIFT);
	313	break;
	314	default:
	315	return -EINVAL;
	316	}
	317
	318	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
	319	}
	320
	321	static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
	322	{
	323	struct pll_div dpll_cfg;
	324
	325	/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
	326	switch (set_rate) {
	327	case 400*MHz:
	328	dpll_cfg = (struct pll_div)
	329	{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
	330	break;
	331	case 600*MHz:
	332	dpll_cfg = (struct pll_div)
	333	{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
	334	break;
	335	case 800*MHz:
	336	dpll_cfg = (struct pll_div)
	337	{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
	338	break;
	339	}
	340
	341	/* pll enter slow-mode */
	342	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
	343	DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
	344	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
	345	/* PLL enter normal-mode */
	346	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
	347	DPLL_MODE_NORM << DPLL_MODE_SHIFT);
	348
	349	return set_rate;
	350	}
	351	static ulong rk322x_clk_get_rate(struct clk *clk)
	352	{
	353	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	354	ulong rate, gclk_rate;
	355
	356	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	357	switch (clk->id) {
	358	case 0 ... 63:
	359	rate = rkclk_pll_get_rate(priv->cru, clk->id);
	360	break;
	361	case HCLK_EMMC:
	362	case SCLK_EMMC:
	363	case HCLK_SDMMC:
364	case SCLK_SDMMC:
365	rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
366	break;
367	default:
368	return -ENOENT;
369	}
370
371	return rate;
372	}
373
374	static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
375	{
376	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
377	ulong new_rate, gclk_rate;
378
379	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
380	switch (clk->id) {
381	case HCLK_EMMC:
382	case SCLK_EMMC:
383	case HCLK_SDMMC:
384	case SCLK_SDMMC:
385	new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
386	clk->id, rate);
387	break;
388	case CLK_DDR:
389	new_rate = rk322x_ddr_set_clk(priv->cru, rate);
390	break;
5bb616c6 DW	391	case SCLK_MAC:
	392	new_rate = rk322x_mac_set_clk(priv->cru, rate);
	393	break;
	394	case PLL_GPLL:
	395	return 0;
045029cb KY	396	default:
	397	return -ENOENT;
	398	}
	399
	400	return new_rate;
	401	}
	402
5bb616c6 DW	403	static int rk322x_gmac_set_parent(struct clk clk, struct clk parent)
	404	{
	405	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	406	struct rk322x_cru *cru = priv->cru;
	407
	408	/*
	409	* If the requested parent is in the same clock-controller and the id
	410	* is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
	411	*/
	412	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
	413	debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
	414	rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
	415	return 0;
	416	}
	417
	418	/*
	419	* If the requested parent is in the same clock-controller and the id
	420	* is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
	421	*/
	422	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
	423	debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
	424	rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
	425	return 0;
	426	}
	427
	428	return -EINVAL;
	429	}
	430
	431	static int rk322x_gmac_extclk_set_parent(struct clk clk, struct clk parent)
	432	{
	433	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	434	const char *clock_output_name;
	435	struct rk322x_cru *cru = priv->cru;
	436	int ret;
	437
	438	ret = dev_read_string_index(parent->dev, "clock-output-names",
	439	parent->id, &clock_output_name);
	440	if (ret < 0)
	441	return -ENODATA;
	442
	443	if (!strcmp(clock_output_name, "ext_gmac")) {
	444	debug("%s: switching gmac extclk to ext_gmac\n", __func__);
	445	rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
	446	return 0;
	447	} else if (!strcmp(clock_output_name, "phy_50m_out")) {
	448	debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
	449	rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
	450	return 0;
	451	}
	452
	453	return -EINVAL;
	454	}
	455
	456	static int rk322x_clk_set_parent(struct clk clk, struct clk parent)
	457	{
	458	switch (clk->id) {
	459	case SCLK_MAC:
	460	return rk322x_gmac_set_parent(clk, parent);
	461	case SCLK_MAC_EXTCLK:
	462	return rk322x_gmac_extclk_set_parent(clk, parent);
	463	}
	464
	465	debug("%s: unsupported clk %ld\n", __func__, clk->id);
	466	return -ENOENT;
467	}
468
045029cb KY	469	static struct clk_ops rk322x_clk_ops = {
	470	.get_rate = rk322x_clk_get_rate,
	471	.set_rate = rk322x_clk_set_rate,
5bb616c6	472	.set_parent = rk322x_clk_set_parent,
045029cb KY	473	};
	474
	475	static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
	476	{
	477	struct rk322x_clk_priv *priv = dev_get_priv(dev);
	478
99b8553c	479	priv->cru = dev_read_addr_ptr(dev);
045029cb KY	480
	481	return 0;
	482	}
	483
	484	static int rk322x_clk_probe(struct udevice *dev)
	485	{
	486	struct rk322x_clk_priv *priv = dev_get_priv(dev);
	487
	488	rkclk_init(priv->cru);
	489
	490	return 0;
	491	}
	492
	493	static int rk322x_clk_bind(struct udevice *dev)
	494	{
	495	int ret;
f24e36da KY	496	struct udevice *sys_child;
f24e36da KY	497	struct sysreset_reg *priv;
045029cb KY	498
045029cb KY	499	/* The reset driver does not have a device node, so bind it here */
f24e36da KY	500	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
	501	&sys_child);
	502	if (ret) {
	503	debug("Warning: No sysreset driver: ret=%d\n", ret);
	504	} else {
	505	priv = malloc(sizeof(struct sysreset_reg));
	506	priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
	507	cru_glb_srst_fst_value);
	508	priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
	509	cru_glb_srst_snd_value);
	510	sys_child->priv = priv;
	511	}
045029cb	512
a5ada25e	513	#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
538f67c3 EZ	514	ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
	515	ret = rockchip_reset_bind(dev, ret, 9);
	516	if (ret)
	517	debug("Warning: software reset driver bind faile\n");
	518	#endif
	519
045029cb KY	520	return 0;
	521	}
	522
	523	static const struct udevice_id rk322x_clk_ids[] = {
	524	{ .compatible = "rockchip,rk3228-cru" },
	525	{ }
	526	};
	527
	528	U_BOOT_DRIVER(rockchip_rk322x_cru) = {
	529	.name = "clk_rk322x",
	530	.id = UCLASS_CLK,
	531	.of_match = rk322x_clk_ids,
	532	.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
	533	.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
	534	.ops = &rk322x_clk_ops,
	535	.bind = rk322x_clk_bind,
	536	.probe = rk322x_clk_probe,
	537	};