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99c15650 SG |
1 | /* |
2 | * (C) Copyright 2015 Google, Inc | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0 | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
ef4cf5ae | 8 | #include <bitfield.h> |
135aa950 | 9 | #include <clk-uclass.h> |
99c15650 | 10 | #include <dm.h> |
2d143bd6 | 11 | #include <dt-structs.h> |
99c15650 | 12 | #include <errno.h> |
2d143bd6 | 13 | #include <mapmem.h> |
99c15650 SG |
14 | #include <syscon.h> |
15 | #include <asm/io.h> | |
16 | #include <asm/arch/clock.h> | |
17 | #include <asm/arch/cru_rk3288.h> | |
18 | #include <asm/arch/grf_rk3288.h> | |
19 | #include <asm/arch/hardware.h> | |
898d6439 | 20 | #include <dt-bindings/clock/rk3288-cru.h> |
64b7faa7 | 21 | #include <dm/device-internal.h> |
99c15650 | 22 | #include <dm/lists.h> |
64b7faa7 | 23 | #include <dm/uclass-internal.h> |
abd0128e | 24 | #include <linux/log2.h> |
99c15650 SG |
25 | |
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
2d143bd6 SG |
28 | struct rk3288_clk_plat { |
29 | #if CONFIG_IS_ENABLED(OF_PLATDATA) | |
30 | struct dtd_rockchip_rk3288_cru dtd; | |
31 | #endif | |
32 | }; | |
33 | ||
99c15650 SG |
34 | struct pll_div { |
35 | u32 nr; | |
36 | u32 nf; | |
37 | u32 no; | |
38 | }; | |
39 | ||
40 | enum { | |
41 | VCO_MAX_HZ = 2200U * 1000000, | |
42 | VCO_MIN_HZ = 440 * 1000000, | |
43 | OUTPUT_MAX_HZ = 2200U * 1000000, | |
44 | OUTPUT_MIN_HZ = 27500000, | |
45 | FREF_MAX_HZ = 2200U * 1000000, | |
c3f03ffb | 46 | FREF_MIN_HZ = 269 * 1000, |
99c15650 SG |
47 | }; |
48 | ||
49 | enum { | |
50 | /* PLL CON0 */ | |
51 | PLL_OD_MASK = 0x0f, | |
52 | ||
53 | /* PLL CON1 */ | |
54 | PLL_NF_MASK = 0x1fff, | |
55 | ||
56 | /* PLL CON2 */ | |
57 | PLL_BWADJ_MASK = 0x0fff, | |
58 | ||
59 | /* PLL CON3 */ | |
60 | PLL_RESET_SHIFT = 5, | |
61 | ||
dae594f2 | 62 | /* CLKSEL0 */ |
dae594f2 | 63 | CORE_SEL_PLL_SHIFT = 15, |
b223c1ae | 64 | CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, |
dae594f2 | 65 | A17_DIV_SHIFT = 8, |
b223c1ae | 66 | A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, |
dae594f2 | 67 | MP_DIV_SHIFT = 4, |
b223c1ae | 68 | MP_DIV_MASK = 0xf << MP_DIV_SHIFT, |
dae594f2 | 69 | M0_DIV_SHIFT = 0, |
b223c1ae | 70 | M0_DIV_MASK = 0xf << M0_DIV_SHIFT, |
dae594f2 | 71 | |
99c15650 SG |
72 | /* CLKSEL1: pd bus clk pll sel: codec or general */ |
73 | PD_BUS_SEL_PLL_MASK = 15, | |
74 | PD_BUS_SEL_CPLL = 0, | |
75 | PD_BUS_SEL_GPLL, | |
76 | ||
77 | /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ | |
78 | PD_BUS_PCLK_DIV_SHIFT = 12, | |
b223c1ae | 79 | PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, |
99c15650 SG |
80 | |
81 | /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ | |
82 | PD_BUS_HCLK_DIV_SHIFT = 8, | |
b223c1ae | 83 | PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, |
99c15650 SG |
84 | |
85 | /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ | |
86 | PD_BUS_ACLK_DIV0_SHIFT = 3, | |
b223c1ae | 87 | PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, |
99c15650 | 88 | PD_BUS_ACLK_DIV1_SHIFT = 0, |
b223c1ae | 89 | PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, |
99c15650 SG |
90 | |
91 | /* | |
92 | * CLKSEL10 | |
93 | * peripheral bus pclk div: | |
94 | * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 | |
95 | */ | |
c87c129f | 96 | PERI_SEL_PLL_SHIFT = 15, |
b223c1ae | 97 | PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, |
c87c129f SG |
98 | PERI_SEL_CPLL = 0, |
99 | PERI_SEL_GPLL, | |
100 | ||
99c15650 | 101 | PERI_PCLK_DIV_SHIFT = 12, |
b223c1ae | 102 | PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, |
99c15650 SG |
103 | |
104 | /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ | |
105 | PERI_HCLK_DIV_SHIFT = 8, | |
b223c1ae | 106 | PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, |
99c15650 SG |
107 | |
108 | /* | |
109 | * peripheral bus aclk div: | |
110 | * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) | |
111 | */ | |
112 | PERI_ACLK_DIV_SHIFT = 0, | |
b223c1ae | 113 | PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, |
99c15650 | 114 | |
ef4cf5ae DW |
115 | /* |
116 | * CLKSEL24 | |
117 | * saradc_div_con: | |
118 | * clk_saradc=24MHz/(saradc_div_con+1) | |
119 | */ | |
120 | CLK_SARADC_DIV_CON_SHIFT = 8, | |
121 | CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), | |
122 | CLK_SARADC_DIV_CON_WIDTH = 8, | |
123 | ||
99c15650 SG |
124 | SOCSTS_DPLL_LOCK = 1 << 5, |
125 | SOCSTS_APLL_LOCK = 1 << 6, | |
126 | SOCSTS_CPLL_LOCK = 1 << 7, | |
127 | SOCSTS_GPLL_LOCK = 1 << 8, | |
128 | SOCSTS_NPLL_LOCK = 1 << 9, | |
129 | }; | |
130 | ||
99c15650 SG |
131 | #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) |
132 | ||
133 | #define PLL_DIVISORS(hz, _nr, _no) {\ | |
134 | .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ | |
135 | _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ | |
136 | (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ | |
137 | "divisors on line " __stringify(__LINE__)); | |
138 | ||
139 | /* Keep divisors as low as possible to reduce jitter and power usage */ | |
140 | static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); | |
141 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); | |
142 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); | |
143 | ||
144 | static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, | |
145 | const struct pll_div *div) | |
146 | { | |
147 | int pll_id = rk_pll_id(clk_id); | |
148 | struct rk3288_pll *pll = &cru->pll[pll_id]; | |
149 | /* All PLLs have same VCO and output frequency range restrictions. */ | |
150 | uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; | |
151 | uint output_hz = vco_hz / div->no; | |
152 | ||
c87c129f SG |
153 | debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", |
154 | (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); | |
99c15650 SG |
155 | assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && |
156 | output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && | |
157 | (div->no == 1 || !(div->no % 2))); | |
158 | ||
c87c129f | 159 | /* enter reset */ |
99c15650 SG |
160 | rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
161 | ||
b223c1ae | 162 | rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, |
99c15650 SG |
163 | ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); |
164 | rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); | |
165 | rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); | |
166 | ||
167 | udelay(10); | |
168 | ||
c87c129f | 169 | /* return from reset */ |
99c15650 SG |
170 | rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
99c15650 SG |
175 | static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, |
176 | unsigned int hz) | |
177 | { | |
178 | static const struct pll_div dpll_cfg[] = { | |
179 | {.nf = 25, .nr = 2, .no = 1}, | |
180 | {.nf = 400, .nr = 9, .no = 2}, | |
181 | {.nf = 500, .nr = 9, .no = 2}, | |
182 | {.nf = 100, .nr = 3, .no = 1}, | |
183 | }; | |
184 | int cfg; | |
185 | ||
99c15650 SG |
186 | switch (hz) { |
187 | case 300000000: | |
188 | cfg = 0; | |
189 | break; | |
190 | case 533000000: /* actually 533.3P MHz */ | |
191 | cfg = 1; | |
192 | break; | |
193 | case 666000000: /* actually 666.6P MHz */ | |
194 | cfg = 2; | |
195 | break; | |
196 | case 800000000: | |
197 | cfg = 3; | |
198 | break; | |
199 | default: | |
c87c129f | 200 | debug("Unsupported SDRAM frequency"); |
99c15650 SG |
201 | return -EINVAL; |
202 | } | |
203 | ||
204 | /* pll enter slow-mode */ | |
b223c1ae | 205 | rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, |
99c15650 SG |
206 | DPLL_MODE_SLOW << DPLL_MODE_SHIFT); |
207 | ||
208 | rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); | |
209 | ||
210 | /* wait for pll lock */ | |
211 | while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) | |
212 | udelay(1); | |
213 | ||
214 | /* PLL enter normal-mode */ | |
b223c1ae | 215 | rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, |
009741fb | 216 | DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); |
99c15650 SG |
217 | |
218 | return 0; | |
219 | } | |
220 | ||
830a6081 SG |
221 | #ifndef CONFIG_SPL_BUILD |
222 | #define VCO_MAX_KHZ 2200000 | |
223 | #define VCO_MIN_KHZ 440000 | |
224 | #define FREF_MAX_KHZ 2200000 | |
225 | #define FREF_MIN_KHZ 269 | |
226 | ||
227 | static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) | |
228 | { | |
229 | uint ref_khz = OSC_HZ / 1000, nr, nf = 0; | |
230 | uint fref_khz; | |
231 | uint diff_khz, best_diff_khz; | |
232 | const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4; | |
233 | uint vco_khz; | |
234 | uint no = 1; | |
235 | uint freq_khz = freq_hz / 1000; | |
236 | ||
237 | if (!freq_hz) { | |
238 | printf("%s: the frequency can not be 0 Hz\n", __func__); | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); | |
243 | if (ext_div) { | |
244 | *ext_div = DIV_ROUND_UP(no, max_no); | |
245 | no = DIV_ROUND_UP(no, *ext_div); | |
246 | } | |
247 | ||
248 | /* only even divisors (and 1) are supported */ | |
249 | if (no > 1) | |
250 | no = DIV_ROUND_UP(no, 2) * 2; | |
251 | ||
252 | vco_khz = freq_khz * no; | |
253 | if (ext_div) | |
254 | vco_khz *= *ext_div; | |
255 | ||
256 | if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { | |
257 | printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n", | |
258 | __func__, freq_hz); | |
259 | return -1; | |
260 | } | |
261 | ||
262 | div->no = no; | |
263 | ||
264 | best_diff_khz = vco_khz; | |
265 | for (nr = 1; nr < max_nr && best_diff_khz; nr++) { | |
266 | fref_khz = ref_khz / nr; | |
267 | if (fref_khz < FREF_MIN_KHZ) | |
268 | break; | |
269 | if (fref_khz > FREF_MAX_KHZ) | |
270 | continue; | |
271 | ||
272 | nf = vco_khz / fref_khz; | |
273 | if (nf >= max_nf) | |
274 | continue; | |
275 | diff_khz = vco_khz - nf * fref_khz; | |
276 | if (nf + 1 < max_nf && diff_khz > fref_khz / 2) { | |
277 | nf++; | |
278 | diff_khz = fref_khz - diff_khz; | |
279 | } | |
280 | ||
281 | if (diff_khz >= best_diff_khz) | |
282 | continue; | |
283 | ||
284 | best_diff_khz = diff_khz; | |
285 | div->nr = nr; | |
286 | div->nf = nf; | |
287 | } | |
288 | ||
289 | if (best_diff_khz > 4 * 1000) { | |
290 | printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n", | |
291 | __func__, freq_hz, best_diff_khz * 1000); | |
292 | return -EINVAL; | |
293 | } | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
0aefc0b0 SS |
298 | static int rockchip_mac_set_clk(struct rk3288_cru *cru, |
299 | int periph, uint freq) | |
300 | { | |
301 | /* Assuming mac_clk is fed by an external clock */ | |
302 | rk_clrsetreg(&cru->cru_clksel_con[21], | |
b223c1ae | 303 | RMII_EXTCLK_MASK, |
0aefc0b0 SS |
304 | RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
830a6081 SG |
309 | static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, |
310 | int periph, unsigned int rate_hz) | |
311 | { | |
312 | struct pll_div npll_config = {0}; | |
313 | u32 lcdc_div; | |
314 | int ret; | |
315 | ||
316 | ret = pll_para_config(rate_hz, &npll_config, &lcdc_div); | |
317 | if (ret) | |
318 | return ret; | |
319 | ||
b223c1ae | 320 | rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, |
830a6081 SG |
321 | NPLL_MODE_SLOW << NPLL_MODE_SHIFT); |
322 | rkclk_set_pll(cru, CLK_NEW, &npll_config); | |
323 | ||
324 | /* waiting for pll lock */ | |
325 | while (1) { | |
326 | if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK) | |
327 | break; | |
328 | udelay(1); | |
329 | } | |
330 | ||
b223c1ae | 331 | rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, |
830a6081 SG |
332 | NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); |
333 | ||
334 | /* vop dclk source clk: npll,dclk_div: 1 */ | |
335 | switch (periph) { | |
336 | case DCLK_VOP0: | |
337 | rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, | |
338 | (lcdc_div - 1) << 8 | 2 << 0); | |
339 | break; | |
340 | case DCLK_VOP1: | |
341 | rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, | |
342 | (lcdc_div - 1) << 8 | 2 << 6); | |
343 | break; | |
344 | } | |
345 | ||
346 | return 0; | |
347 | } | |
d3cb46aa | 348 | #endif /* CONFIG_SPL_BUILD */ |
830a6081 | 349 | |
99c15650 SG |
350 | static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) |
351 | { | |
352 | u32 aclk_div; | |
353 | u32 hclk_div; | |
354 | u32 pclk_div; | |
355 | ||
356 | /* pll enter slow-mode */ | |
357 | rk_clrsetreg(&cru->cru_mode_con, | |
b223c1ae | 358 | GPLL_MODE_MASK | CPLL_MODE_MASK, |
99c15650 SG |
359 | GPLL_MODE_SLOW << GPLL_MODE_SHIFT | |
360 | CPLL_MODE_SLOW << CPLL_MODE_SHIFT); | |
361 | ||
362 | /* init pll */ | |
363 | rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); | |
364 | rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); | |
365 | ||
366 | /* waiting for pll lock */ | |
367 | while ((readl(&grf->soc_status[1]) & | |
368 | (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != | |
369 | (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) | |
370 | udelay(1); | |
371 | ||
372 | /* | |
373 | * pd_bus clock pll source selection and | |
374 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. | |
375 | */ | |
376 | aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; | |
377 | assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); | |
378 | hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; | |
379 | assert((hclk_div + 1) * PD_BUS_HCLK_HZ == | |
380 | PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); | |
381 | ||
382 | pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; | |
383 | assert((pclk_div + 1) * PD_BUS_PCLK_HZ == | |
384 | PD_BUS_ACLK_HZ && pclk_div < 0x7); | |
385 | ||
386 | rk_clrsetreg(&cru->cru_clksel_con[1], | |
b223c1ae SG |
387 | PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | |
388 | PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, | |
99c15650 SG |
389 | pclk_div << PD_BUS_PCLK_DIV_SHIFT | |
390 | hclk_div << PD_BUS_HCLK_DIV_SHIFT | | |
391 | aclk_div << PD_BUS_ACLK_DIV0_SHIFT | | |
392 | 0 << 0); | |
393 | ||
394 | /* | |
395 | * peri clock pll source selection and | |
396 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. | |
397 | */ | |
398 | aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; | |
399 | assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); | |
400 | ||
abd0128e | 401 | hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); |
99c15650 SG |
402 | assert((1 << hclk_div) * PERI_HCLK_HZ == |
403 | PERI_ACLK_HZ && (hclk_div < 0x4)); | |
404 | ||
abd0128e | 405 | pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); |
99c15650 SG |
406 | assert((1 << pclk_div) * PERI_PCLK_HZ == |
407 | PERI_ACLK_HZ && (pclk_div < 0x4)); | |
408 | ||
409 | rk_clrsetreg(&cru->cru_clksel_con[10], | |
b223c1ae SG |
410 | PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | |
411 | PERI_ACLK_DIV_MASK, | |
c87c129f | 412 | PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | |
99c15650 SG |
413 | pclk_div << PERI_PCLK_DIV_SHIFT | |
414 | hclk_div << PERI_HCLK_DIV_SHIFT | | |
415 | aclk_div << PERI_ACLK_DIV_SHIFT); | |
416 | ||
417 | /* PLL enter normal-mode */ | |
418 | rk_clrsetreg(&cru->cru_mode_con, | |
b223c1ae | 419 | GPLL_MODE_MASK | CPLL_MODE_MASK, |
009741fb SG |
420 | GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | |
421 | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); | |
99c15650 | 422 | } |
99c15650 | 423 | |
b339b5db | 424 | void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) |
dae594f2 SG |
425 | { |
426 | /* pll enter slow-mode */ | |
b223c1ae | 427 | rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, |
dae594f2 SG |
428 | APLL_MODE_SLOW << APLL_MODE_SHIFT); |
429 | ||
430 | rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); | |
431 | ||
432 | /* waiting for pll lock */ | |
433 | while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) | |
434 | udelay(1); | |
435 | ||
436 | /* | |
437 | * core clock pll source selection and | |
438 | * set up dependent divisors for MPAXI/M0AXI and ARM clocks. | |
439 | * core clock select apll, apll clk = 1800MHz | |
440 | * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz | |
441 | */ | |
442 | rk_clrsetreg(&cru->cru_clksel_con[0], | |
b223c1ae SG |
443 | CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | |
444 | M0_DIV_MASK, | |
dae594f2 SG |
445 | 0 << A17_DIV_SHIFT | |
446 | 3 << MP_DIV_SHIFT | | |
447 | 1 << M0_DIV_SHIFT); | |
448 | ||
449 | /* | |
450 | * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. | |
451 | * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz | |
452 | */ | |
453 | rk_clrsetreg(&cru->cru_clksel_con[37], | |
b223c1ae SG |
454 | CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | |
455 | PCLK_CORE_DBG_DIV_MASK, | |
dae594f2 SG |
456 | 1 << CLK_L2RAM_DIV_SHIFT | |
457 | 3 << ATCLK_CORE_DIV_CON_SHIFT | | |
458 | 3 << PCLK_CORE_DBG_DIV_SHIFT); | |
459 | ||
460 | /* PLL enter normal-mode */ | |
b223c1ae | 461 | rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, |
dae594f2 SG |
462 | APLL_MODE_NORMAL << APLL_MODE_SHIFT); |
463 | } | |
464 | ||
99c15650 SG |
465 | /* Get pll rate by id */ |
466 | static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, | |
467 | enum rk_clk_id clk_id) | |
468 | { | |
469 | uint32_t nr, no, nf; | |
470 | uint32_t con; | |
471 | int pll_id = rk_pll_id(clk_id); | |
472 | struct rk3288_pll *pll = &cru->pll[pll_id]; | |
473 | static u8 clk_shift[CLK_COUNT] = { | |
009741fb SG |
474 | 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, |
475 | GPLL_MODE_SHIFT, NPLL_MODE_SHIFT | |
99c15650 SG |
476 | }; |
477 | uint shift; | |
478 | ||
479 | con = readl(&cru->cru_mode_con); | |
480 | shift = clk_shift[clk_id]; | |
b223c1ae | 481 | switch ((con >> shift) & CRU_MODE_MASK) { |
009741fb | 482 | case APLL_MODE_SLOW: |
99c15650 | 483 | return OSC_HZ; |
009741fb | 484 | case APLL_MODE_NORMAL: |
99c15650 SG |
485 | /* normal mode */ |
486 | con = readl(&pll->con0); | |
b223c1ae SG |
487 | no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; |
488 | nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; | |
99c15650 | 489 | con = readl(&pll->con1); |
b223c1ae | 490 | nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; |
99c15650 SG |
491 | |
492 | return (24 * nf / (nr * no)) * 1000000; | |
009741fb | 493 | case APLL_MODE_DEEP: |
99c15650 SG |
494 | default: |
495 | return 32768; | |
496 | } | |
497 | } | |
498 | ||
542635a0 | 499 | static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, |
898d6439 | 500 | int periph) |
99c15650 SG |
501 | { |
502 | uint src_rate; | |
503 | uint div, mux; | |
504 | u32 con; | |
505 | ||
506 | switch (periph) { | |
898d6439 | 507 | case HCLK_EMMC: |
45112271 | 508 | case SCLK_EMMC: |
99c15650 | 509 | con = readl(&cru->cru_clksel_con[12]); |
b223c1ae SG |
510 | mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; |
511 | div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; | |
99c15650 | 512 | break; |
898d6439 | 513 | case HCLK_SDMMC: |
45112271 | 514 | case SCLK_SDMMC: |
898d6439 | 515 | con = readl(&cru->cru_clksel_con[11]); |
b223c1ae SG |
516 | mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; |
517 | div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; | |
99c15650 | 518 | break; |
898d6439 | 519 | case HCLK_SDIO0: |
45112271 | 520 | case SCLK_SDIO0: |
99c15650 | 521 | con = readl(&cru->cru_clksel_con[12]); |
b223c1ae SG |
522 | mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; |
523 | div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; | |
99c15650 SG |
524 | break; |
525 | default: | |
526 | return -EINVAL; | |
527 | } | |
528 | ||
542635a0 | 529 | src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; |
99c15650 SG |
530 | return DIV_TO_RATE(src_rate, div); |
531 | } | |
532 | ||
542635a0 | 533 | static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, |
898d6439 | 534 | int periph, uint freq) |
99c15650 SG |
535 | { |
536 | int src_clk_div; | |
537 | int mux; | |
538 | ||
542635a0 | 539 | debug("%s: gclk_rate=%u\n", __func__, gclk_rate); |
3a94d75d KY |
540 | /* mmc clock default div 2 internal, need provide double in cru */ |
541 | src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); | |
99c15650 SG |
542 | |
543 | if (src_clk_div > 0x3f) { | |
3a94d75d | 544 | src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); |
217273cd | 545 | assert(src_clk_div < 0x40); |
99c15650 SG |
546 | mux = EMMC_PLL_SELECT_24MHZ; |
547 | assert((int)EMMC_PLL_SELECT_24MHZ == | |
548 | (int)MMC0_PLL_SELECT_24MHZ); | |
549 | } else { | |
550 | mux = EMMC_PLL_SELECT_GENERAL; | |
551 | assert((int)EMMC_PLL_SELECT_GENERAL == | |
552 | (int)MMC0_PLL_SELECT_GENERAL); | |
553 | } | |
554 | switch (periph) { | |
898d6439 | 555 | case HCLK_EMMC: |
45112271 | 556 | case SCLK_EMMC: |
99c15650 | 557 | rk_clrsetreg(&cru->cru_clksel_con[12], |
b223c1ae | 558 | EMMC_PLL_MASK | EMMC_DIV_MASK, |
99c15650 SG |
559 | mux << EMMC_PLL_SHIFT | |
560 | (src_clk_div - 1) << EMMC_DIV_SHIFT); | |
561 | break; | |
898d6439 | 562 | case HCLK_SDMMC: |
45112271 | 563 | case SCLK_SDMMC: |
99c15650 | 564 | rk_clrsetreg(&cru->cru_clksel_con[11], |
b223c1ae | 565 | MMC0_PLL_MASK | MMC0_DIV_MASK, |
99c15650 SG |
566 | mux << MMC0_PLL_SHIFT | |
567 | (src_clk_div - 1) << MMC0_DIV_SHIFT); | |
568 | break; | |
898d6439 | 569 | case HCLK_SDIO0: |
45112271 | 570 | case SCLK_SDIO0: |
99c15650 | 571 | rk_clrsetreg(&cru->cru_clksel_con[12], |
b223c1ae | 572 | SDIO0_PLL_MASK | SDIO0_DIV_MASK, |
99c15650 SG |
573 | mux << SDIO0_PLL_SHIFT | |
574 | (src_clk_div - 1) << SDIO0_DIV_SHIFT); | |
575 | break; | |
576 | default: | |
577 | return -EINVAL; | |
578 | } | |
579 | ||
542635a0 | 580 | return rockchip_mmc_get_clk(cru, gclk_rate, periph); |
99c15650 SG |
581 | } |
582 | ||
542635a0 | 583 | static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, |
898d6439 | 584 | int periph) |
99c15650 SG |
585 | { |
586 | uint div, mux; | |
587 | u32 con; | |
588 | ||
589 | switch (periph) { | |
898d6439 | 590 | case SCLK_SPI0: |
99c15650 | 591 | con = readl(&cru->cru_clksel_con[25]); |
b223c1ae SG |
592 | mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; |
593 | div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; | |
99c15650 | 594 | break; |
898d6439 | 595 | case SCLK_SPI1: |
99c15650 | 596 | con = readl(&cru->cru_clksel_con[25]); |
b223c1ae SG |
597 | mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; |
598 | div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; | |
99c15650 | 599 | break; |
898d6439 | 600 | case SCLK_SPI2: |
99c15650 | 601 | con = readl(&cru->cru_clksel_con[39]); |
b223c1ae SG |
602 | mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; |
603 | div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; | |
99c15650 SG |
604 | break; |
605 | default: | |
606 | return -EINVAL; | |
607 | } | |
608 | assert(mux == SPI0_PLL_SELECT_GENERAL); | |
609 | ||
542635a0 | 610 | return DIV_TO_RATE(gclk_rate, div); |
99c15650 SG |
611 | } |
612 | ||
542635a0 | 613 | static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, |
898d6439 | 614 | int periph, uint freq) |
99c15650 SG |
615 | { |
616 | int src_clk_div; | |
617 | ||
542635a0 | 618 | debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); |
217273cd KY |
619 | src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; |
620 | assert(src_clk_div < 128); | |
99c15650 | 621 | switch (periph) { |
898d6439 | 622 | case SCLK_SPI0: |
99c15650 | 623 | rk_clrsetreg(&cru->cru_clksel_con[25], |
b223c1ae | 624 | SPI0_PLL_MASK | SPI0_DIV_MASK, |
99c15650 SG |
625 | SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | |
626 | src_clk_div << SPI0_DIV_SHIFT); | |
627 | break; | |
898d6439 | 628 | case SCLK_SPI1: |
99c15650 | 629 | rk_clrsetreg(&cru->cru_clksel_con[25], |
b223c1ae | 630 | SPI1_PLL_MASK | SPI1_DIV_MASK, |
99c15650 SG |
631 | SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | |
632 | src_clk_div << SPI1_DIV_SHIFT); | |
633 | break; | |
898d6439 | 634 | case SCLK_SPI2: |
99c15650 | 635 | rk_clrsetreg(&cru->cru_clksel_con[39], |
b223c1ae | 636 | SPI2_PLL_MASK | SPI2_DIV_MASK, |
99c15650 SG |
637 | SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | |
638 | src_clk_div << SPI2_DIV_SHIFT); | |
639 | break; | |
640 | default: | |
641 | return -EINVAL; | |
642 | } | |
643 | ||
542635a0 | 644 | return rockchip_spi_get_clk(cru, gclk_rate, periph); |
99c15650 SG |
645 | } |
646 | ||
ef4cf5ae DW |
647 | static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) |
648 | { | |
649 | u32 div, val; | |
650 | ||
651 | val = readl(&cru->cru_clksel_con[24]); | |
652 | div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, | |
653 | CLK_SARADC_DIV_CON_WIDTH); | |
654 | ||
655 | return DIV_TO_RATE(OSC_HZ, div); | |
656 | } | |
657 | ||
658 | static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) | |
659 | { | |
660 | int src_clk_div; | |
661 | ||
662 | src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; | |
663 | assert(src_clk_div < 128); | |
664 | ||
665 | rk_clrsetreg(&cru->cru_clksel_con[24], | |
666 | CLK_SARADC_DIV_CON_MASK, | |
667 | src_clk_div << CLK_SARADC_DIV_CON_SHIFT); | |
668 | ||
669 | return rockchip_saradc_get_clk(cru); | |
670 | } | |
671 | ||
135aa950 | 672 | static ulong rk3288_clk_get_rate(struct clk *clk) |
4f43673e | 673 | { |
135aa950 | 674 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); |
4f43673e | 675 | ulong new_rate, gclk_rate; |
4f43673e | 676 | |
135aa950 SW |
677 | gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); |
678 | switch (clk->id) { | |
679 | case 0 ... 63: | |
680 | new_rate = rkclk_pll_get_rate(priv->cru, clk->id); | |
681 | break; | |
4f43673e | 682 | case HCLK_EMMC: |
342999f9 | 683 | case HCLK_SDMMC: |
4f43673e | 684 | case HCLK_SDIO0: |
45112271 XZ |
685 | case SCLK_EMMC: |
686 | case SCLK_SDMMC: | |
687 | case SCLK_SDIO0: | |
135aa950 | 688 | new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); |
4f43673e SG |
689 | break; |
690 | case SCLK_SPI0: | |
691 | case SCLK_SPI1: | |
692 | case SCLK_SPI2: | |
135aa950 | 693 | new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); |
4f43673e SG |
694 | break; |
695 | case PCLK_I2C0: | |
696 | case PCLK_I2C1: | |
697 | case PCLK_I2C2: | |
698 | case PCLK_I2C3: | |
699 | case PCLK_I2C4: | |
700 | case PCLK_I2C5: | |
701 | return gclk_rate; | |
4f0b8efa KY |
702 | case PCLK_PWM: |
703 | return PD_BUS_PCLK_HZ; | |
ef4cf5ae DW |
704 | case SCLK_SARADC: |
705 | new_rate = rockchip_saradc_get_clk(priv->cru); | |
706 | break; | |
4f43673e SG |
707 | default: |
708 | return -ENOENT; | |
709 | } | |
710 | ||
711 | return new_rate; | |
712 | } | |
713 | ||
135aa950 | 714 | static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) |
99c15650 | 715 | { |
135aa950 | 716 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); |
830a6081 | 717 | struct rk3288_cru *cru = priv->cru; |
898d6439 | 718 | ulong new_rate, gclk_rate; |
898d6439 | 719 | |
135aa950 SW |
720 | gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); |
721 | switch (clk->id) { | |
3a8a42d9 SG |
722 | case PLL_APLL: |
723 | /* We only support a fixed rate here */ | |
724 | if (rate != 1800000000) | |
725 | return -EINVAL; | |
726 | rk3288_clk_configure_cpu(priv->cru, priv->grf); | |
727 | new_rate = rate; | |
728 | break; | |
135aa950 SW |
729 | case CLK_DDR: |
730 | new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); | |
731 | break; | |
898d6439 SG |
732 | case HCLK_EMMC: |
733 | case HCLK_SDMMC: | |
734 | case HCLK_SDIO0: | |
45112271 XZ |
735 | case SCLK_EMMC: |
736 | case SCLK_SDMMC: | |
737 | case SCLK_SDIO0: | |
135aa950 | 738 | new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); |
99c15650 | 739 | break; |
898d6439 SG |
740 | case SCLK_SPI0: |
741 | case SCLK_SPI1: | |
742 | case SCLK_SPI2: | |
135aa950 | 743 | new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); |
99c15650 | 744 | break; |
830a6081 | 745 | #ifndef CONFIG_SPL_BUILD |
0aefc0b0 | 746 | case SCLK_MAC: |
135aa950 | 747 | new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate); |
0aefc0b0 | 748 | break; |
830a6081 SG |
749 | case DCLK_VOP0: |
750 | case DCLK_VOP1: | |
135aa950 | 751 | new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); |
830a6081 SG |
752 | break; |
753 | case SCLK_EDP_24M: | |
754 | /* clk_edp_24M source: 24M */ | |
755 | rk_setreg(&cru->cru_clksel_con[28], 1 << 15); | |
756 | ||
757 | /* rst edp */ | |
758 | rk_setreg(&cru->cru_clksel_con[6], 1 << 15); | |
759 | udelay(1); | |
760 | rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); | |
761 | new_rate = rate; | |
762 | break; | |
763 | case ACLK_VOP0: | |
764 | case ACLK_VOP1: { | |
765 | u32 div; | |
766 | ||
767 | /* vop aclk source clk: cpll */ | |
768 | div = CPLL_HZ / rate; | |
769 | assert((div - 1 < 64) && (div * rate == CPLL_HZ)); | |
770 | ||
135aa950 | 771 | switch (clk->id) { |
830a6081 SG |
772 | case ACLK_VOP0: |
773 | rk_clrsetreg(&cru->cru_clksel_con[31], | |
774 | 3 << 6 | 0x1f << 0, | |
775 | 0 << 6 | (div - 1) << 0); | |
776 | break; | |
777 | case ACLK_VOP1: | |
778 | rk_clrsetreg(&cru->cru_clksel_con[31], | |
779 | 3 << 14 | 0x1f << 8, | |
780 | 0 << 14 | (div - 1) << 8); | |
781 | break; | |
782 | } | |
783 | new_rate = rate; | |
784 | break; | |
785 | } | |
786 | case PCLK_HDMI_CTRL: | |
787 | /* enable pclk hdmi ctrl */ | |
788 | rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); | |
789 | ||
790 | /* software reset hdmi */ | |
791 | rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); | |
792 | udelay(1); | |
793 | rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); | |
794 | new_rate = rate; | |
795 | break; | |
796 | #endif | |
ef4cf5ae DW |
797 | case SCLK_SARADC: |
798 | new_rate = rockchip_saradc_set_clk(priv->cru, rate); | |
799 | break; | |
99c15650 SG |
800 | default: |
801 | return -ENOENT; | |
802 | } | |
803 | ||
804 | return new_rate; | |
805 | } | |
806 | ||
807 | static struct clk_ops rk3288_clk_ops = { | |
808 | .get_rate = rk3288_clk_get_rate, | |
809 | .set_rate = rk3288_clk_set_rate, | |
99c15650 SG |
810 | }; |
811 | ||
08fd82cf | 812 | static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) |
99c15650 | 813 | { |
2d143bd6 | 814 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
99c15650 SG |
815 | struct rk3288_clk_priv *priv = dev_get_priv(dev); |
816 | ||
a821c4af | 817 | priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev); |
2d143bd6 | 818 | #endif |
08fd82cf SG |
819 | |
820 | return 0; | |
821 | } | |
822 | ||
823 | static int rk3288_clk_probe(struct udevice *dev) | |
824 | { | |
825 | struct rk3288_clk_priv *priv = dev_get_priv(dev); | |
d3cb46aa | 826 | bool init_clocks = false; |
08fd82cf | 827 | |
99c15650 | 828 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
08fd82cf SG |
829 | if (IS_ERR(priv->grf)) |
830 | return PTR_ERR(priv->grf); | |
99c15650 | 831 | #ifdef CONFIG_SPL_BUILD |
2d143bd6 SG |
832 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
833 | struct rk3288_clk_plat *plat = dev_get_platdata(dev); | |
834 | ||
835 | priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); | |
836 | #endif | |
d3cb46aa | 837 | init_clocks = true; |
99c15650 | 838 | #endif |
d3cb46aa SG |
839 | if (!(gd->flags & GD_FLG_RELOC)) { |
840 | u32 reg; | |
841 | ||
842 | /* | |
843 | * Init clocks in U-Boot proper if the NPLL is runnning. This | |
844 | * indicates that a previous boot loader set up the clocks, so | |
845 | * we need to redo it. U-Boot's SPL does not set this clock. | |
846 | */ | |
847 | reg = readl(&priv->cru->cru_mode_con); | |
848 | if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == | |
849 | NPLL_MODE_NORMAL) | |
850 | init_clocks = true; | |
851 | } | |
852 | ||
853 | if (init_clocks) | |
854 | rkclk_init(priv->cru, priv->grf); | |
99c15650 SG |
855 | |
856 | return 0; | |
857 | } | |
858 | ||
99c15650 SG |
859 | static int rk3288_clk_bind(struct udevice *dev) |
860 | { | |
135aa950 | 861 | int ret; |
f24e36da KY |
862 | struct udevice *sys_child; |
863 | struct sysreset_reg *priv; | |
99c15650 SG |
864 | |
865 | /* The reset driver does not have a device node, so bind it here */ | |
f24e36da KY |
866 | ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", |
867 | &sys_child); | |
868 | if (ret) { | |
869 | debug("Warning: No sysreset driver: ret=%d\n", ret); | |
870 | } else { | |
871 | priv = malloc(sizeof(struct sysreset_reg)); | |
872 | priv->glb_srst_fst_value = offsetof(struct rk3288_cru, | |
873 | cru_glb_srst_fst_value); | |
874 | priv->glb_srst_snd_value = offsetof(struct rk3288_cru, | |
875 | cru_glb_srst_snd_value); | |
876 | sys_child->priv = priv; | |
877 | } | |
99c15650 | 878 | |
538f67c3 EZ |
879 | #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) |
880 | ret = offsetof(struct rk3288_cru, cru_softrst_con[0]); | |
881 | ret = rockchip_reset_bind(dev, ret, 12); | |
882 | if (ret) | |
883 | debug("Warning: software reset driver bind faile\n"); | |
884 | #endif | |
885 | ||
99c15650 SG |
886 | return 0; |
887 | } | |
888 | ||
889 | static const struct udevice_id rk3288_clk_ids[] = { | |
890 | { .compatible = "rockchip,rk3288-cru" }, | |
891 | { } | |
892 | }; | |
893 | ||
2d143bd6 SG |
894 | U_BOOT_DRIVER(rockchip_rk3288_cru) = { |
895 | .name = "rockchip_rk3288_cru", | |
99c15650 SG |
896 | .id = UCLASS_CLK, |
897 | .of_match = rk3288_clk_ids, | |
898 | .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), | |
2d143bd6 | 899 | .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), |
99c15650 SG |
900 | .ops = &rk3288_clk_ops, |
901 | .bind = rk3288_clk_bind, | |
08fd82cf | 902 | .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata, |
99c15650 SG |
903 | .probe = rk3288_clk_probe, |
904 | }; |