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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
99c15650 SG |
2 | /* |
3 | * (C) Copyright 2015 Google, Inc | |
99c15650 SG |
4 | */ |
5 | ||
6 | #include <common.h> | |
ef4cf5ae | 7 | #include <bitfield.h> |
135aa950 | 8 | #include <clk-uclass.h> |
3dbfe5ae | 9 | #include <div64.h> |
99c15650 | 10 | #include <dm.h> |
2d143bd6 | 11 | #include <dt-structs.h> |
99c15650 | 12 | #include <errno.h> |
2d143bd6 | 13 | #include <mapmem.h> |
99c15650 SG |
14 | #include <syscon.h> |
15 | #include <asm/io.h> | |
15f09a1a | 16 | #include <asm/arch-rockchip/clock.h> |
b52a199e | 17 | #include <asm/arch-rockchip/cru.h> |
15f09a1a KY |
18 | #include <asm/arch-rockchip/grf_rk3288.h> |
19 | #include <asm/arch-rockchip/hardware.h> | |
898d6439 | 20 | #include <dt-bindings/clock/rk3288-cru.h> |
64b7faa7 | 21 | #include <dm/device-internal.h> |
99c15650 | 22 | #include <dm/lists.h> |
64b7faa7 | 23 | #include <dm/uclass-internal.h> |
61b29b82 | 24 | #include <linux/err.h> |
abd0128e | 25 | #include <linux/log2.h> |
99c15650 SG |
26 | |
27 | DECLARE_GLOBAL_DATA_PTR; | |
28 | ||
2d143bd6 SG |
29 | struct rk3288_clk_plat { |
30 | #if CONFIG_IS_ENABLED(OF_PLATDATA) | |
31 | struct dtd_rockchip_rk3288_cru dtd; | |
32 | #endif | |
33 | }; | |
34 | ||
99c15650 SG |
35 | struct pll_div { |
36 | u32 nr; | |
37 | u32 nf; | |
38 | u32 no; | |
39 | }; | |
40 | ||
41 | enum { | |
42 | VCO_MAX_HZ = 2200U * 1000000, | |
43 | VCO_MIN_HZ = 440 * 1000000, | |
44 | OUTPUT_MAX_HZ = 2200U * 1000000, | |
45 | OUTPUT_MIN_HZ = 27500000, | |
46 | FREF_MAX_HZ = 2200U * 1000000, | |
c3f03ffb | 47 | FREF_MIN_HZ = 269 * 1000, |
99c15650 SG |
48 | }; |
49 | ||
50 | enum { | |
51 | /* PLL CON0 */ | |
52 | PLL_OD_MASK = 0x0f, | |
53 | ||
54 | /* PLL CON1 */ | |
55 | PLL_NF_MASK = 0x1fff, | |
56 | ||
57 | /* PLL CON2 */ | |
58 | PLL_BWADJ_MASK = 0x0fff, | |
59 | ||
60 | /* PLL CON3 */ | |
61 | PLL_RESET_SHIFT = 5, | |
62 | ||
dae594f2 | 63 | /* CLKSEL0 */ |
dae594f2 | 64 | CORE_SEL_PLL_SHIFT = 15, |
b223c1ae | 65 | CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, |
dae594f2 | 66 | A17_DIV_SHIFT = 8, |
b223c1ae | 67 | A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, |
dae594f2 | 68 | MP_DIV_SHIFT = 4, |
b223c1ae | 69 | MP_DIV_MASK = 0xf << MP_DIV_SHIFT, |
dae594f2 | 70 | M0_DIV_SHIFT = 0, |
b223c1ae | 71 | M0_DIV_MASK = 0xf << M0_DIV_SHIFT, |
dae594f2 | 72 | |
99c15650 SG |
73 | /* CLKSEL1: pd bus clk pll sel: codec or general */ |
74 | PD_BUS_SEL_PLL_MASK = 15, | |
75 | PD_BUS_SEL_CPLL = 0, | |
76 | PD_BUS_SEL_GPLL, | |
77 | ||
78 | /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ | |
79 | PD_BUS_PCLK_DIV_SHIFT = 12, | |
b223c1ae | 80 | PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, |
99c15650 SG |
81 | |
82 | /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ | |
83 | PD_BUS_HCLK_DIV_SHIFT = 8, | |
b223c1ae | 84 | PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, |
99c15650 SG |
85 | |
86 | /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ | |
87 | PD_BUS_ACLK_DIV0_SHIFT = 3, | |
b223c1ae | 88 | PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, |
99c15650 | 89 | PD_BUS_ACLK_DIV1_SHIFT = 0, |
b223c1ae | 90 | PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, |
99c15650 SG |
91 | |
92 | /* | |
93 | * CLKSEL10 | |
94 | * peripheral bus pclk div: | |
95 | * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 | |
96 | */ | |
c87c129f | 97 | PERI_SEL_PLL_SHIFT = 15, |
b223c1ae | 98 | PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, |
c87c129f SG |
99 | PERI_SEL_CPLL = 0, |
100 | PERI_SEL_GPLL, | |
101 | ||
99c15650 | 102 | PERI_PCLK_DIV_SHIFT = 12, |
b223c1ae | 103 | PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, |
99c15650 SG |
104 | |
105 | /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ | |
106 | PERI_HCLK_DIV_SHIFT = 8, | |
b223c1ae | 107 | PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, |
99c15650 SG |
108 | |
109 | /* | |
110 | * peripheral bus aclk div: | |
111 | * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) | |
112 | */ | |
113 | PERI_ACLK_DIV_SHIFT = 0, | |
b223c1ae | 114 | PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, |
99c15650 | 115 | |
ef4cf5ae DW |
116 | /* |
117 | * CLKSEL24 | |
118 | * saradc_div_con: | |
119 | * clk_saradc=24MHz/(saradc_div_con+1) | |
120 | */ | |
121 | CLK_SARADC_DIV_CON_SHIFT = 8, | |
122 | CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), | |
123 | CLK_SARADC_DIV_CON_WIDTH = 8, | |
124 | ||
99c15650 SG |
125 | SOCSTS_DPLL_LOCK = 1 << 5, |
126 | SOCSTS_APLL_LOCK = 1 << 6, | |
127 | SOCSTS_CPLL_LOCK = 1 << 7, | |
128 | SOCSTS_GPLL_LOCK = 1 << 8, | |
129 | SOCSTS_NPLL_LOCK = 1 << 9, | |
130 | }; | |
131 | ||
99c15650 SG |
132 | #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) |
133 | ||
134 | #define PLL_DIVISORS(hz, _nr, _no) {\ | |
135 | .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ | |
136 | _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ | |
137 | (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ | |
138 | "divisors on line " __stringify(__LINE__)); | |
139 | ||
140 | /* Keep divisors as low as possible to reduce jitter and power usage */ | |
141 | static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); | |
142 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); | |
143 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); | |
144 | ||
b52a199e | 145 | static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id, |
99c15650 SG |
146 | const struct pll_div *div) |
147 | { | |
148 | int pll_id = rk_pll_id(clk_id); | |
149 | struct rk3288_pll *pll = &cru->pll[pll_id]; | |
150 | /* All PLLs have same VCO and output frequency range restrictions. */ | |
151 | uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; | |
152 | uint output_hz = vco_hz / div->no; | |
153 | ||
c87c129f SG |
154 | debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", |
155 | (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); | |
99c15650 SG |
156 | assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && |
157 | output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && | |
158 | (div->no == 1 || !(div->no % 2))); | |
159 | ||
c87c129f | 160 | /* enter reset */ |
99c15650 SG |
161 | rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
162 | ||
b223c1ae | 163 | rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, |
99c15650 SG |
164 | ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); |
165 | rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); | |
166 | rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); | |
167 | ||
168 | udelay(10); | |
169 | ||
c87c129f | 170 | /* return from reset */ |
99c15650 SG |
171 | rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
b52a199e | 176 | static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf, |
99c15650 SG |
177 | unsigned int hz) |
178 | { | |
179 | static const struct pll_div dpll_cfg[] = { | |
180 | {.nf = 25, .nr = 2, .no = 1}, | |
181 | {.nf = 400, .nr = 9, .no = 2}, | |
182 | {.nf = 500, .nr = 9, .no = 2}, | |
183 | {.nf = 100, .nr = 3, .no = 1}, | |
184 | }; | |
185 | int cfg; | |
186 | ||
99c15650 SG |
187 | switch (hz) { |
188 | case 300000000: | |
189 | cfg = 0; | |
190 | break; | |
191 | case 533000000: /* actually 533.3P MHz */ | |
192 | cfg = 1; | |
193 | break; | |
194 | case 666000000: /* actually 666.6P MHz */ | |
195 | cfg = 2; | |
196 | break; | |
197 | case 800000000: | |
198 | cfg = 3; | |
199 | break; | |
200 | default: | |
c87c129f | 201 | debug("Unsupported SDRAM frequency"); |
99c15650 SG |
202 | return -EINVAL; |
203 | } | |
204 | ||
205 | /* pll enter slow-mode */ | |
b223c1ae | 206 | rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, |
99c15650 SG |
207 | DPLL_MODE_SLOW << DPLL_MODE_SHIFT); |
208 | ||
209 | rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); | |
210 | ||
211 | /* wait for pll lock */ | |
212 | while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) | |
213 | udelay(1); | |
214 | ||
215 | /* PLL enter normal-mode */ | |
b223c1ae | 216 | rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, |
009741fb | 217 | DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); |
99c15650 SG |
218 | |
219 | return 0; | |
220 | } | |
221 | ||
830a6081 SG |
222 | #ifndef CONFIG_SPL_BUILD |
223 | #define VCO_MAX_KHZ 2200000 | |
224 | #define VCO_MIN_KHZ 440000 | |
225 | #define FREF_MAX_KHZ 2200000 | |
226 | #define FREF_MIN_KHZ 269 | |
227 | ||
228 | static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) | |
229 | { | |
230 | uint ref_khz = OSC_HZ / 1000, nr, nf = 0; | |
231 | uint fref_khz; | |
232 | uint diff_khz, best_diff_khz; | |
233 | const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4; | |
234 | uint vco_khz; | |
235 | uint no = 1; | |
236 | uint freq_khz = freq_hz / 1000; | |
237 | ||
238 | if (!freq_hz) { | |
239 | printf("%s: the frequency can not be 0 Hz\n", __func__); | |
240 | return -EINVAL; | |
241 | } | |
242 | ||
243 | no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); | |
244 | if (ext_div) { | |
245 | *ext_div = DIV_ROUND_UP(no, max_no); | |
246 | no = DIV_ROUND_UP(no, *ext_div); | |
247 | } | |
248 | ||
249 | /* only even divisors (and 1) are supported */ | |
250 | if (no > 1) | |
251 | no = DIV_ROUND_UP(no, 2) * 2; | |
252 | ||
253 | vco_khz = freq_khz * no; | |
254 | if (ext_div) | |
255 | vco_khz *= *ext_div; | |
256 | ||
257 | if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { | |
258 | printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n", | |
259 | __func__, freq_hz); | |
260 | return -1; | |
261 | } | |
262 | ||
263 | div->no = no; | |
264 | ||
265 | best_diff_khz = vco_khz; | |
266 | for (nr = 1; nr < max_nr && best_diff_khz; nr++) { | |
267 | fref_khz = ref_khz / nr; | |
268 | if (fref_khz < FREF_MIN_KHZ) | |
269 | break; | |
270 | if (fref_khz > FREF_MAX_KHZ) | |
271 | continue; | |
272 | ||
273 | nf = vco_khz / fref_khz; | |
274 | if (nf >= max_nf) | |
275 | continue; | |
276 | diff_khz = vco_khz - nf * fref_khz; | |
277 | if (nf + 1 < max_nf && diff_khz > fref_khz / 2) { | |
278 | nf++; | |
279 | diff_khz = fref_khz - diff_khz; | |
280 | } | |
281 | ||
282 | if (diff_khz >= best_diff_khz) | |
283 | continue; | |
284 | ||
285 | best_diff_khz = diff_khz; | |
286 | div->nr = nr; | |
287 | div->nf = nf; | |
288 | } | |
289 | ||
290 | if (best_diff_khz > 4 * 1000) { | |
291 | printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n", | |
292 | __func__, freq_hz, best_diff_khz * 1000); | |
293 | return -EINVAL; | |
294 | } | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
b52a199e | 299 | static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq) |
0aefc0b0 | 300 | { |
01c60eaf | 301 | ulong ret; |
0aefc0b0 | 302 | |
01c60eaf DW |
303 | /* |
304 | * The gmac clock can be derived either from an external clock | |
305 | * or can be generated from internally by a divider from SCLK_MAC. | |
306 | */ | |
307 | if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { | |
308 | /* An external clock will always generate the right rate... */ | |
309 | ret = freq; | |
310 | } else { | |
311 | u32 con = readl(&cru->cru_clksel_con[21]); | |
312 | ulong pll_rate; | |
313 | u8 div; | |
314 | ||
315 | if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == | |
316 | EMAC_PLL_SELECT_GENERAL) | |
317 | pll_rate = GPLL_HZ; | |
318 | else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == | |
319 | EMAC_PLL_SELECT_CODEC) | |
320 | pll_rate = CPLL_HZ; | |
321 | else | |
322 | pll_rate = NPLL_HZ; | |
323 | ||
324 | div = DIV_ROUND_UP(pll_rate, freq) - 1; | |
325 | if (div <= 0x1f) | |
326 | rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, | |
327 | div << MAC_DIV_CON_SHIFT); | |
328 | else | |
329 | debug("Unsupported div for gmac:%d\n", div); | |
330 | ||
331 | return DIV_TO_RATE(pll_rate, div); | |
332 | } | |
333 | ||
334 | return ret; | |
0aefc0b0 SS |
335 | } |
336 | ||
b52a199e | 337 | static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf, |
830a6081 SG |
338 | int periph, unsigned int rate_hz) |
339 | { | |
340 | struct pll_div npll_config = {0}; | |
341 | u32 lcdc_div; | |
342 | int ret; | |
343 | ||
344 | ret = pll_para_config(rate_hz, &npll_config, &lcdc_div); | |
345 | if (ret) | |
346 | return ret; | |
347 | ||
b223c1ae | 348 | rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, |
830a6081 SG |
349 | NPLL_MODE_SLOW << NPLL_MODE_SHIFT); |
350 | rkclk_set_pll(cru, CLK_NEW, &npll_config); | |
351 | ||
352 | /* waiting for pll lock */ | |
353 | while (1) { | |
354 | if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK) | |
355 | break; | |
356 | udelay(1); | |
357 | } | |
358 | ||
b223c1ae | 359 | rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, |
830a6081 SG |
360 | NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); |
361 | ||
362 | /* vop dclk source clk: npll,dclk_div: 1 */ | |
363 | switch (periph) { | |
364 | case DCLK_VOP0: | |
365 | rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, | |
366 | (lcdc_div - 1) << 8 | 2 << 0); | |
367 | break; | |
368 | case DCLK_VOP1: | |
369 | rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, | |
370 | (lcdc_div - 1) << 8 | 2 << 6); | |
371 | break; | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
3dbfe5ae SG |
376 | |
377 | static u32 rockchip_clk_gcd(u32 a, u32 b) | |
378 | { | |
379 | while (b != 0) { | |
380 | int r = b; | |
381 | ||
382 | b = a % b; | |
383 | a = r; | |
384 | } | |
385 | return a; | |
386 | } | |
387 | ||
b52a199e | 388 | static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate) |
3dbfe5ae SG |
389 | { |
390 | unsigned long long rate; | |
391 | uint val; | |
392 | int n, d; | |
393 | ||
394 | val = readl(&cru->cru_clksel_con[8]); | |
395 | n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT; | |
396 | d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT; | |
397 | ||
398 | rate = (unsigned long long)gclk_rate * n; | |
399 | do_div(rate, d); | |
400 | ||
401 | return (ulong)rate; | |
402 | } | |
403 | ||
b52a199e | 404 | static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate, |
3dbfe5ae SG |
405 | uint freq) |
406 | { | |
407 | int n, d; | |
408 | int v; | |
409 | ||
410 | /* set frac divider */ | |
411 | v = rockchip_clk_gcd(gclk_rate, freq); | |
412 | n = gclk_rate / v; | |
413 | d = freq / v; | |
414 | assert(freq == gclk_rate / n * d); | |
415 | writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT, | |
416 | &cru->cru_clksel_con[8]); | |
417 | ||
418 | return rockchip_i2s_get_clk(cru, gclk_rate); | |
419 | } | |
d3cb46aa | 420 | #endif /* CONFIG_SPL_BUILD */ |
830a6081 | 421 | |
b52a199e | 422 | static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf) |
99c15650 SG |
423 | { |
424 | u32 aclk_div; | |
425 | u32 hclk_div; | |
426 | u32 pclk_div; | |
427 | ||
428 | /* pll enter slow-mode */ | |
429 | rk_clrsetreg(&cru->cru_mode_con, | |
b223c1ae | 430 | GPLL_MODE_MASK | CPLL_MODE_MASK, |
99c15650 SG |
431 | GPLL_MODE_SLOW << GPLL_MODE_SHIFT | |
432 | CPLL_MODE_SLOW << CPLL_MODE_SHIFT); | |
433 | ||
434 | /* init pll */ | |
435 | rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); | |
436 | rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); | |
437 | ||
438 | /* waiting for pll lock */ | |
439 | while ((readl(&grf->soc_status[1]) & | |
440 | (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != | |
441 | (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) | |
442 | udelay(1); | |
443 | ||
444 | /* | |
445 | * pd_bus clock pll source selection and | |
446 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. | |
447 | */ | |
448 | aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; | |
449 | assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); | |
450 | hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; | |
451 | assert((hclk_div + 1) * PD_BUS_HCLK_HZ == | |
452 | PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); | |
453 | ||
454 | pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; | |
455 | assert((pclk_div + 1) * PD_BUS_PCLK_HZ == | |
456 | PD_BUS_ACLK_HZ && pclk_div < 0x7); | |
457 | ||
458 | rk_clrsetreg(&cru->cru_clksel_con[1], | |
b223c1ae SG |
459 | PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | |
460 | PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, | |
99c15650 SG |
461 | pclk_div << PD_BUS_PCLK_DIV_SHIFT | |
462 | hclk_div << PD_BUS_HCLK_DIV_SHIFT | | |
463 | aclk_div << PD_BUS_ACLK_DIV0_SHIFT | | |
464 | 0 << 0); | |
465 | ||
466 | /* | |
467 | * peri clock pll source selection and | |
468 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. | |
469 | */ | |
470 | aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; | |
471 | assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); | |
472 | ||
abd0128e | 473 | hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); |
99c15650 SG |
474 | assert((1 << hclk_div) * PERI_HCLK_HZ == |
475 | PERI_ACLK_HZ && (hclk_div < 0x4)); | |
476 | ||
abd0128e | 477 | pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); |
99c15650 SG |
478 | assert((1 << pclk_div) * PERI_PCLK_HZ == |
479 | PERI_ACLK_HZ && (pclk_div < 0x4)); | |
480 | ||
481 | rk_clrsetreg(&cru->cru_clksel_con[10], | |
b223c1ae SG |
482 | PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | |
483 | PERI_ACLK_DIV_MASK, | |
c87c129f | 484 | PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | |
99c15650 SG |
485 | pclk_div << PERI_PCLK_DIV_SHIFT | |
486 | hclk_div << PERI_HCLK_DIV_SHIFT | | |
487 | aclk_div << PERI_ACLK_DIV_SHIFT); | |
488 | ||
489 | /* PLL enter normal-mode */ | |
490 | rk_clrsetreg(&cru->cru_mode_con, | |
b223c1ae | 491 | GPLL_MODE_MASK | CPLL_MODE_MASK, |
009741fb SG |
492 | GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | |
493 | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); | |
99c15650 | 494 | } |
99c15650 | 495 | |
b52a199e | 496 | void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf) |
dae594f2 SG |
497 | { |
498 | /* pll enter slow-mode */ | |
b223c1ae | 499 | rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, |
dae594f2 SG |
500 | APLL_MODE_SLOW << APLL_MODE_SHIFT); |
501 | ||
502 | rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); | |
503 | ||
504 | /* waiting for pll lock */ | |
505 | while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) | |
506 | udelay(1); | |
507 | ||
508 | /* | |
509 | * core clock pll source selection and | |
510 | * set up dependent divisors for MPAXI/M0AXI and ARM clocks. | |
511 | * core clock select apll, apll clk = 1800MHz | |
512 | * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz | |
513 | */ | |
514 | rk_clrsetreg(&cru->cru_clksel_con[0], | |
b223c1ae SG |
515 | CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | |
516 | M0_DIV_MASK, | |
dae594f2 SG |
517 | 0 << A17_DIV_SHIFT | |
518 | 3 << MP_DIV_SHIFT | | |
519 | 1 << M0_DIV_SHIFT); | |
520 | ||
521 | /* | |
522 | * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. | |
523 | * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz | |
524 | */ | |
525 | rk_clrsetreg(&cru->cru_clksel_con[37], | |
b223c1ae SG |
526 | CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | |
527 | PCLK_CORE_DBG_DIV_MASK, | |
dae594f2 SG |
528 | 1 << CLK_L2RAM_DIV_SHIFT | |
529 | 3 << ATCLK_CORE_DIV_CON_SHIFT | | |
530 | 3 << PCLK_CORE_DBG_DIV_SHIFT); | |
531 | ||
532 | /* PLL enter normal-mode */ | |
b223c1ae | 533 | rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, |
dae594f2 SG |
534 | APLL_MODE_NORMAL << APLL_MODE_SHIFT); |
535 | } | |
536 | ||
99c15650 | 537 | /* Get pll rate by id */ |
b52a199e | 538 | static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru, |
99c15650 SG |
539 | enum rk_clk_id clk_id) |
540 | { | |
541 | uint32_t nr, no, nf; | |
542 | uint32_t con; | |
543 | int pll_id = rk_pll_id(clk_id); | |
544 | struct rk3288_pll *pll = &cru->pll[pll_id]; | |
545 | static u8 clk_shift[CLK_COUNT] = { | |
009741fb SG |
546 | 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, |
547 | GPLL_MODE_SHIFT, NPLL_MODE_SHIFT | |
99c15650 SG |
548 | }; |
549 | uint shift; | |
550 | ||
551 | con = readl(&cru->cru_mode_con); | |
552 | shift = clk_shift[clk_id]; | |
b223c1ae | 553 | switch ((con >> shift) & CRU_MODE_MASK) { |
009741fb | 554 | case APLL_MODE_SLOW: |
99c15650 | 555 | return OSC_HZ; |
009741fb | 556 | case APLL_MODE_NORMAL: |
99c15650 SG |
557 | /* normal mode */ |
558 | con = readl(&pll->con0); | |
b223c1ae SG |
559 | no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; |
560 | nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; | |
99c15650 | 561 | con = readl(&pll->con1); |
b223c1ae | 562 | nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; |
99c15650 SG |
563 | |
564 | return (24 * nf / (nr * no)) * 1000000; | |
009741fb | 565 | case APLL_MODE_DEEP: |
99c15650 SG |
566 | default: |
567 | return 32768; | |
568 | } | |
569 | } | |
570 | ||
b52a199e | 571 | static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate, |
898d6439 | 572 | int periph) |
99c15650 SG |
573 | { |
574 | uint src_rate; | |
575 | uint div, mux; | |
576 | u32 con; | |
577 | ||
578 | switch (periph) { | |
898d6439 | 579 | case HCLK_EMMC: |
45112271 | 580 | case SCLK_EMMC: |
99c15650 | 581 | con = readl(&cru->cru_clksel_con[12]); |
b223c1ae SG |
582 | mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; |
583 | div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; | |
99c15650 | 584 | break; |
898d6439 | 585 | case HCLK_SDMMC: |
45112271 | 586 | case SCLK_SDMMC: |
898d6439 | 587 | con = readl(&cru->cru_clksel_con[11]); |
b223c1ae SG |
588 | mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; |
589 | div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; | |
99c15650 | 590 | break; |
898d6439 | 591 | case HCLK_SDIO0: |
45112271 | 592 | case SCLK_SDIO0: |
99c15650 | 593 | con = readl(&cru->cru_clksel_con[12]); |
b223c1ae SG |
594 | mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; |
595 | div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; | |
99c15650 SG |
596 | break; |
597 | default: | |
598 | return -EINVAL; | |
599 | } | |
600 | ||
542635a0 | 601 | src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; |
99c15650 SG |
602 | return DIV_TO_RATE(src_rate, div); |
603 | } | |
604 | ||
b52a199e | 605 | static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate, |
898d6439 | 606 | int periph, uint freq) |
99c15650 SG |
607 | { |
608 | int src_clk_div; | |
609 | int mux; | |
610 | ||
542635a0 | 611 | debug("%s: gclk_rate=%u\n", __func__, gclk_rate); |
3a94d75d KY |
612 | /* mmc clock default div 2 internal, need provide double in cru */ |
613 | src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); | |
99c15650 SG |
614 | |
615 | if (src_clk_div > 0x3f) { | |
3a94d75d | 616 | src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); |
217273cd | 617 | assert(src_clk_div < 0x40); |
99c15650 SG |
618 | mux = EMMC_PLL_SELECT_24MHZ; |
619 | assert((int)EMMC_PLL_SELECT_24MHZ == | |
620 | (int)MMC0_PLL_SELECT_24MHZ); | |
621 | } else { | |
622 | mux = EMMC_PLL_SELECT_GENERAL; | |
623 | assert((int)EMMC_PLL_SELECT_GENERAL == | |
624 | (int)MMC0_PLL_SELECT_GENERAL); | |
625 | } | |
626 | switch (periph) { | |
898d6439 | 627 | case HCLK_EMMC: |
45112271 | 628 | case SCLK_EMMC: |
99c15650 | 629 | rk_clrsetreg(&cru->cru_clksel_con[12], |
b223c1ae | 630 | EMMC_PLL_MASK | EMMC_DIV_MASK, |
99c15650 SG |
631 | mux << EMMC_PLL_SHIFT | |
632 | (src_clk_div - 1) << EMMC_DIV_SHIFT); | |
633 | break; | |
898d6439 | 634 | case HCLK_SDMMC: |
45112271 | 635 | case SCLK_SDMMC: |
99c15650 | 636 | rk_clrsetreg(&cru->cru_clksel_con[11], |
b223c1ae | 637 | MMC0_PLL_MASK | MMC0_DIV_MASK, |
99c15650 SG |
638 | mux << MMC0_PLL_SHIFT | |
639 | (src_clk_div - 1) << MMC0_DIV_SHIFT); | |
640 | break; | |
898d6439 | 641 | case HCLK_SDIO0: |
45112271 | 642 | case SCLK_SDIO0: |
99c15650 | 643 | rk_clrsetreg(&cru->cru_clksel_con[12], |
b223c1ae | 644 | SDIO0_PLL_MASK | SDIO0_DIV_MASK, |
99c15650 SG |
645 | mux << SDIO0_PLL_SHIFT | |
646 | (src_clk_div - 1) << SDIO0_DIV_SHIFT); | |
647 | break; | |
648 | default: | |
649 | return -EINVAL; | |
650 | } | |
651 | ||
542635a0 | 652 | return rockchip_mmc_get_clk(cru, gclk_rate, periph); |
99c15650 SG |
653 | } |
654 | ||
b52a199e | 655 | static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate, |
898d6439 | 656 | int periph) |
99c15650 SG |
657 | { |
658 | uint div, mux; | |
659 | u32 con; | |
660 | ||
661 | switch (periph) { | |
898d6439 | 662 | case SCLK_SPI0: |
99c15650 | 663 | con = readl(&cru->cru_clksel_con[25]); |
b223c1ae SG |
664 | mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; |
665 | div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; | |
99c15650 | 666 | break; |
898d6439 | 667 | case SCLK_SPI1: |
99c15650 | 668 | con = readl(&cru->cru_clksel_con[25]); |
b223c1ae SG |
669 | mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; |
670 | div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; | |
99c15650 | 671 | break; |
898d6439 | 672 | case SCLK_SPI2: |
99c15650 | 673 | con = readl(&cru->cru_clksel_con[39]); |
b223c1ae SG |
674 | mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; |
675 | div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; | |
99c15650 SG |
676 | break; |
677 | default: | |
678 | return -EINVAL; | |
679 | } | |
680 | assert(mux == SPI0_PLL_SELECT_GENERAL); | |
681 | ||
542635a0 | 682 | return DIV_TO_RATE(gclk_rate, div); |
99c15650 SG |
683 | } |
684 | ||
b52a199e | 685 | static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate, |
898d6439 | 686 | int periph, uint freq) |
99c15650 SG |
687 | { |
688 | int src_clk_div; | |
689 | ||
542635a0 | 690 | debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); |
217273cd KY |
691 | src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; |
692 | assert(src_clk_div < 128); | |
99c15650 | 693 | switch (periph) { |
898d6439 | 694 | case SCLK_SPI0: |
99c15650 | 695 | rk_clrsetreg(&cru->cru_clksel_con[25], |
b223c1ae | 696 | SPI0_PLL_MASK | SPI0_DIV_MASK, |
99c15650 SG |
697 | SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | |
698 | src_clk_div << SPI0_DIV_SHIFT); | |
699 | break; | |
898d6439 | 700 | case SCLK_SPI1: |
99c15650 | 701 | rk_clrsetreg(&cru->cru_clksel_con[25], |
b223c1ae | 702 | SPI1_PLL_MASK | SPI1_DIV_MASK, |
99c15650 SG |
703 | SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | |
704 | src_clk_div << SPI1_DIV_SHIFT); | |
705 | break; | |
898d6439 | 706 | case SCLK_SPI2: |
99c15650 | 707 | rk_clrsetreg(&cru->cru_clksel_con[39], |
b223c1ae | 708 | SPI2_PLL_MASK | SPI2_DIV_MASK, |
99c15650 SG |
709 | SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | |
710 | src_clk_div << SPI2_DIV_SHIFT); | |
711 | break; | |
712 | default: | |
713 | return -EINVAL; | |
714 | } | |
715 | ||
542635a0 | 716 | return rockchip_spi_get_clk(cru, gclk_rate, periph); |
99c15650 SG |
717 | } |
718 | ||
b52a199e | 719 | static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru) |
ef4cf5ae DW |
720 | { |
721 | u32 div, val; | |
722 | ||
723 | val = readl(&cru->cru_clksel_con[24]); | |
724 | div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, | |
725 | CLK_SARADC_DIV_CON_WIDTH); | |
726 | ||
727 | return DIV_TO_RATE(OSC_HZ, div); | |
728 | } | |
729 | ||
b52a199e | 730 | static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz) |
ef4cf5ae DW |
731 | { |
732 | int src_clk_div; | |
733 | ||
734 | src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; | |
735 | assert(src_clk_div < 128); | |
736 | ||
737 | rk_clrsetreg(&cru->cru_clksel_con[24], | |
738 | CLK_SARADC_DIV_CON_MASK, | |
739 | src_clk_div << CLK_SARADC_DIV_CON_SHIFT); | |
740 | ||
741 | return rockchip_saradc_get_clk(cru); | |
742 | } | |
743 | ||
135aa950 | 744 | static ulong rk3288_clk_get_rate(struct clk *clk) |
4f43673e | 745 | { |
135aa950 | 746 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); |
4f43673e | 747 | ulong new_rate, gclk_rate; |
4f43673e | 748 | |
135aa950 SW |
749 | gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); |
750 | switch (clk->id) { | |
751 | case 0 ... 63: | |
752 | new_rate = rkclk_pll_get_rate(priv->cru, clk->id); | |
753 | break; | |
4f43673e | 754 | case HCLK_EMMC: |
342999f9 | 755 | case HCLK_SDMMC: |
4f43673e | 756 | case HCLK_SDIO0: |
45112271 XZ |
757 | case SCLK_EMMC: |
758 | case SCLK_SDMMC: | |
759 | case SCLK_SDIO0: | |
135aa950 | 760 | new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); |
4f43673e SG |
761 | break; |
762 | case SCLK_SPI0: | |
763 | case SCLK_SPI1: | |
764 | case SCLK_SPI2: | |
135aa950 | 765 | new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); |
4f43673e SG |
766 | break; |
767 | case PCLK_I2C0: | |
768 | case PCLK_I2C1: | |
769 | case PCLK_I2C2: | |
770 | case PCLK_I2C3: | |
771 | case PCLK_I2C4: | |
772 | case PCLK_I2C5: | |
773 | return gclk_rate; | |
4f0b8efa KY |
774 | case PCLK_PWM: |
775 | return PD_BUS_PCLK_HZ; | |
ef4cf5ae DW |
776 | case SCLK_SARADC: |
777 | new_rate = rockchip_saradc_get_clk(priv->cru); | |
778 | break; | |
4f43673e SG |
779 | default: |
780 | return -ENOENT; | |
781 | } | |
782 | ||
783 | return new_rate; | |
784 | } | |
785 | ||
135aa950 | 786 | static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) |
99c15650 | 787 | { |
135aa950 | 788 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); |
b52a199e | 789 | struct rockchip_cru *cru = priv->cru; |
898d6439 | 790 | ulong new_rate, gclk_rate; |
898d6439 | 791 | |
135aa950 SW |
792 | gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); |
793 | switch (clk->id) { | |
3a8a42d9 SG |
794 | case PLL_APLL: |
795 | /* We only support a fixed rate here */ | |
796 | if (rate != 1800000000) | |
797 | return -EINVAL; | |
798 | rk3288_clk_configure_cpu(priv->cru, priv->grf); | |
799 | new_rate = rate; | |
800 | break; | |
135aa950 SW |
801 | case CLK_DDR: |
802 | new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); | |
803 | break; | |
898d6439 SG |
804 | case HCLK_EMMC: |
805 | case HCLK_SDMMC: | |
806 | case HCLK_SDIO0: | |
45112271 XZ |
807 | case SCLK_EMMC: |
808 | case SCLK_SDMMC: | |
809 | case SCLK_SDIO0: | |
135aa950 | 810 | new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); |
99c15650 | 811 | break; |
898d6439 SG |
812 | case SCLK_SPI0: |
813 | case SCLK_SPI1: | |
814 | case SCLK_SPI2: | |
135aa950 | 815 | new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); |
99c15650 | 816 | break; |
830a6081 | 817 | #ifndef CONFIG_SPL_BUILD |
3dbfe5ae SG |
818 | case SCLK_I2S0: |
819 | new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate); | |
820 | break; | |
0aefc0b0 | 821 | case SCLK_MAC: |
01c60eaf | 822 | new_rate = rockchip_mac_set_clk(priv->cru, rate); |
0aefc0b0 | 823 | break; |
830a6081 SG |
824 | case DCLK_VOP0: |
825 | case DCLK_VOP1: | |
135aa950 | 826 | new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); |
830a6081 SG |
827 | break; |
828 | case SCLK_EDP_24M: | |
829 | /* clk_edp_24M source: 24M */ | |
830 | rk_setreg(&cru->cru_clksel_con[28], 1 << 15); | |
831 | ||
832 | /* rst edp */ | |
833 | rk_setreg(&cru->cru_clksel_con[6], 1 << 15); | |
834 | udelay(1); | |
835 | rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); | |
836 | new_rate = rate; | |
837 | break; | |
838 | case ACLK_VOP0: | |
839 | case ACLK_VOP1: { | |
840 | u32 div; | |
841 | ||
842 | /* vop aclk source clk: cpll */ | |
843 | div = CPLL_HZ / rate; | |
844 | assert((div - 1 < 64) && (div * rate == CPLL_HZ)); | |
845 | ||
135aa950 | 846 | switch (clk->id) { |
830a6081 SG |
847 | case ACLK_VOP0: |
848 | rk_clrsetreg(&cru->cru_clksel_con[31], | |
849 | 3 << 6 | 0x1f << 0, | |
850 | 0 << 6 | (div - 1) << 0); | |
851 | break; | |
852 | case ACLK_VOP1: | |
853 | rk_clrsetreg(&cru->cru_clksel_con[31], | |
854 | 3 << 14 | 0x1f << 8, | |
855 | 0 << 14 | (div - 1) << 8); | |
856 | break; | |
857 | } | |
858 | new_rate = rate; | |
859 | break; | |
860 | } | |
861 | case PCLK_HDMI_CTRL: | |
862 | /* enable pclk hdmi ctrl */ | |
863 | rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); | |
864 | ||
865 | /* software reset hdmi */ | |
866 | rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); | |
867 | udelay(1); | |
868 | rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); | |
869 | new_rate = rate; | |
870 | break; | |
871 | #endif | |
ef4cf5ae DW |
872 | case SCLK_SARADC: |
873 | new_rate = rockchip_saradc_set_clk(priv->cru, rate); | |
874 | break; | |
01c60eaf DW |
875 | case PLL_GPLL: |
876 | case PLL_CPLL: | |
877 | case PLL_NPLL: | |
878 | case ACLK_CPU: | |
879 | case HCLK_CPU: | |
880 | case PCLK_CPU: | |
881 | case ACLK_PERI: | |
882 | case HCLK_PERI: | |
883 | case PCLK_PERI: | |
884 | case SCLK_UART0: | |
885 | return 0; | |
99c15650 SG |
886 | default: |
887 | return -ENOENT; | |
888 | } | |
889 | ||
890 | return new_rate; | |
891 | } | |
892 | ||
75b381aa | 893 | static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) |
01c60eaf DW |
894 | { |
895 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); | |
b52a199e | 896 | struct rockchip_cru *cru = priv->cru; |
01c60eaf DW |
897 | const char *clock_output_name; |
898 | int ret; | |
899 | ||
900 | /* | |
901 | * If the requested parent is in the same clock-controller and | |
902 | * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal | |
903 | * clock. | |
904 | */ | |
905 | if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { | |
906 | debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); | |
907 | rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); | |
908 | return 0; | |
909 | } | |
910 | ||
911 | /* | |
912 | * Otherwise, we need to check the clock-output-names of the | |
913 | * requested parent to see if the requested id is "ext_gmac". | |
914 | */ | |
915 | ret = dev_read_string_index(parent->dev, "clock-output-names", | |
916 | parent->id, &clock_output_name); | |
917 | if (ret < 0) | |
918 | return -ENODATA; | |
919 | ||
920 | /* If this is "ext_gmac", switch to the external clock input */ | |
921 | if (!strcmp(clock_output_name, "ext_gmac")) { | |
922 | debug("%s: switching GMAC to external clock\n", __func__); | |
923 | rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, | |
924 | RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); | |
925 | return 0; | |
926 | } | |
927 | ||
928 | return -EINVAL; | |
929 | } | |
930 | ||
75b381aa | 931 | static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent) |
01c60eaf DW |
932 | { |
933 | switch (clk->id) { | |
934 | case SCLK_MAC: | |
935 | return rk3288_gmac_set_parent(clk, parent); | |
936 | case SCLK_USBPHY480M_SRC: | |
937 | return 0; | |
938 | } | |
939 | ||
940 | debug("%s: unsupported clk %ld\n", __func__, clk->id); | |
941 | return -ENOENT; | |
942 | } | |
943 | ||
99c15650 SG |
944 | static struct clk_ops rk3288_clk_ops = { |
945 | .get_rate = rk3288_clk_get_rate, | |
946 | .set_rate = rk3288_clk_set_rate, | |
75b381aa | 947 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
01c60eaf | 948 | .set_parent = rk3288_clk_set_parent, |
75b381aa | 949 | #endif |
99c15650 SG |
950 | }; |
951 | ||
08fd82cf | 952 | static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) |
99c15650 | 953 | { |
2d143bd6 | 954 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
99c15650 SG |
955 | struct rk3288_clk_priv *priv = dev_get_priv(dev); |
956 | ||
995cde1f | 957 | priv->cru = dev_read_addr_ptr(dev); |
2d143bd6 | 958 | #endif |
08fd82cf SG |
959 | |
960 | return 0; | |
961 | } | |
962 | ||
963 | static int rk3288_clk_probe(struct udevice *dev) | |
964 | { | |
965 | struct rk3288_clk_priv *priv = dev_get_priv(dev); | |
d3cb46aa | 966 | bool init_clocks = false; |
08fd82cf | 967 | |
99c15650 | 968 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
08fd82cf SG |
969 | if (IS_ERR(priv->grf)) |
970 | return PTR_ERR(priv->grf); | |
99c15650 | 971 | #ifdef CONFIG_SPL_BUILD |
2d143bd6 SG |
972 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
973 | struct rk3288_clk_plat *plat = dev_get_platdata(dev); | |
974 | ||
975 | priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); | |
976 | #endif | |
d3cb46aa | 977 | init_clocks = true; |
99c15650 | 978 | #endif |
d3cb46aa SG |
979 | if (!(gd->flags & GD_FLG_RELOC)) { |
980 | u32 reg; | |
981 | ||
982 | /* | |
983 | * Init clocks in U-Boot proper if the NPLL is runnning. This | |
984 | * indicates that a previous boot loader set up the clocks, so | |
985 | * we need to redo it. U-Boot's SPL does not set this clock. | |
986 | */ | |
987 | reg = readl(&priv->cru->cru_mode_con); | |
988 | if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == | |
989 | NPLL_MODE_NORMAL) | |
990 | init_clocks = true; | |
991 | } | |
992 | ||
993 | if (init_clocks) | |
994 | rkclk_init(priv->cru, priv->grf); | |
99c15650 SG |
995 | |
996 | return 0; | |
997 | } | |
998 | ||
99c15650 SG |
999 | static int rk3288_clk_bind(struct udevice *dev) |
1000 | { | |
135aa950 | 1001 | int ret; |
f24e36da KY |
1002 | struct udevice *sys_child; |
1003 | struct sysreset_reg *priv; | |
99c15650 SG |
1004 | |
1005 | /* The reset driver does not have a device node, so bind it here */ | |
f24e36da KY |
1006 | ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", |
1007 | &sys_child); | |
1008 | if (ret) { | |
1009 | debug("Warning: No sysreset driver: ret=%d\n", ret); | |
1010 | } else { | |
1011 | priv = malloc(sizeof(struct sysreset_reg)); | |
b52a199e | 1012 | priv->glb_srst_fst_value = offsetof(struct rockchip_cru, |
f24e36da | 1013 | cru_glb_srst_fst_value); |
b52a199e | 1014 | priv->glb_srst_snd_value = offsetof(struct rockchip_cru, |
f24e36da KY |
1015 | cru_glb_srst_snd_value); |
1016 | sys_child->priv = priv; | |
1017 | } | |
99c15650 | 1018 | |
a5ada25e | 1019 | #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) |
b52a199e | 1020 | ret = offsetof(struct rockchip_cru, cru_softrst_con[0]); |
538f67c3 EZ |
1021 | ret = rockchip_reset_bind(dev, ret, 12); |
1022 | if (ret) | |
1023 | debug("Warning: software reset driver bind faile\n"); | |
1024 | #endif | |
1025 | ||
99c15650 SG |
1026 | return 0; |
1027 | } | |
1028 | ||
1029 | static const struct udevice_id rk3288_clk_ids[] = { | |
1030 | { .compatible = "rockchip,rk3288-cru" }, | |
1031 | { } | |
1032 | }; | |
1033 | ||
2d143bd6 SG |
1034 | U_BOOT_DRIVER(rockchip_rk3288_cru) = { |
1035 | .name = "rockchip_rk3288_cru", | |
99c15650 SG |
1036 | .id = UCLASS_CLK, |
1037 | .of_match = rk3288_clk_ids, | |
1038 | .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), | |
2d143bd6 | 1039 | .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), |
99c15650 SG |
1040 | .ops = &rk3288_clk_ops, |
1041 | .bind = rk3288_clk_bind, | |
08fd82cf | 1042 | .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata, |
99c15650 SG |
1043 | .probe = rk3288_clk_probe, |
1044 | }; |