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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
99c15650 SG |
2 | /* |
3 | * (C) Copyright 2015 Google, Inc | |
99c15650 SG |
4 | */ |
5 | ||
6 | #include <common.h> | |
ef4cf5ae | 7 | #include <bitfield.h> |
135aa950 | 8 | #include <clk-uclass.h> |
3dbfe5ae | 9 | #include <div64.h> |
99c15650 | 10 | #include <dm.h> |
2d143bd6 | 11 | #include <dt-structs.h> |
99c15650 | 12 | #include <errno.h> |
2d143bd6 | 13 | #include <mapmem.h> |
99c15650 SG |
14 | #include <syscon.h> |
15 | #include <asm/io.h> | |
16 | #include <asm/arch/clock.h> | |
17 | #include <asm/arch/cru_rk3288.h> | |
18 | #include <asm/arch/grf_rk3288.h> | |
19 | #include <asm/arch/hardware.h> | |
898d6439 | 20 | #include <dt-bindings/clock/rk3288-cru.h> |
64b7faa7 | 21 | #include <dm/device-internal.h> |
99c15650 | 22 | #include <dm/lists.h> |
64b7faa7 | 23 | #include <dm/uclass-internal.h> |
abd0128e | 24 | #include <linux/log2.h> |
99c15650 SG |
25 | |
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
2d143bd6 SG |
28 | struct rk3288_clk_plat { |
29 | #if CONFIG_IS_ENABLED(OF_PLATDATA) | |
30 | struct dtd_rockchip_rk3288_cru dtd; | |
31 | #endif | |
32 | }; | |
33 | ||
99c15650 SG |
34 | struct pll_div { |
35 | u32 nr; | |
36 | u32 nf; | |
37 | u32 no; | |
38 | }; | |
39 | ||
40 | enum { | |
41 | VCO_MAX_HZ = 2200U * 1000000, | |
42 | VCO_MIN_HZ = 440 * 1000000, | |
43 | OUTPUT_MAX_HZ = 2200U * 1000000, | |
44 | OUTPUT_MIN_HZ = 27500000, | |
45 | FREF_MAX_HZ = 2200U * 1000000, | |
c3f03ffb | 46 | FREF_MIN_HZ = 269 * 1000, |
99c15650 SG |
47 | }; |
48 | ||
49 | enum { | |
50 | /* PLL CON0 */ | |
51 | PLL_OD_MASK = 0x0f, | |
52 | ||
53 | /* PLL CON1 */ | |
54 | PLL_NF_MASK = 0x1fff, | |
55 | ||
56 | /* PLL CON2 */ | |
57 | PLL_BWADJ_MASK = 0x0fff, | |
58 | ||
59 | /* PLL CON3 */ | |
60 | PLL_RESET_SHIFT = 5, | |
61 | ||
dae594f2 | 62 | /* CLKSEL0 */ |
dae594f2 | 63 | CORE_SEL_PLL_SHIFT = 15, |
b223c1ae | 64 | CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, |
dae594f2 | 65 | A17_DIV_SHIFT = 8, |
b223c1ae | 66 | A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, |
dae594f2 | 67 | MP_DIV_SHIFT = 4, |
b223c1ae | 68 | MP_DIV_MASK = 0xf << MP_DIV_SHIFT, |
dae594f2 | 69 | M0_DIV_SHIFT = 0, |
b223c1ae | 70 | M0_DIV_MASK = 0xf << M0_DIV_SHIFT, |
dae594f2 | 71 | |
99c15650 SG |
72 | /* CLKSEL1: pd bus clk pll sel: codec or general */ |
73 | PD_BUS_SEL_PLL_MASK = 15, | |
74 | PD_BUS_SEL_CPLL = 0, | |
75 | PD_BUS_SEL_GPLL, | |
76 | ||
77 | /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ | |
78 | PD_BUS_PCLK_DIV_SHIFT = 12, | |
b223c1ae | 79 | PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, |
99c15650 SG |
80 | |
81 | /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ | |
82 | PD_BUS_HCLK_DIV_SHIFT = 8, | |
b223c1ae | 83 | PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, |
99c15650 SG |
84 | |
85 | /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ | |
86 | PD_BUS_ACLK_DIV0_SHIFT = 3, | |
b223c1ae | 87 | PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, |
99c15650 | 88 | PD_BUS_ACLK_DIV1_SHIFT = 0, |
b223c1ae | 89 | PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, |
99c15650 SG |
90 | |
91 | /* | |
92 | * CLKSEL10 | |
93 | * peripheral bus pclk div: | |
94 | * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 | |
95 | */ | |
c87c129f | 96 | PERI_SEL_PLL_SHIFT = 15, |
b223c1ae | 97 | PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, |
c87c129f SG |
98 | PERI_SEL_CPLL = 0, |
99 | PERI_SEL_GPLL, | |
100 | ||
99c15650 | 101 | PERI_PCLK_DIV_SHIFT = 12, |
b223c1ae | 102 | PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, |
99c15650 SG |
103 | |
104 | /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ | |
105 | PERI_HCLK_DIV_SHIFT = 8, | |
b223c1ae | 106 | PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, |
99c15650 SG |
107 | |
108 | /* | |
109 | * peripheral bus aclk div: | |
110 | * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) | |
111 | */ | |
112 | PERI_ACLK_DIV_SHIFT = 0, | |
b223c1ae | 113 | PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, |
99c15650 | 114 | |
ef4cf5ae DW |
115 | /* |
116 | * CLKSEL24 | |
117 | * saradc_div_con: | |
118 | * clk_saradc=24MHz/(saradc_div_con+1) | |
119 | */ | |
120 | CLK_SARADC_DIV_CON_SHIFT = 8, | |
121 | CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), | |
122 | CLK_SARADC_DIV_CON_WIDTH = 8, | |
123 | ||
99c15650 SG |
124 | SOCSTS_DPLL_LOCK = 1 << 5, |
125 | SOCSTS_APLL_LOCK = 1 << 6, | |
126 | SOCSTS_CPLL_LOCK = 1 << 7, | |
127 | SOCSTS_GPLL_LOCK = 1 << 8, | |
128 | SOCSTS_NPLL_LOCK = 1 << 9, | |
129 | }; | |
130 | ||
99c15650 SG |
131 | #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) |
132 | ||
133 | #define PLL_DIVISORS(hz, _nr, _no) {\ | |
134 | .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ | |
135 | _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ | |
136 | (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ | |
137 | "divisors on line " __stringify(__LINE__)); | |
138 | ||
139 | /* Keep divisors as low as possible to reduce jitter and power usage */ | |
140 | static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); | |
141 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); | |
142 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); | |
143 | ||
144 | static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, | |
145 | const struct pll_div *div) | |
146 | { | |
147 | int pll_id = rk_pll_id(clk_id); | |
148 | struct rk3288_pll *pll = &cru->pll[pll_id]; | |
149 | /* All PLLs have same VCO and output frequency range restrictions. */ | |
150 | uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; | |
151 | uint output_hz = vco_hz / div->no; | |
152 | ||
c87c129f SG |
153 | debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", |
154 | (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); | |
99c15650 SG |
155 | assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && |
156 | output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && | |
157 | (div->no == 1 || !(div->no % 2))); | |
158 | ||
c87c129f | 159 | /* enter reset */ |
99c15650 SG |
160 | rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
161 | ||
b223c1ae | 162 | rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, |
99c15650 SG |
163 | ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); |
164 | rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); | |
165 | rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); | |
166 | ||
167 | udelay(10); | |
168 | ||
c87c129f | 169 | /* return from reset */ |
99c15650 SG |
170 | rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
99c15650 SG |
175 | static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, |
176 | unsigned int hz) | |
177 | { | |
178 | static const struct pll_div dpll_cfg[] = { | |
179 | {.nf = 25, .nr = 2, .no = 1}, | |
180 | {.nf = 400, .nr = 9, .no = 2}, | |
181 | {.nf = 500, .nr = 9, .no = 2}, | |
182 | {.nf = 100, .nr = 3, .no = 1}, | |
183 | }; | |
184 | int cfg; | |
185 | ||
99c15650 SG |
186 | switch (hz) { |
187 | case 300000000: | |
188 | cfg = 0; | |
189 | break; | |
190 | case 533000000: /* actually 533.3P MHz */ | |
191 | cfg = 1; | |
192 | break; | |
193 | case 666000000: /* actually 666.6P MHz */ | |
194 | cfg = 2; | |
195 | break; | |
196 | case 800000000: | |
197 | cfg = 3; | |
198 | break; | |
199 | default: | |
c87c129f | 200 | debug("Unsupported SDRAM frequency"); |
99c15650 SG |
201 | return -EINVAL; |
202 | } | |
203 | ||
204 | /* pll enter slow-mode */ | |
b223c1ae | 205 | rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, |
99c15650 SG |
206 | DPLL_MODE_SLOW << DPLL_MODE_SHIFT); |
207 | ||
208 | rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); | |
209 | ||
210 | /* wait for pll lock */ | |
211 | while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) | |
212 | udelay(1); | |
213 | ||
214 | /* PLL enter normal-mode */ | |
b223c1ae | 215 | rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, |
009741fb | 216 | DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); |
99c15650 SG |
217 | |
218 | return 0; | |
219 | } | |
220 | ||
830a6081 SG |
221 | #ifndef CONFIG_SPL_BUILD |
222 | #define VCO_MAX_KHZ 2200000 | |
223 | #define VCO_MIN_KHZ 440000 | |
224 | #define FREF_MAX_KHZ 2200000 | |
225 | #define FREF_MIN_KHZ 269 | |
226 | ||
227 | static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) | |
228 | { | |
229 | uint ref_khz = OSC_HZ / 1000, nr, nf = 0; | |
230 | uint fref_khz; | |
231 | uint diff_khz, best_diff_khz; | |
232 | const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4; | |
233 | uint vco_khz; | |
234 | uint no = 1; | |
235 | uint freq_khz = freq_hz / 1000; | |
236 | ||
237 | if (!freq_hz) { | |
238 | printf("%s: the frequency can not be 0 Hz\n", __func__); | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); | |
243 | if (ext_div) { | |
244 | *ext_div = DIV_ROUND_UP(no, max_no); | |
245 | no = DIV_ROUND_UP(no, *ext_div); | |
246 | } | |
247 | ||
248 | /* only even divisors (and 1) are supported */ | |
249 | if (no > 1) | |
250 | no = DIV_ROUND_UP(no, 2) * 2; | |
251 | ||
252 | vco_khz = freq_khz * no; | |
253 | if (ext_div) | |
254 | vco_khz *= *ext_div; | |
255 | ||
256 | if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { | |
257 | printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n", | |
258 | __func__, freq_hz); | |
259 | return -1; | |
260 | } | |
261 | ||
262 | div->no = no; | |
263 | ||
264 | best_diff_khz = vco_khz; | |
265 | for (nr = 1; nr < max_nr && best_diff_khz; nr++) { | |
266 | fref_khz = ref_khz / nr; | |
267 | if (fref_khz < FREF_MIN_KHZ) | |
268 | break; | |
269 | if (fref_khz > FREF_MAX_KHZ) | |
270 | continue; | |
271 | ||
272 | nf = vco_khz / fref_khz; | |
273 | if (nf >= max_nf) | |
274 | continue; | |
275 | diff_khz = vco_khz - nf * fref_khz; | |
276 | if (nf + 1 < max_nf && diff_khz > fref_khz / 2) { | |
277 | nf++; | |
278 | diff_khz = fref_khz - diff_khz; | |
279 | } | |
280 | ||
281 | if (diff_khz >= best_diff_khz) | |
282 | continue; | |
283 | ||
284 | best_diff_khz = diff_khz; | |
285 | div->nr = nr; | |
286 | div->nf = nf; | |
287 | } | |
288 | ||
289 | if (best_diff_khz > 4 * 1000) { | |
290 | printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n", | |
291 | __func__, freq_hz, best_diff_khz * 1000); | |
292 | return -EINVAL; | |
293 | } | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
01c60eaf | 298 | static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) |
0aefc0b0 | 299 | { |
01c60eaf | 300 | ulong ret; |
0aefc0b0 | 301 | |
01c60eaf DW |
302 | /* |
303 | * The gmac clock can be derived either from an external clock | |
304 | * or can be generated from internally by a divider from SCLK_MAC. | |
305 | */ | |
306 | if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { | |
307 | /* An external clock will always generate the right rate... */ | |
308 | ret = freq; | |
309 | } else { | |
310 | u32 con = readl(&cru->cru_clksel_con[21]); | |
311 | ulong pll_rate; | |
312 | u8 div; | |
313 | ||
314 | if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == | |
315 | EMAC_PLL_SELECT_GENERAL) | |
316 | pll_rate = GPLL_HZ; | |
317 | else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == | |
318 | EMAC_PLL_SELECT_CODEC) | |
319 | pll_rate = CPLL_HZ; | |
320 | else | |
321 | pll_rate = NPLL_HZ; | |
322 | ||
323 | div = DIV_ROUND_UP(pll_rate, freq) - 1; | |
324 | if (div <= 0x1f) | |
325 | rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, | |
326 | div << MAC_DIV_CON_SHIFT); | |
327 | else | |
328 | debug("Unsupported div for gmac:%d\n", div); | |
329 | ||
330 | return DIV_TO_RATE(pll_rate, div); | |
331 | } | |
332 | ||
333 | return ret; | |
0aefc0b0 SS |
334 | } |
335 | ||
830a6081 SG |
336 | static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, |
337 | int periph, unsigned int rate_hz) | |
338 | { | |
339 | struct pll_div npll_config = {0}; | |
340 | u32 lcdc_div; | |
341 | int ret; | |
342 | ||
343 | ret = pll_para_config(rate_hz, &npll_config, &lcdc_div); | |
344 | if (ret) | |
345 | return ret; | |
346 | ||
b223c1ae | 347 | rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, |
830a6081 SG |
348 | NPLL_MODE_SLOW << NPLL_MODE_SHIFT); |
349 | rkclk_set_pll(cru, CLK_NEW, &npll_config); | |
350 | ||
351 | /* waiting for pll lock */ | |
352 | while (1) { | |
353 | if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK) | |
354 | break; | |
355 | udelay(1); | |
356 | } | |
357 | ||
b223c1ae | 358 | rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, |
830a6081 SG |
359 | NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); |
360 | ||
361 | /* vop dclk source clk: npll,dclk_div: 1 */ | |
362 | switch (periph) { | |
363 | case DCLK_VOP0: | |
364 | rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, | |
365 | (lcdc_div - 1) << 8 | 2 << 0); | |
366 | break; | |
367 | case DCLK_VOP1: | |
368 | rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, | |
369 | (lcdc_div - 1) << 8 | 2 << 6); | |
370 | break; | |
371 | } | |
372 | ||
373 | return 0; | |
374 | } | |
3dbfe5ae SG |
375 | |
376 | static u32 rockchip_clk_gcd(u32 a, u32 b) | |
377 | { | |
378 | while (b != 0) { | |
379 | int r = b; | |
380 | ||
381 | b = a % b; | |
382 | a = r; | |
383 | } | |
384 | return a; | |
385 | } | |
386 | ||
387 | static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate) | |
388 | { | |
389 | unsigned long long rate; | |
390 | uint val; | |
391 | int n, d; | |
392 | ||
393 | val = readl(&cru->cru_clksel_con[8]); | |
394 | n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT; | |
395 | d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT; | |
396 | ||
397 | rate = (unsigned long long)gclk_rate * n; | |
398 | do_div(rate, d); | |
399 | ||
400 | return (ulong)rate; | |
401 | } | |
402 | ||
403 | static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate, | |
404 | uint freq) | |
405 | { | |
406 | int n, d; | |
407 | int v; | |
408 | ||
409 | /* set frac divider */ | |
410 | v = rockchip_clk_gcd(gclk_rate, freq); | |
411 | n = gclk_rate / v; | |
412 | d = freq / v; | |
413 | assert(freq == gclk_rate / n * d); | |
414 | writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT, | |
415 | &cru->cru_clksel_con[8]); | |
416 | ||
417 | return rockchip_i2s_get_clk(cru, gclk_rate); | |
418 | } | |
d3cb46aa | 419 | #endif /* CONFIG_SPL_BUILD */ |
830a6081 | 420 | |
99c15650 SG |
421 | static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) |
422 | { | |
423 | u32 aclk_div; | |
424 | u32 hclk_div; | |
425 | u32 pclk_div; | |
426 | ||
427 | /* pll enter slow-mode */ | |
428 | rk_clrsetreg(&cru->cru_mode_con, | |
b223c1ae | 429 | GPLL_MODE_MASK | CPLL_MODE_MASK, |
99c15650 SG |
430 | GPLL_MODE_SLOW << GPLL_MODE_SHIFT | |
431 | CPLL_MODE_SLOW << CPLL_MODE_SHIFT); | |
432 | ||
433 | /* init pll */ | |
434 | rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); | |
435 | rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); | |
436 | ||
437 | /* waiting for pll lock */ | |
438 | while ((readl(&grf->soc_status[1]) & | |
439 | (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != | |
440 | (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) | |
441 | udelay(1); | |
442 | ||
443 | /* | |
444 | * pd_bus clock pll source selection and | |
445 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. | |
446 | */ | |
447 | aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; | |
448 | assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); | |
449 | hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; | |
450 | assert((hclk_div + 1) * PD_BUS_HCLK_HZ == | |
451 | PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); | |
452 | ||
453 | pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; | |
454 | assert((pclk_div + 1) * PD_BUS_PCLK_HZ == | |
455 | PD_BUS_ACLK_HZ && pclk_div < 0x7); | |
456 | ||
457 | rk_clrsetreg(&cru->cru_clksel_con[1], | |
b223c1ae SG |
458 | PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | |
459 | PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, | |
99c15650 SG |
460 | pclk_div << PD_BUS_PCLK_DIV_SHIFT | |
461 | hclk_div << PD_BUS_HCLK_DIV_SHIFT | | |
462 | aclk_div << PD_BUS_ACLK_DIV0_SHIFT | | |
463 | 0 << 0); | |
464 | ||
465 | /* | |
466 | * peri clock pll source selection and | |
467 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. | |
468 | */ | |
469 | aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; | |
470 | assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); | |
471 | ||
abd0128e | 472 | hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); |
99c15650 SG |
473 | assert((1 << hclk_div) * PERI_HCLK_HZ == |
474 | PERI_ACLK_HZ && (hclk_div < 0x4)); | |
475 | ||
abd0128e | 476 | pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); |
99c15650 SG |
477 | assert((1 << pclk_div) * PERI_PCLK_HZ == |
478 | PERI_ACLK_HZ && (pclk_div < 0x4)); | |
479 | ||
480 | rk_clrsetreg(&cru->cru_clksel_con[10], | |
b223c1ae SG |
481 | PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | |
482 | PERI_ACLK_DIV_MASK, | |
c87c129f | 483 | PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | |
99c15650 SG |
484 | pclk_div << PERI_PCLK_DIV_SHIFT | |
485 | hclk_div << PERI_HCLK_DIV_SHIFT | | |
486 | aclk_div << PERI_ACLK_DIV_SHIFT); | |
487 | ||
488 | /* PLL enter normal-mode */ | |
489 | rk_clrsetreg(&cru->cru_mode_con, | |
b223c1ae | 490 | GPLL_MODE_MASK | CPLL_MODE_MASK, |
009741fb SG |
491 | GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | |
492 | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); | |
99c15650 | 493 | } |
99c15650 | 494 | |
b339b5db | 495 | void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) |
dae594f2 SG |
496 | { |
497 | /* pll enter slow-mode */ | |
b223c1ae | 498 | rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, |
dae594f2 SG |
499 | APLL_MODE_SLOW << APLL_MODE_SHIFT); |
500 | ||
501 | rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); | |
502 | ||
503 | /* waiting for pll lock */ | |
504 | while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) | |
505 | udelay(1); | |
506 | ||
507 | /* | |
508 | * core clock pll source selection and | |
509 | * set up dependent divisors for MPAXI/M0AXI and ARM clocks. | |
510 | * core clock select apll, apll clk = 1800MHz | |
511 | * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz | |
512 | */ | |
513 | rk_clrsetreg(&cru->cru_clksel_con[0], | |
b223c1ae SG |
514 | CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | |
515 | M0_DIV_MASK, | |
dae594f2 SG |
516 | 0 << A17_DIV_SHIFT | |
517 | 3 << MP_DIV_SHIFT | | |
518 | 1 << M0_DIV_SHIFT); | |
519 | ||
520 | /* | |
521 | * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. | |
522 | * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz | |
523 | */ | |
524 | rk_clrsetreg(&cru->cru_clksel_con[37], | |
b223c1ae SG |
525 | CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | |
526 | PCLK_CORE_DBG_DIV_MASK, | |
dae594f2 SG |
527 | 1 << CLK_L2RAM_DIV_SHIFT | |
528 | 3 << ATCLK_CORE_DIV_CON_SHIFT | | |
529 | 3 << PCLK_CORE_DBG_DIV_SHIFT); | |
530 | ||
531 | /* PLL enter normal-mode */ | |
b223c1ae | 532 | rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, |
dae594f2 SG |
533 | APLL_MODE_NORMAL << APLL_MODE_SHIFT); |
534 | } | |
535 | ||
99c15650 SG |
536 | /* Get pll rate by id */ |
537 | static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, | |
538 | enum rk_clk_id clk_id) | |
539 | { | |
540 | uint32_t nr, no, nf; | |
541 | uint32_t con; | |
542 | int pll_id = rk_pll_id(clk_id); | |
543 | struct rk3288_pll *pll = &cru->pll[pll_id]; | |
544 | static u8 clk_shift[CLK_COUNT] = { | |
009741fb SG |
545 | 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, |
546 | GPLL_MODE_SHIFT, NPLL_MODE_SHIFT | |
99c15650 SG |
547 | }; |
548 | uint shift; | |
549 | ||
550 | con = readl(&cru->cru_mode_con); | |
551 | shift = clk_shift[clk_id]; | |
b223c1ae | 552 | switch ((con >> shift) & CRU_MODE_MASK) { |
009741fb | 553 | case APLL_MODE_SLOW: |
99c15650 | 554 | return OSC_HZ; |
009741fb | 555 | case APLL_MODE_NORMAL: |
99c15650 SG |
556 | /* normal mode */ |
557 | con = readl(&pll->con0); | |
b223c1ae SG |
558 | no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; |
559 | nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; | |
99c15650 | 560 | con = readl(&pll->con1); |
b223c1ae | 561 | nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; |
99c15650 SG |
562 | |
563 | return (24 * nf / (nr * no)) * 1000000; | |
009741fb | 564 | case APLL_MODE_DEEP: |
99c15650 SG |
565 | default: |
566 | return 32768; | |
567 | } | |
568 | } | |
569 | ||
542635a0 | 570 | static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, |
898d6439 | 571 | int periph) |
99c15650 SG |
572 | { |
573 | uint src_rate; | |
574 | uint div, mux; | |
575 | u32 con; | |
576 | ||
577 | switch (periph) { | |
898d6439 | 578 | case HCLK_EMMC: |
45112271 | 579 | case SCLK_EMMC: |
99c15650 | 580 | con = readl(&cru->cru_clksel_con[12]); |
b223c1ae SG |
581 | mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; |
582 | div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; | |
99c15650 | 583 | break; |
898d6439 | 584 | case HCLK_SDMMC: |
45112271 | 585 | case SCLK_SDMMC: |
898d6439 | 586 | con = readl(&cru->cru_clksel_con[11]); |
b223c1ae SG |
587 | mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; |
588 | div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; | |
99c15650 | 589 | break; |
898d6439 | 590 | case HCLK_SDIO0: |
45112271 | 591 | case SCLK_SDIO0: |
99c15650 | 592 | con = readl(&cru->cru_clksel_con[12]); |
b223c1ae SG |
593 | mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; |
594 | div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; | |
99c15650 SG |
595 | break; |
596 | default: | |
597 | return -EINVAL; | |
598 | } | |
599 | ||
542635a0 | 600 | src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; |
99c15650 SG |
601 | return DIV_TO_RATE(src_rate, div); |
602 | } | |
603 | ||
542635a0 | 604 | static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, |
898d6439 | 605 | int periph, uint freq) |
99c15650 SG |
606 | { |
607 | int src_clk_div; | |
608 | int mux; | |
609 | ||
542635a0 | 610 | debug("%s: gclk_rate=%u\n", __func__, gclk_rate); |
3a94d75d KY |
611 | /* mmc clock default div 2 internal, need provide double in cru */ |
612 | src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); | |
99c15650 SG |
613 | |
614 | if (src_clk_div > 0x3f) { | |
3a94d75d | 615 | src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); |
217273cd | 616 | assert(src_clk_div < 0x40); |
99c15650 SG |
617 | mux = EMMC_PLL_SELECT_24MHZ; |
618 | assert((int)EMMC_PLL_SELECT_24MHZ == | |
619 | (int)MMC0_PLL_SELECT_24MHZ); | |
620 | } else { | |
621 | mux = EMMC_PLL_SELECT_GENERAL; | |
622 | assert((int)EMMC_PLL_SELECT_GENERAL == | |
623 | (int)MMC0_PLL_SELECT_GENERAL); | |
624 | } | |
625 | switch (periph) { | |
898d6439 | 626 | case HCLK_EMMC: |
45112271 | 627 | case SCLK_EMMC: |
99c15650 | 628 | rk_clrsetreg(&cru->cru_clksel_con[12], |
b223c1ae | 629 | EMMC_PLL_MASK | EMMC_DIV_MASK, |
99c15650 SG |
630 | mux << EMMC_PLL_SHIFT | |
631 | (src_clk_div - 1) << EMMC_DIV_SHIFT); | |
632 | break; | |
898d6439 | 633 | case HCLK_SDMMC: |
45112271 | 634 | case SCLK_SDMMC: |
99c15650 | 635 | rk_clrsetreg(&cru->cru_clksel_con[11], |
b223c1ae | 636 | MMC0_PLL_MASK | MMC0_DIV_MASK, |
99c15650 SG |
637 | mux << MMC0_PLL_SHIFT | |
638 | (src_clk_div - 1) << MMC0_DIV_SHIFT); | |
639 | break; | |
898d6439 | 640 | case HCLK_SDIO0: |
45112271 | 641 | case SCLK_SDIO0: |
99c15650 | 642 | rk_clrsetreg(&cru->cru_clksel_con[12], |
b223c1ae | 643 | SDIO0_PLL_MASK | SDIO0_DIV_MASK, |
99c15650 SG |
644 | mux << SDIO0_PLL_SHIFT | |
645 | (src_clk_div - 1) << SDIO0_DIV_SHIFT); | |
646 | break; | |
647 | default: | |
648 | return -EINVAL; | |
649 | } | |
650 | ||
542635a0 | 651 | return rockchip_mmc_get_clk(cru, gclk_rate, periph); |
99c15650 SG |
652 | } |
653 | ||
542635a0 | 654 | static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, |
898d6439 | 655 | int periph) |
99c15650 SG |
656 | { |
657 | uint div, mux; | |
658 | u32 con; | |
659 | ||
660 | switch (periph) { | |
898d6439 | 661 | case SCLK_SPI0: |
99c15650 | 662 | con = readl(&cru->cru_clksel_con[25]); |
b223c1ae SG |
663 | mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; |
664 | div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; | |
99c15650 | 665 | break; |
898d6439 | 666 | case SCLK_SPI1: |
99c15650 | 667 | con = readl(&cru->cru_clksel_con[25]); |
b223c1ae SG |
668 | mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; |
669 | div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; | |
99c15650 | 670 | break; |
898d6439 | 671 | case SCLK_SPI2: |
99c15650 | 672 | con = readl(&cru->cru_clksel_con[39]); |
b223c1ae SG |
673 | mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; |
674 | div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; | |
99c15650 SG |
675 | break; |
676 | default: | |
677 | return -EINVAL; | |
678 | } | |
679 | assert(mux == SPI0_PLL_SELECT_GENERAL); | |
680 | ||
542635a0 | 681 | return DIV_TO_RATE(gclk_rate, div); |
99c15650 SG |
682 | } |
683 | ||
542635a0 | 684 | static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, |
898d6439 | 685 | int periph, uint freq) |
99c15650 SG |
686 | { |
687 | int src_clk_div; | |
688 | ||
542635a0 | 689 | debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); |
217273cd KY |
690 | src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; |
691 | assert(src_clk_div < 128); | |
99c15650 | 692 | switch (periph) { |
898d6439 | 693 | case SCLK_SPI0: |
99c15650 | 694 | rk_clrsetreg(&cru->cru_clksel_con[25], |
b223c1ae | 695 | SPI0_PLL_MASK | SPI0_DIV_MASK, |
99c15650 SG |
696 | SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | |
697 | src_clk_div << SPI0_DIV_SHIFT); | |
698 | break; | |
898d6439 | 699 | case SCLK_SPI1: |
99c15650 | 700 | rk_clrsetreg(&cru->cru_clksel_con[25], |
b223c1ae | 701 | SPI1_PLL_MASK | SPI1_DIV_MASK, |
99c15650 SG |
702 | SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | |
703 | src_clk_div << SPI1_DIV_SHIFT); | |
704 | break; | |
898d6439 | 705 | case SCLK_SPI2: |
99c15650 | 706 | rk_clrsetreg(&cru->cru_clksel_con[39], |
b223c1ae | 707 | SPI2_PLL_MASK | SPI2_DIV_MASK, |
99c15650 SG |
708 | SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | |
709 | src_clk_div << SPI2_DIV_SHIFT); | |
710 | break; | |
711 | default: | |
712 | return -EINVAL; | |
713 | } | |
714 | ||
542635a0 | 715 | return rockchip_spi_get_clk(cru, gclk_rate, periph); |
99c15650 SG |
716 | } |
717 | ||
ef4cf5ae DW |
718 | static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) |
719 | { | |
720 | u32 div, val; | |
721 | ||
722 | val = readl(&cru->cru_clksel_con[24]); | |
723 | div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, | |
724 | CLK_SARADC_DIV_CON_WIDTH); | |
725 | ||
726 | return DIV_TO_RATE(OSC_HZ, div); | |
727 | } | |
728 | ||
729 | static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) | |
730 | { | |
731 | int src_clk_div; | |
732 | ||
733 | src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; | |
734 | assert(src_clk_div < 128); | |
735 | ||
736 | rk_clrsetreg(&cru->cru_clksel_con[24], | |
737 | CLK_SARADC_DIV_CON_MASK, | |
738 | src_clk_div << CLK_SARADC_DIV_CON_SHIFT); | |
739 | ||
740 | return rockchip_saradc_get_clk(cru); | |
741 | } | |
742 | ||
135aa950 | 743 | static ulong rk3288_clk_get_rate(struct clk *clk) |
4f43673e | 744 | { |
135aa950 | 745 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); |
4f43673e | 746 | ulong new_rate, gclk_rate; |
4f43673e | 747 | |
135aa950 SW |
748 | gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); |
749 | switch (clk->id) { | |
750 | case 0 ... 63: | |
751 | new_rate = rkclk_pll_get_rate(priv->cru, clk->id); | |
752 | break; | |
4f43673e | 753 | case HCLK_EMMC: |
342999f9 | 754 | case HCLK_SDMMC: |
4f43673e | 755 | case HCLK_SDIO0: |
45112271 XZ |
756 | case SCLK_EMMC: |
757 | case SCLK_SDMMC: | |
758 | case SCLK_SDIO0: | |
135aa950 | 759 | new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); |
4f43673e SG |
760 | break; |
761 | case SCLK_SPI0: | |
762 | case SCLK_SPI1: | |
763 | case SCLK_SPI2: | |
135aa950 | 764 | new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); |
4f43673e SG |
765 | break; |
766 | case PCLK_I2C0: | |
767 | case PCLK_I2C1: | |
768 | case PCLK_I2C2: | |
769 | case PCLK_I2C3: | |
770 | case PCLK_I2C4: | |
771 | case PCLK_I2C5: | |
772 | return gclk_rate; | |
4f0b8efa KY |
773 | case PCLK_PWM: |
774 | return PD_BUS_PCLK_HZ; | |
ef4cf5ae DW |
775 | case SCLK_SARADC: |
776 | new_rate = rockchip_saradc_get_clk(priv->cru); | |
777 | break; | |
4f43673e SG |
778 | default: |
779 | return -ENOENT; | |
780 | } | |
781 | ||
782 | return new_rate; | |
783 | } | |
784 | ||
135aa950 | 785 | static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) |
99c15650 | 786 | { |
135aa950 | 787 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); |
830a6081 | 788 | struct rk3288_cru *cru = priv->cru; |
898d6439 | 789 | ulong new_rate, gclk_rate; |
898d6439 | 790 | |
135aa950 SW |
791 | gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); |
792 | switch (clk->id) { | |
3a8a42d9 SG |
793 | case PLL_APLL: |
794 | /* We only support a fixed rate here */ | |
795 | if (rate != 1800000000) | |
796 | return -EINVAL; | |
797 | rk3288_clk_configure_cpu(priv->cru, priv->grf); | |
798 | new_rate = rate; | |
799 | break; | |
135aa950 SW |
800 | case CLK_DDR: |
801 | new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); | |
802 | break; | |
898d6439 SG |
803 | case HCLK_EMMC: |
804 | case HCLK_SDMMC: | |
805 | case HCLK_SDIO0: | |
45112271 XZ |
806 | case SCLK_EMMC: |
807 | case SCLK_SDMMC: | |
808 | case SCLK_SDIO0: | |
135aa950 | 809 | new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); |
99c15650 | 810 | break; |
898d6439 SG |
811 | case SCLK_SPI0: |
812 | case SCLK_SPI1: | |
813 | case SCLK_SPI2: | |
135aa950 | 814 | new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); |
99c15650 | 815 | break; |
830a6081 | 816 | #ifndef CONFIG_SPL_BUILD |
3dbfe5ae SG |
817 | case SCLK_I2S0: |
818 | new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate); | |
819 | break; | |
0aefc0b0 | 820 | case SCLK_MAC: |
01c60eaf | 821 | new_rate = rockchip_mac_set_clk(priv->cru, rate); |
0aefc0b0 | 822 | break; |
830a6081 SG |
823 | case DCLK_VOP0: |
824 | case DCLK_VOP1: | |
135aa950 | 825 | new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); |
830a6081 SG |
826 | break; |
827 | case SCLK_EDP_24M: | |
828 | /* clk_edp_24M source: 24M */ | |
829 | rk_setreg(&cru->cru_clksel_con[28], 1 << 15); | |
830 | ||
831 | /* rst edp */ | |
832 | rk_setreg(&cru->cru_clksel_con[6], 1 << 15); | |
833 | udelay(1); | |
834 | rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); | |
835 | new_rate = rate; | |
836 | break; | |
837 | case ACLK_VOP0: | |
838 | case ACLK_VOP1: { | |
839 | u32 div; | |
840 | ||
841 | /* vop aclk source clk: cpll */ | |
842 | div = CPLL_HZ / rate; | |
843 | assert((div - 1 < 64) && (div * rate == CPLL_HZ)); | |
844 | ||
135aa950 | 845 | switch (clk->id) { |
830a6081 SG |
846 | case ACLK_VOP0: |
847 | rk_clrsetreg(&cru->cru_clksel_con[31], | |
848 | 3 << 6 | 0x1f << 0, | |
849 | 0 << 6 | (div - 1) << 0); | |
850 | break; | |
851 | case ACLK_VOP1: | |
852 | rk_clrsetreg(&cru->cru_clksel_con[31], | |
853 | 3 << 14 | 0x1f << 8, | |
854 | 0 << 14 | (div - 1) << 8); | |
855 | break; | |
856 | } | |
857 | new_rate = rate; | |
858 | break; | |
859 | } | |
860 | case PCLK_HDMI_CTRL: | |
861 | /* enable pclk hdmi ctrl */ | |
862 | rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); | |
863 | ||
864 | /* software reset hdmi */ | |
865 | rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); | |
866 | udelay(1); | |
867 | rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); | |
868 | new_rate = rate; | |
869 | break; | |
870 | #endif | |
ef4cf5ae DW |
871 | case SCLK_SARADC: |
872 | new_rate = rockchip_saradc_set_clk(priv->cru, rate); | |
873 | break; | |
01c60eaf DW |
874 | case PLL_GPLL: |
875 | case PLL_CPLL: | |
876 | case PLL_NPLL: | |
877 | case ACLK_CPU: | |
878 | case HCLK_CPU: | |
879 | case PCLK_CPU: | |
880 | case ACLK_PERI: | |
881 | case HCLK_PERI: | |
882 | case PCLK_PERI: | |
883 | case SCLK_UART0: | |
884 | return 0; | |
99c15650 SG |
885 | default: |
886 | return -ENOENT; | |
887 | } | |
888 | ||
889 | return new_rate; | |
890 | } | |
891 | ||
75b381aa | 892 | static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) |
01c60eaf DW |
893 | { |
894 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); | |
895 | struct rk3288_cru *cru = priv->cru; | |
896 | const char *clock_output_name; | |
897 | int ret; | |
898 | ||
899 | /* | |
900 | * If the requested parent is in the same clock-controller and | |
901 | * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal | |
902 | * clock. | |
903 | */ | |
904 | if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { | |
905 | debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); | |
906 | rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); | |
907 | return 0; | |
908 | } | |
909 | ||
910 | /* | |
911 | * Otherwise, we need to check the clock-output-names of the | |
912 | * requested parent to see if the requested id is "ext_gmac". | |
913 | */ | |
914 | ret = dev_read_string_index(parent->dev, "clock-output-names", | |
915 | parent->id, &clock_output_name); | |
916 | if (ret < 0) | |
917 | return -ENODATA; | |
918 | ||
919 | /* If this is "ext_gmac", switch to the external clock input */ | |
920 | if (!strcmp(clock_output_name, "ext_gmac")) { | |
921 | debug("%s: switching GMAC to external clock\n", __func__); | |
922 | rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, | |
923 | RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); | |
924 | return 0; | |
925 | } | |
926 | ||
927 | return -EINVAL; | |
928 | } | |
929 | ||
75b381aa | 930 | static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent) |
01c60eaf DW |
931 | { |
932 | switch (clk->id) { | |
933 | case SCLK_MAC: | |
934 | return rk3288_gmac_set_parent(clk, parent); | |
935 | case SCLK_USBPHY480M_SRC: | |
936 | return 0; | |
937 | } | |
938 | ||
939 | debug("%s: unsupported clk %ld\n", __func__, clk->id); | |
940 | return -ENOENT; | |
941 | } | |
942 | ||
b0ba1e7e WE |
943 | static int rk3288_clk_enable(struct clk *clk) |
944 | { | |
945 | switch (clk->id) { | |
946 | case HCLK_USBHOST0: | |
947 | case HCLK_HSIC: | |
948 | return 0; | |
ed1030e1 JG |
949 | |
950 | case SCLK_MAC: | |
951 | case SCLK_MAC_RX: | |
952 | case SCLK_MAC_TX: | |
953 | case SCLK_MACREF: | |
954 | case SCLK_MACREF_OUT: | |
955 | case ACLK_GMAC: | |
956 | case PCLK_GMAC: | |
957 | /* Required to successfully probe the Designware GMAC driver */ | |
958 | return 0; | |
b0ba1e7e WE |
959 | } |
960 | ||
961 | debug("%s: unsupported clk %ld\n", __func__, clk->id); | |
962 | return -ENOENT; | |
963 | } | |
964 | ||
99c15650 SG |
965 | static struct clk_ops rk3288_clk_ops = { |
966 | .get_rate = rk3288_clk_get_rate, | |
967 | .set_rate = rk3288_clk_set_rate, | |
75b381aa | 968 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
01c60eaf | 969 | .set_parent = rk3288_clk_set_parent, |
75b381aa | 970 | #endif |
b0ba1e7e | 971 | .enable = rk3288_clk_enable, |
99c15650 SG |
972 | }; |
973 | ||
08fd82cf | 974 | static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) |
99c15650 | 975 | { |
2d143bd6 | 976 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
99c15650 SG |
977 | struct rk3288_clk_priv *priv = dev_get_priv(dev); |
978 | ||
995cde1f | 979 | priv->cru = dev_read_addr_ptr(dev); |
2d143bd6 | 980 | #endif |
08fd82cf SG |
981 | |
982 | return 0; | |
983 | } | |
984 | ||
985 | static int rk3288_clk_probe(struct udevice *dev) | |
986 | { | |
987 | struct rk3288_clk_priv *priv = dev_get_priv(dev); | |
d3cb46aa | 988 | bool init_clocks = false; |
08fd82cf | 989 | |
99c15650 | 990 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
08fd82cf SG |
991 | if (IS_ERR(priv->grf)) |
992 | return PTR_ERR(priv->grf); | |
99c15650 | 993 | #ifdef CONFIG_SPL_BUILD |
2d143bd6 SG |
994 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
995 | struct rk3288_clk_plat *plat = dev_get_platdata(dev); | |
996 | ||
997 | priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); | |
998 | #endif | |
d3cb46aa | 999 | init_clocks = true; |
99c15650 | 1000 | #endif |
d3cb46aa SG |
1001 | if (!(gd->flags & GD_FLG_RELOC)) { |
1002 | u32 reg; | |
1003 | ||
1004 | /* | |
1005 | * Init clocks in U-Boot proper if the NPLL is runnning. This | |
1006 | * indicates that a previous boot loader set up the clocks, so | |
1007 | * we need to redo it. U-Boot's SPL does not set this clock. | |
1008 | */ | |
1009 | reg = readl(&priv->cru->cru_mode_con); | |
1010 | if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == | |
1011 | NPLL_MODE_NORMAL) | |
1012 | init_clocks = true; | |
1013 | } | |
1014 | ||
1015 | if (init_clocks) | |
1016 | rkclk_init(priv->cru, priv->grf); | |
99c15650 SG |
1017 | |
1018 | return 0; | |
1019 | } | |
1020 | ||
99c15650 SG |
1021 | static int rk3288_clk_bind(struct udevice *dev) |
1022 | { | |
135aa950 | 1023 | int ret; |
f24e36da KY |
1024 | struct udevice *sys_child; |
1025 | struct sysreset_reg *priv; | |
99c15650 SG |
1026 | |
1027 | /* The reset driver does not have a device node, so bind it here */ | |
f24e36da KY |
1028 | ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", |
1029 | &sys_child); | |
1030 | if (ret) { | |
1031 | debug("Warning: No sysreset driver: ret=%d\n", ret); | |
1032 | } else { | |
1033 | priv = malloc(sizeof(struct sysreset_reg)); | |
1034 | priv->glb_srst_fst_value = offsetof(struct rk3288_cru, | |
1035 | cru_glb_srst_fst_value); | |
1036 | priv->glb_srst_snd_value = offsetof(struct rk3288_cru, | |
1037 | cru_glb_srst_snd_value); | |
1038 | sys_child->priv = priv; | |
1039 | } | |
99c15650 | 1040 | |
538f67c3 EZ |
1041 | #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) |
1042 | ret = offsetof(struct rk3288_cru, cru_softrst_con[0]); | |
1043 | ret = rockchip_reset_bind(dev, ret, 12); | |
1044 | if (ret) | |
1045 | debug("Warning: software reset driver bind faile\n"); | |
1046 | #endif | |
1047 | ||
99c15650 SG |
1048 | return 0; |
1049 | } | |
1050 | ||
1051 | static const struct udevice_id rk3288_clk_ids[] = { | |
1052 | { .compatible = "rockchip,rk3288-cru" }, | |
1053 | { } | |
1054 | }; | |
1055 | ||
2d143bd6 SG |
1056 | U_BOOT_DRIVER(rockchip_rk3288_cru) = { |
1057 | .name = "rockchip_rk3288_cru", | |
99c15650 SG |
1058 | .id = UCLASS_CLK, |
1059 | .of_match = rk3288_clk_ids, | |
1060 | .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), | |
2d143bd6 | 1061 | .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), |
99c15650 SG |
1062 | .ops = &rk3288_clk_ops, |
1063 | .bind = rk3288_clk_bind, | |
08fd82cf | 1064 | .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata, |
99c15650 SG |
1065 | .probe = rk3288_clk_probe, |
1066 | }; |