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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
99c15650 SG |
2 | /* |
3 | * (C) Copyright 2015 Google, Inc | |
99c15650 SG |
4 | */ |
5 | ||
6 | #include <common.h> | |
ef4cf5ae | 7 | #include <bitfield.h> |
135aa950 | 8 | #include <clk-uclass.h> |
3dbfe5ae | 9 | #include <div64.h> |
99c15650 | 10 | #include <dm.h> |
2d143bd6 | 11 | #include <dt-structs.h> |
99c15650 | 12 | #include <errno.h> |
f7ae49fc | 13 | #include <log.h> |
336d4615 | 14 | #include <malloc.h> |
2d143bd6 | 15 | #include <mapmem.h> |
99c15650 SG |
16 | #include <syscon.h> |
17 | #include <asm/io.h> | |
15f09a1a | 18 | #include <asm/arch-rockchip/clock.h> |
b52a199e | 19 | #include <asm/arch-rockchip/cru.h> |
15f09a1a KY |
20 | #include <asm/arch-rockchip/grf_rk3288.h> |
21 | #include <asm/arch-rockchip/hardware.h> | |
898d6439 | 22 | #include <dt-bindings/clock/rk3288-cru.h> |
64b7faa7 | 23 | #include <dm/device-internal.h> |
99c15650 | 24 | #include <dm/lists.h> |
64b7faa7 | 25 | #include <dm/uclass-internal.h> |
61b29b82 | 26 | #include <linux/err.h> |
abd0128e | 27 | #include <linux/log2.h> |
99c15650 SG |
28 | |
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
2d143bd6 SG |
31 | struct rk3288_clk_plat { |
32 | #if CONFIG_IS_ENABLED(OF_PLATDATA) | |
33 | struct dtd_rockchip_rk3288_cru dtd; | |
34 | #endif | |
35 | }; | |
36 | ||
99c15650 SG |
37 | struct pll_div { |
38 | u32 nr; | |
39 | u32 nf; | |
40 | u32 no; | |
41 | }; | |
42 | ||
43 | enum { | |
44 | VCO_MAX_HZ = 2200U * 1000000, | |
45 | VCO_MIN_HZ = 440 * 1000000, | |
46 | OUTPUT_MAX_HZ = 2200U * 1000000, | |
47 | OUTPUT_MIN_HZ = 27500000, | |
48 | FREF_MAX_HZ = 2200U * 1000000, | |
c3f03ffb | 49 | FREF_MIN_HZ = 269 * 1000, |
99c15650 SG |
50 | }; |
51 | ||
52 | enum { | |
53 | /* PLL CON0 */ | |
54 | PLL_OD_MASK = 0x0f, | |
55 | ||
56 | /* PLL CON1 */ | |
57 | PLL_NF_MASK = 0x1fff, | |
58 | ||
59 | /* PLL CON2 */ | |
60 | PLL_BWADJ_MASK = 0x0fff, | |
61 | ||
62 | /* PLL CON3 */ | |
63 | PLL_RESET_SHIFT = 5, | |
64 | ||
dae594f2 | 65 | /* CLKSEL0 */ |
dae594f2 | 66 | CORE_SEL_PLL_SHIFT = 15, |
b223c1ae | 67 | CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, |
dae594f2 | 68 | A17_DIV_SHIFT = 8, |
b223c1ae | 69 | A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, |
dae594f2 | 70 | MP_DIV_SHIFT = 4, |
b223c1ae | 71 | MP_DIV_MASK = 0xf << MP_DIV_SHIFT, |
dae594f2 | 72 | M0_DIV_SHIFT = 0, |
b223c1ae | 73 | M0_DIV_MASK = 0xf << M0_DIV_SHIFT, |
dae594f2 | 74 | |
99c15650 SG |
75 | /* CLKSEL1: pd bus clk pll sel: codec or general */ |
76 | PD_BUS_SEL_PLL_MASK = 15, | |
77 | PD_BUS_SEL_CPLL = 0, | |
78 | PD_BUS_SEL_GPLL, | |
79 | ||
80 | /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ | |
81 | PD_BUS_PCLK_DIV_SHIFT = 12, | |
b223c1ae | 82 | PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, |
99c15650 SG |
83 | |
84 | /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ | |
85 | PD_BUS_HCLK_DIV_SHIFT = 8, | |
b223c1ae | 86 | PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, |
99c15650 SG |
87 | |
88 | /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ | |
89 | PD_BUS_ACLK_DIV0_SHIFT = 3, | |
b223c1ae | 90 | PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, |
99c15650 | 91 | PD_BUS_ACLK_DIV1_SHIFT = 0, |
b223c1ae | 92 | PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, |
99c15650 SG |
93 | |
94 | /* | |
95 | * CLKSEL10 | |
96 | * peripheral bus pclk div: | |
97 | * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 | |
98 | */ | |
c87c129f | 99 | PERI_SEL_PLL_SHIFT = 15, |
b223c1ae | 100 | PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, |
c87c129f SG |
101 | PERI_SEL_CPLL = 0, |
102 | PERI_SEL_GPLL, | |
103 | ||
99c15650 | 104 | PERI_PCLK_DIV_SHIFT = 12, |
b223c1ae | 105 | PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, |
99c15650 SG |
106 | |
107 | /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ | |
108 | PERI_HCLK_DIV_SHIFT = 8, | |
b223c1ae | 109 | PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, |
99c15650 SG |
110 | |
111 | /* | |
112 | * peripheral bus aclk div: | |
113 | * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) | |
114 | */ | |
115 | PERI_ACLK_DIV_SHIFT = 0, | |
b223c1ae | 116 | PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, |
99c15650 | 117 | |
ef4cf5ae DW |
118 | /* |
119 | * CLKSEL24 | |
120 | * saradc_div_con: | |
121 | * clk_saradc=24MHz/(saradc_div_con+1) | |
122 | */ | |
123 | CLK_SARADC_DIV_CON_SHIFT = 8, | |
124 | CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), | |
125 | CLK_SARADC_DIV_CON_WIDTH = 8, | |
126 | ||
99c15650 SG |
127 | SOCSTS_DPLL_LOCK = 1 << 5, |
128 | SOCSTS_APLL_LOCK = 1 << 6, | |
129 | SOCSTS_CPLL_LOCK = 1 << 7, | |
130 | SOCSTS_GPLL_LOCK = 1 << 8, | |
131 | SOCSTS_NPLL_LOCK = 1 << 9, | |
132 | }; | |
133 | ||
99c15650 SG |
134 | #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) |
135 | ||
136 | #define PLL_DIVISORS(hz, _nr, _no) {\ | |
137 | .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ | |
138 | _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ | |
139 | (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ | |
140 | "divisors on line " __stringify(__LINE__)); | |
141 | ||
142 | /* Keep divisors as low as possible to reduce jitter and power usage */ | |
143 | static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); | |
144 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); | |
145 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); | |
146 | ||
b52a199e | 147 | static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id, |
99c15650 SG |
148 | const struct pll_div *div) |
149 | { | |
150 | int pll_id = rk_pll_id(clk_id); | |
151 | struct rk3288_pll *pll = &cru->pll[pll_id]; | |
152 | /* All PLLs have same VCO and output frequency range restrictions. */ | |
153 | uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; | |
154 | uint output_hz = vco_hz / div->no; | |
155 | ||
c87c129f SG |
156 | debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", |
157 | (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); | |
99c15650 SG |
158 | assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && |
159 | output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && | |
160 | (div->no == 1 || !(div->no % 2))); | |
161 | ||
c87c129f | 162 | /* enter reset */ |
99c15650 SG |
163 | rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
164 | ||
b223c1ae | 165 | rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, |
99c15650 SG |
166 | ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); |
167 | rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); | |
168 | rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); | |
169 | ||
170 | udelay(10); | |
171 | ||
c87c129f | 172 | /* return from reset */ |
99c15650 SG |
173 | rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
b52a199e | 178 | static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf, |
99c15650 SG |
179 | unsigned int hz) |
180 | { | |
181 | static const struct pll_div dpll_cfg[] = { | |
182 | {.nf = 25, .nr = 2, .no = 1}, | |
183 | {.nf = 400, .nr = 9, .no = 2}, | |
184 | {.nf = 500, .nr = 9, .no = 2}, | |
185 | {.nf = 100, .nr = 3, .no = 1}, | |
186 | }; | |
187 | int cfg; | |
188 | ||
99c15650 SG |
189 | switch (hz) { |
190 | case 300000000: | |
191 | cfg = 0; | |
192 | break; | |
193 | case 533000000: /* actually 533.3P MHz */ | |
194 | cfg = 1; | |
195 | break; | |
196 | case 666000000: /* actually 666.6P MHz */ | |
197 | cfg = 2; | |
198 | break; | |
199 | case 800000000: | |
200 | cfg = 3; | |
201 | break; | |
202 | default: | |
c87c129f | 203 | debug("Unsupported SDRAM frequency"); |
99c15650 SG |
204 | return -EINVAL; |
205 | } | |
206 | ||
207 | /* pll enter slow-mode */ | |
b223c1ae | 208 | rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, |
99c15650 SG |
209 | DPLL_MODE_SLOW << DPLL_MODE_SHIFT); |
210 | ||
211 | rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); | |
212 | ||
213 | /* wait for pll lock */ | |
214 | while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) | |
215 | udelay(1); | |
216 | ||
217 | /* PLL enter normal-mode */ | |
b223c1ae | 218 | rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, |
009741fb | 219 | DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); |
99c15650 SG |
220 | |
221 | return 0; | |
222 | } | |
223 | ||
830a6081 SG |
224 | #ifndef CONFIG_SPL_BUILD |
225 | #define VCO_MAX_KHZ 2200000 | |
226 | #define VCO_MIN_KHZ 440000 | |
227 | #define FREF_MAX_KHZ 2200000 | |
228 | #define FREF_MIN_KHZ 269 | |
229 | ||
230 | static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) | |
231 | { | |
232 | uint ref_khz = OSC_HZ / 1000, nr, nf = 0; | |
233 | uint fref_khz; | |
234 | uint diff_khz, best_diff_khz; | |
235 | const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4; | |
236 | uint vco_khz; | |
237 | uint no = 1; | |
238 | uint freq_khz = freq_hz / 1000; | |
239 | ||
240 | if (!freq_hz) { | |
241 | printf("%s: the frequency can not be 0 Hz\n", __func__); | |
242 | return -EINVAL; | |
243 | } | |
244 | ||
245 | no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); | |
246 | if (ext_div) { | |
247 | *ext_div = DIV_ROUND_UP(no, max_no); | |
248 | no = DIV_ROUND_UP(no, *ext_div); | |
249 | } | |
250 | ||
251 | /* only even divisors (and 1) are supported */ | |
252 | if (no > 1) | |
253 | no = DIV_ROUND_UP(no, 2) * 2; | |
254 | ||
255 | vco_khz = freq_khz * no; | |
256 | if (ext_div) | |
257 | vco_khz *= *ext_div; | |
258 | ||
259 | if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { | |
260 | printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n", | |
261 | __func__, freq_hz); | |
262 | return -1; | |
263 | } | |
264 | ||
265 | div->no = no; | |
266 | ||
267 | best_diff_khz = vco_khz; | |
268 | for (nr = 1; nr < max_nr && best_diff_khz; nr++) { | |
269 | fref_khz = ref_khz / nr; | |
270 | if (fref_khz < FREF_MIN_KHZ) | |
271 | break; | |
272 | if (fref_khz > FREF_MAX_KHZ) | |
273 | continue; | |
274 | ||
275 | nf = vco_khz / fref_khz; | |
276 | if (nf >= max_nf) | |
277 | continue; | |
278 | diff_khz = vco_khz - nf * fref_khz; | |
279 | if (nf + 1 < max_nf && diff_khz > fref_khz / 2) { | |
280 | nf++; | |
281 | diff_khz = fref_khz - diff_khz; | |
282 | } | |
283 | ||
284 | if (diff_khz >= best_diff_khz) | |
285 | continue; | |
286 | ||
287 | best_diff_khz = diff_khz; | |
288 | div->nr = nr; | |
289 | div->nf = nf; | |
290 | } | |
291 | ||
292 | if (best_diff_khz > 4 * 1000) { | |
293 | printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n", | |
294 | __func__, freq_hz, best_diff_khz * 1000); | |
295 | return -EINVAL; | |
296 | } | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
b52a199e | 301 | static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq) |
0aefc0b0 | 302 | { |
01c60eaf | 303 | ulong ret; |
0aefc0b0 | 304 | |
01c60eaf DW |
305 | /* |
306 | * The gmac clock can be derived either from an external clock | |
307 | * or can be generated from internally by a divider from SCLK_MAC. | |
308 | */ | |
309 | if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { | |
310 | /* An external clock will always generate the right rate... */ | |
311 | ret = freq; | |
312 | } else { | |
313 | u32 con = readl(&cru->cru_clksel_con[21]); | |
314 | ulong pll_rate; | |
315 | u8 div; | |
316 | ||
317 | if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == | |
318 | EMAC_PLL_SELECT_GENERAL) | |
319 | pll_rate = GPLL_HZ; | |
320 | else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == | |
321 | EMAC_PLL_SELECT_CODEC) | |
322 | pll_rate = CPLL_HZ; | |
323 | else | |
324 | pll_rate = NPLL_HZ; | |
325 | ||
326 | div = DIV_ROUND_UP(pll_rate, freq) - 1; | |
327 | if (div <= 0x1f) | |
328 | rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, | |
329 | div << MAC_DIV_CON_SHIFT); | |
330 | else | |
331 | debug("Unsupported div for gmac:%d\n", div); | |
332 | ||
333 | return DIV_TO_RATE(pll_rate, div); | |
334 | } | |
335 | ||
336 | return ret; | |
0aefc0b0 SS |
337 | } |
338 | ||
b52a199e | 339 | static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf, |
830a6081 SG |
340 | int periph, unsigned int rate_hz) |
341 | { | |
342 | struct pll_div npll_config = {0}; | |
343 | u32 lcdc_div; | |
344 | int ret; | |
345 | ||
346 | ret = pll_para_config(rate_hz, &npll_config, &lcdc_div); | |
347 | if (ret) | |
348 | return ret; | |
349 | ||
b223c1ae | 350 | rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, |
830a6081 SG |
351 | NPLL_MODE_SLOW << NPLL_MODE_SHIFT); |
352 | rkclk_set_pll(cru, CLK_NEW, &npll_config); | |
353 | ||
354 | /* waiting for pll lock */ | |
355 | while (1) { | |
356 | if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK) | |
357 | break; | |
358 | udelay(1); | |
359 | } | |
360 | ||
b223c1ae | 361 | rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, |
830a6081 SG |
362 | NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); |
363 | ||
364 | /* vop dclk source clk: npll,dclk_div: 1 */ | |
365 | switch (periph) { | |
366 | case DCLK_VOP0: | |
367 | rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, | |
368 | (lcdc_div - 1) << 8 | 2 << 0); | |
369 | break; | |
370 | case DCLK_VOP1: | |
371 | rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, | |
372 | (lcdc_div - 1) << 8 | 2 << 6); | |
373 | break; | |
374 | } | |
375 | ||
376 | return 0; | |
377 | } | |
3dbfe5ae SG |
378 | |
379 | static u32 rockchip_clk_gcd(u32 a, u32 b) | |
380 | { | |
381 | while (b != 0) { | |
382 | int r = b; | |
383 | ||
384 | b = a % b; | |
385 | a = r; | |
386 | } | |
387 | return a; | |
388 | } | |
389 | ||
b52a199e | 390 | static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate) |
3dbfe5ae SG |
391 | { |
392 | unsigned long long rate; | |
393 | uint val; | |
394 | int n, d; | |
395 | ||
396 | val = readl(&cru->cru_clksel_con[8]); | |
397 | n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT; | |
398 | d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT; | |
399 | ||
400 | rate = (unsigned long long)gclk_rate * n; | |
401 | do_div(rate, d); | |
402 | ||
403 | return (ulong)rate; | |
404 | } | |
405 | ||
b52a199e | 406 | static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate, |
3dbfe5ae SG |
407 | uint freq) |
408 | { | |
409 | int n, d; | |
410 | int v; | |
411 | ||
412 | /* set frac divider */ | |
413 | v = rockchip_clk_gcd(gclk_rate, freq); | |
414 | n = gclk_rate / v; | |
415 | d = freq / v; | |
416 | assert(freq == gclk_rate / n * d); | |
417 | writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT, | |
418 | &cru->cru_clksel_con[8]); | |
419 | ||
420 | return rockchip_i2s_get_clk(cru, gclk_rate); | |
421 | } | |
d3cb46aa | 422 | #endif /* CONFIG_SPL_BUILD */ |
830a6081 | 423 | |
b52a199e | 424 | static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf) |
99c15650 SG |
425 | { |
426 | u32 aclk_div; | |
427 | u32 hclk_div; | |
428 | u32 pclk_div; | |
429 | ||
430 | /* pll enter slow-mode */ | |
431 | rk_clrsetreg(&cru->cru_mode_con, | |
b223c1ae | 432 | GPLL_MODE_MASK | CPLL_MODE_MASK, |
99c15650 SG |
433 | GPLL_MODE_SLOW << GPLL_MODE_SHIFT | |
434 | CPLL_MODE_SLOW << CPLL_MODE_SHIFT); | |
435 | ||
436 | /* init pll */ | |
437 | rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); | |
438 | rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); | |
439 | ||
440 | /* waiting for pll lock */ | |
441 | while ((readl(&grf->soc_status[1]) & | |
442 | (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != | |
443 | (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) | |
444 | udelay(1); | |
445 | ||
446 | /* | |
447 | * pd_bus clock pll source selection and | |
448 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. | |
449 | */ | |
450 | aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; | |
451 | assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); | |
452 | hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; | |
453 | assert((hclk_div + 1) * PD_BUS_HCLK_HZ == | |
454 | PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); | |
455 | ||
456 | pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; | |
457 | assert((pclk_div + 1) * PD_BUS_PCLK_HZ == | |
458 | PD_BUS_ACLK_HZ && pclk_div < 0x7); | |
459 | ||
460 | rk_clrsetreg(&cru->cru_clksel_con[1], | |
b223c1ae SG |
461 | PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | |
462 | PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, | |
99c15650 SG |
463 | pclk_div << PD_BUS_PCLK_DIV_SHIFT | |
464 | hclk_div << PD_BUS_HCLK_DIV_SHIFT | | |
465 | aclk_div << PD_BUS_ACLK_DIV0_SHIFT | | |
466 | 0 << 0); | |
467 | ||
468 | /* | |
469 | * peri clock pll source selection and | |
470 | * set up dependent divisors for PCLK/HCLK and ACLK clocks. | |
471 | */ | |
472 | aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; | |
473 | assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); | |
474 | ||
abd0128e | 475 | hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); |
99c15650 SG |
476 | assert((1 << hclk_div) * PERI_HCLK_HZ == |
477 | PERI_ACLK_HZ && (hclk_div < 0x4)); | |
478 | ||
abd0128e | 479 | pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); |
99c15650 SG |
480 | assert((1 << pclk_div) * PERI_PCLK_HZ == |
481 | PERI_ACLK_HZ && (pclk_div < 0x4)); | |
482 | ||
483 | rk_clrsetreg(&cru->cru_clksel_con[10], | |
b223c1ae SG |
484 | PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | |
485 | PERI_ACLK_DIV_MASK, | |
c87c129f | 486 | PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | |
99c15650 SG |
487 | pclk_div << PERI_PCLK_DIV_SHIFT | |
488 | hclk_div << PERI_HCLK_DIV_SHIFT | | |
489 | aclk_div << PERI_ACLK_DIV_SHIFT); | |
490 | ||
491 | /* PLL enter normal-mode */ | |
492 | rk_clrsetreg(&cru->cru_mode_con, | |
b223c1ae | 493 | GPLL_MODE_MASK | CPLL_MODE_MASK, |
009741fb SG |
494 | GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | |
495 | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); | |
99c15650 | 496 | } |
99c15650 | 497 | |
b52a199e | 498 | void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf) |
dae594f2 SG |
499 | { |
500 | /* pll enter slow-mode */ | |
b223c1ae | 501 | rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, |
dae594f2 SG |
502 | APLL_MODE_SLOW << APLL_MODE_SHIFT); |
503 | ||
504 | rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); | |
505 | ||
506 | /* waiting for pll lock */ | |
507 | while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) | |
508 | udelay(1); | |
509 | ||
510 | /* | |
511 | * core clock pll source selection and | |
512 | * set up dependent divisors for MPAXI/M0AXI and ARM clocks. | |
513 | * core clock select apll, apll clk = 1800MHz | |
514 | * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz | |
515 | */ | |
516 | rk_clrsetreg(&cru->cru_clksel_con[0], | |
b223c1ae SG |
517 | CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | |
518 | M0_DIV_MASK, | |
dae594f2 SG |
519 | 0 << A17_DIV_SHIFT | |
520 | 3 << MP_DIV_SHIFT | | |
521 | 1 << M0_DIV_SHIFT); | |
522 | ||
523 | /* | |
524 | * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. | |
525 | * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz | |
526 | */ | |
527 | rk_clrsetreg(&cru->cru_clksel_con[37], | |
b223c1ae SG |
528 | CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | |
529 | PCLK_CORE_DBG_DIV_MASK, | |
dae594f2 SG |
530 | 1 << CLK_L2RAM_DIV_SHIFT | |
531 | 3 << ATCLK_CORE_DIV_CON_SHIFT | | |
532 | 3 << PCLK_CORE_DBG_DIV_SHIFT); | |
533 | ||
534 | /* PLL enter normal-mode */ | |
b223c1ae | 535 | rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, |
dae594f2 SG |
536 | APLL_MODE_NORMAL << APLL_MODE_SHIFT); |
537 | } | |
538 | ||
99c15650 | 539 | /* Get pll rate by id */ |
b52a199e | 540 | static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru, |
99c15650 SG |
541 | enum rk_clk_id clk_id) |
542 | { | |
543 | uint32_t nr, no, nf; | |
544 | uint32_t con; | |
545 | int pll_id = rk_pll_id(clk_id); | |
546 | struct rk3288_pll *pll = &cru->pll[pll_id]; | |
547 | static u8 clk_shift[CLK_COUNT] = { | |
009741fb SG |
548 | 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, |
549 | GPLL_MODE_SHIFT, NPLL_MODE_SHIFT | |
99c15650 SG |
550 | }; |
551 | uint shift; | |
552 | ||
553 | con = readl(&cru->cru_mode_con); | |
554 | shift = clk_shift[clk_id]; | |
b223c1ae | 555 | switch ((con >> shift) & CRU_MODE_MASK) { |
009741fb | 556 | case APLL_MODE_SLOW: |
99c15650 | 557 | return OSC_HZ; |
009741fb | 558 | case APLL_MODE_NORMAL: |
99c15650 SG |
559 | /* normal mode */ |
560 | con = readl(&pll->con0); | |
b223c1ae SG |
561 | no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; |
562 | nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; | |
99c15650 | 563 | con = readl(&pll->con1); |
b223c1ae | 564 | nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; |
99c15650 SG |
565 | |
566 | return (24 * nf / (nr * no)) * 1000000; | |
009741fb | 567 | case APLL_MODE_DEEP: |
99c15650 SG |
568 | default: |
569 | return 32768; | |
570 | } | |
571 | } | |
572 | ||
b52a199e | 573 | static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate, |
898d6439 | 574 | int periph) |
99c15650 SG |
575 | { |
576 | uint src_rate; | |
577 | uint div, mux; | |
578 | u32 con; | |
579 | ||
580 | switch (periph) { | |
898d6439 | 581 | case HCLK_EMMC: |
45112271 | 582 | case SCLK_EMMC: |
99c15650 | 583 | con = readl(&cru->cru_clksel_con[12]); |
b223c1ae SG |
584 | mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; |
585 | div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; | |
99c15650 | 586 | break; |
898d6439 | 587 | case HCLK_SDMMC: |
45112271 | 588 | case SCLK_SDMMC: |
898d6439 | 589 | con = readl(&cru->cru_clksel_con[11]); |
b223c1ae SG |
590 | mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; |
591 | div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; | |
99c15650 | 592 | break; |
898d6439 | 593 | case HCLK_SDIO0: |
45112271 | 594 | case SCLK_SDIO0: |
99c15650 | 595 | con = readl(&cru->cru_clksel_con[12]); |
b223c1ae SG |
596 | mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; |
597 | div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; | |
99c15650 SG |
598 | break; |
599 | default: | |
600 | return -EINVAL; | |
601 | } | |
602 | ||
542635a0 | 603 | src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; |
99c15650 SG |
604 | return DIV_TO_RATE(src_rate, div); |
605 | } | |
606 | ||
b52a199e | 607 | static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate, |
898d6439 | 608 | int periph, uint freq) |
99c15650 SG |
609 | { |
610 | int src_clk_div; | |
611 | int mux; | |
612 | ||
542635a0 | 613 | debug("%s: gclk_rate=%u\n", __func__, gclk_rate); |
3a94d75d KY |
614 | /* mmc clock default div 2 internal, need provide double in cru */ |
615 | src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); | |
99c15650 SG |
616 | |
617 | if (src_clk_div > 0x3f) { | |
3a94d75d | 618 | src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); |
217273cd | 619 | assert(src_clk_div < 0x40); |
99c15650 SG |
620 | mux = EMMC_PLL_SELECT_24MHZ; |
621 | assert((int)EMMC_PLL_SELECT_24MHZ == | |
622 | (int)MMC0_PLL_SELECT_24MHZ); | |
623 | } else { | |
624 | mux = EMMC_PLL_SELECT_GENERAL; | |
625 | assert((int)EMMC_PLL_SELECT_GENERAL == | |
626 | (int)MMC0_PLL_SELECT_GENERAL); | |
627 | } | |
628 | switch (periph) { | |
898d6439 | 629 | case HCLK_EMMC: |
45112271 | 630 | case SCLK_EMMC: |
99c15650 | 631 | rk_clrsetreg(&cru->cru_clksel_con[12], |
b223c1ae | 632 | EMMC_PLL_MASK | EMMC_DIV_MASK, |
99c15650 SG |
633 | mux << EMMC_PLL_SHIFT | |
634 | (src_clk_div - 1) << EMMC_DIV_SHIFT); | |
635 | break; | |
898d6439 | 636 | case HCLK_SDMMC: |
45112271 | 637 | case SCLK_SDMMC: |
99c15650 | 638 | rk_clrsetreg(&cru->cru_clksel_con[11], |
b223c1ae | 639 | MMC0_PLL_MASK | MMC0_DIV_MASK, |
99c15650 SG |
640 | mux << MMC0_PLL_SHIFT | |
641 | (src_clk_div - 1) << MMC0_DIV_SHIFT); | |
642 | break; | |
898d6439 | 643 | case HCLK_SDIO0: |
45112271 | 644 | case SCLK_SDIO0: |
99c15650 | 645 | rk_clrsetreg(&cru->cru_clksel_con[12], |
b223c1ae | 646 | SDIO0_PLL_MASK | SDIO0_DIV_MASK, |
99c15650 SG |
647 | mux << SDIO0_PLL_SHIFT | |
648 | (src_clk_div - 1) << SDIO0_DIV_SHIFT); | |
649 | break; | |
650 | default: | |
651 | return -EINVAL; | |
652 | } | |
653 | ||
542635a0 | 654 | return rockchip_mmc_get_clk(cru, gclk_rate, periph); |
99c15650 SG |
655 | } |
656 | ||
b52a199e | 657 | static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate, |
898d6439 | 658 | int periph) |
99c15650 SG |
659 | { |
660 | uint div, mux; | |
661 | u32 con; | |
662 | ||
663 | switch (periph) { | |
898d6439 | 664 | case SCLK_SPI0: |
99c15650 | 665 | con = readl(&cru->cru_clksel_con[25]); |
b223c1ae SG |
666 | mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; |
667 | div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; | |
99c15650 | 668 | break; |
898d6439 | 669 | case SCLK_SPI1: |
99c15650 | 670 | con = readl(&cru->cru_clksel_con[25]); |
b223c1ae SG |
671 | mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; |
672 | div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; | |
99c15650 | 673 | break; |
898d6439 | 674 | case SCLK_SPI2: |
99c15650 | 675 | con = readl(&cru->cru_clksel_con[39]); |
b223c1ae SG |
676 | mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; |
677 | div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; | |
99c15650 SG |
678 | break; |
679 | default: | |
680 | return -EINVAL; | |
681 | } | |
682 | assert(mux == SPI0_PLL_SELECT_GENERAL); | |
683 | ||
542635a0 | 684 | return DIV_TO_RATE(gclk_rate, div); |
99c15650 SG |
685 | } |
686 | ||
b52a199e | 687 | static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate, |
898d6439 | 688 | int periph, uint freq) |
99c15650 SG |
689 | { |
690 | int src_clk_div; | |
691 | ||
542635a0 | 692 | debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); |
217273cd KY |
693 | src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; |
694 | assert(src_clk_div < 128); | |
99c15650 | 695 | switch (periph) { |
898d6439 | 696 | case SCLK_SPI0: |
99c15650 | 697 | rk_clrsetreg(&cru->cru_clksel_con[25], |
b223c1ae | 698 | SPI0_PLL_MASK | SPI0_DIV_MASK, |
99c15650 SG |
699 | SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | |
700 | src_clk_div << SPI0_DIV_SHIFT); | |
701 | break; | |
898d6439 | 702 | case SCLK_SPI1: |
99c15650 | 703 | rk_clrsetreg(&cru->cru_clksel_con[25], |
b223c1ae | 704 | SPI1_PLL_MASK | SPI1_DIV_MASK, |
99c15650 SG |
705 | SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | |
706 | src_clk_div << SPI1_DIV_SHIFT); | |
707 | break; | |
898d6439 | 708 | case SCLK_SPI2: |
99c15650 | 709 | rk_clrsetreg(&cru->cru_clksel_con[39], |
b223c1ae | 710 | SPI2_PLL_MASK | SPI2_DIV_MASK, |
99c15650 SG |
711 | SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | |
712 | src_clk_div << SPI2_DIV_SHIFT); | |
713 | break; | |
714 | default: | |
715 | return -EINVAL; | |
716 | } | |
717 | ||
542635a0 | 718 | return rockchip_spi_get_clk(cru, gclk_rate, periph); |
99c15650 SG |
719 | } |
720 | ||
b52a199e | 721 | static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru) |
ef4cf5ae DW |
722 | { |
723 | u32 div, val; | |
724 | ||
725 | val = readl(&cru->cru_clksel_con[24]); | |
726 | div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, | |
727 | CLK_SARADC_DIV_CON_WIDTH); | |
728 | ||
729 | return DIV_TO_RATE(OSC_HZ, div); | |
730 | } | |
731 | ||
b52a199e | 732 | static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz) |
ef4cf5ae DW |
733 | { |
734 | int src_clk_div; | |
735 | ||
736 | src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; | |
737 | assert(src_clk_div < 128); | |
738 | ||
739 | rk_clrsetreg(&cru->cru_clksel_con[24], | |
740 | CLK_SARADC_DIV_CON_MASK, | |
741 | src_clk_div << CLK_SARADC_DIV_CON_SHIFT); | |
742 | ||
743 | return rockchip_saradc_get_clk(cru); | |
744 | } | |
745 | ||
135aa950 | 746 | static ulong rk3288_clk_get_rate(struct clk *clk) |
4f43673e | 747 | { |
135aa950 | 748 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); |
4f43673e | 749 | ulong new_rate, gclk_rate; |
4f43673e | 750 | |
135aa950 SW |
751 | gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); |
752 | switch (clk->id) { | |
753 | case 0 ... 63: | |
754 | new_rate = rkclk_pll_get_rate(priv->cru, clk->id); | |
755 | break; | |
4f43673e | 756 | case HCLK_EMMC: |
342999f9 | 757 | case HCLK_SDMMC: |
4f43673e | 758 | case HCLK_SDIO0: |
45112271 XZ |
759 | case SCLK_EMMC: |
760 | case SCLK_SDMMC: | |
761 | case SCLK_SDIO0: | |
135aa950 | 762 | new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); |
4f43673e SG |
763 | break; |
764 | case SCLK_SPI0: | |
765 | case SCLK_SPI1: | |
766 | case SCLK_SPI2: | |
135aa950 | 767 | new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); |
4f43673e SG |
768 | break; |
769 | case PCLK_I2C0: | |
770 | case PCLK_I2C1: | |
771 | case PCLK_I2C2: | |
772 | case PCLK_I2C3: | |
773 | case PCLK_I2C4: | |
774 | case PCLK_I2C5: | |
775 | return gclk_rate; | |
4f0b8efa KY |
776 | case PCLK_PWM: |
777 | return PD_BUS_PCLK_HZ; | |
ef4cf5ae DW |
778 | case SCLK_SARADC: |
779 | new_rate = rockchip_saradc_get_clk(priv->cru); | |
780 | break; | |
4f43673e SG |
781 | default: |
782 | return -ENOENT; | |
783 | } | |
784 | ||
785 | return new_rate; | |
786 | } | |
787 | ||
135aa950 | 788 | static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) |
99c15650 | 789 | { |
135aa950 | 790 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); |
b52a199e | 791 | struct rockchip_cru *cru = priv->cru; |
898d6439 | 792 | ulong new_rate, gclk_rate; |
898d6439 | 793 | |
135aa950 SW |
794 | gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); |
795 | switch (clk->id) { | |
3a8a42d9 SG |
796 | case PLL_APLL: |
797 | /* We only support a fixed rate here */ | |
798 | if (rate != 1800000000) | |
799 | return -EINVAL; | |
800 | rk3288_clk_configure_cpu(priv->cru, priv->grf); | |
801 | new_rate = rate; | |
802 | break; | |
135aa950 SW |
803 | case CLK_DDR: |
804 | new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); | |
805 | break; | |
898d6439 SG |
806 | case HCLK_EMMC: |
807 | case HCLK_SDMMC: | |
808 | case HCLK_SDIO0: | |
45112271 XZ |
809 | case SCLK_EMMC: |
810 | case SCLK_SDMMC: | |
811 | case SCLK_SDIO0: | |
135aa950 | 812 | new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); |
99c15650 | 813 | break; |
898d6439 SG |
814 | case SCLK_SPI0: |
815 | case SCLK_SPI1: | |
816 | case SCLK_SPI2: | |
135aa950 | 817 | new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); |
99c15650 | 818 | break; |
830a6081 | 819 | #ifndef CONFIG_SPL_BUILD |
3dbfe5ae SG |
820 | case SCLK_I2S0: |
821 | new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate); | |
822 | break; | |
0aefc0b0 | 823 | case SCLK_MAC: |
01c60eaf | 824 | new_rate = rockchip_mac_set_clk(priv->cru, rate); |
0aefc0b0 | 825 | break; |
830a6081 SG |
826 | case DCLK_VOP0: |
827 | case DCLK_VOP1: | |
135aa950 | 828 | new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); |
830a6081 SG |
829 | break; |
830 | case SCLK_EDP_24M: | |
831 | /* clk_edp_24M source: 24M */ | |
832 | rk_setreg(&cru->cru_clksel_con[28], 1 << 15); | |
833 | ||
834 | /* rst edp */ | |
835 | rk_setreg(&cru->cru_clksel_con[6], 1 << 15); | |
836 | udelay(1); | |
837 | rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); | |
838 | new_rate = rate; | |
839 | break; | |
840 | case ACLK_VOP0: | |
841 | case ACLK_VOP1: { | |
842 | u32 div; | |
843 | ||
844 | /* vop aclk source clk: cpll */ | |
845 | div = CPLL_HZ / rate; | |
846 | assert((div - 1 < 64) && (div * rate == CPLL_HZ)); | |
847 | ||
135aa950 | 848 | switch (clk->id) { |
830a6081 SG |
849 | case ACLK_VOP0: |
850 | rk_clrsetreg(&cru->cru_clksel_con[31], | |
851 | 3 << 6 | 0x1f << 0, | |
852 | 0 << 6 | (div - 1) << 0); | |
853 | break; | |
854 | case ACLK_VOP1: | |
855 | rk_clrsetreg(&cru->cru_clksel_con[31], | |
856 | 3 << 14 | 0x1f << 8, | |
857 | 0 << 14 | (div - 1) << 8); | |
858 | break; | |
859 | } | |
860 | new_rate = rate; | |
861 | break; | |
862 | } | |
863 | case PCLK_HDMI_CTRL: | |
864 | /* enable pclk hdmi ctrl */ | |
865 | rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); | |
866 | ||
867 | /* software reset hdmi */ | |
868 | rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); | |
869 | udelay(1); | |
870 | rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); | |
871 | new_rate = rate; | |
872 | break; | |
873 | #endif | |
ef4cf5ae DW |
874 | case SCLK_SARADC: |
875 | new_rate = rockchip_saradc_set_clk(priv->cru, rate); | |
876 | break; | |
01c60eaf DW |
877 | case PLL_GPLL: |
878 | case PLL_CPLL: | |
879 | case PLL_NPLL: | |
880 | case ACLK_CPU: | |
881 | case HCLK_CPU: | |
882 | case PCLK_CPU: | |
883 | case ACLK_PERI: | |
884 | case HCLK_PERI: | |
885 | case PCLK_PERI: | |
886 | case SCLK_UART0: | |
887 | return 0; | |
99c15650 SG |
888 | default: |
889 | return -ENOENT; | |
890 | } | |
891 | ||
892 | return new_rate; | |
893 | } | |
894 | ||
75b381aa | 895 | static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) |
01c60eaf DW |
896 | { |
897 | struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); | |
b52a199e | 898 | struct rockchip_cru *cru = priv->cru; |
01c60eaf DW |
899 | const char *clock_output_name; |
900 | int ret; | |
901 | ||
902 | /* | |
903 | * If the requested parent is in the same clock-controller and | |
904 | * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal | |
905 | * clock. | |
906 | */ | |
907 | if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { | |
908 | debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); | |
909 | rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); | |
910 | return 0; | |
911 | } | |
912 | ||
913 | /* | |
914 | * Otherwise, we need to check the clock-output-names of the | |
915 | * requested parent to see if the requested id is "ext_gmac". | |
916 | */ | |
917 | ret = dev_read_string_index(parent->dev, "clock-output-names", | |
918 | parent->id, &clock_output_name); | |
919 | if (ret < 0) | |
920 | return -ENODATA; | |
921 | ||
922 | /* If this is "ext_gmac", switch to the external clock input */ | |
923 | if (!strcmp(clock_output_name, "ext_gmac")) { | |
924 | debug("%s: switching GMAC to external clock\n", __func__); | |
925 | rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, | |
926 | RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); | |
927 | return 0; | |
928 | } | |
929 | ||
930 | return -EINVAL; | |
931 | } | |
932 | ||
75b381aa | 933 | static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent) |
01c60eaf DW |
934 | { |
935 | switch (clk->id) { | |
936 | case SCLK_MAC: | |
937 | return rk3288_gmac_set_parent(clk, parent); | |
938 | case SCLK_USBPHY480M_SRC: | |
939 | return 0; | |
940 | } | |
941 | ||
942 | debug("%s: unsupported clk %ld\n", __func__, clk->id); | |
943 | return -ENOENT; | |
944 | } | |
945 | ||
99c15650 SG |
946 | static struct clk_ops rk3288_clk_ops = { |
947 | .get_rate = rk3288_clk_get_rate, | |
948 | .set_rate = rk3288_clk_set_rate, | |
75b381aa | 949 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
01c60eaf | 950 | .set_parent = rk3288_clk_set_parent, |
75b381aa | 951 | #endif |
99c15650 SG |
952 | }; |
953 | ||
08fd82cf | 954 | static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) |
99c15650 | 955 | { |
2d143bd6 | 956 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
99c15650 SG |
957 | struct rk3288_clk_priv *priv = dev_get_priv(dev); |
958 | ||
995cde1f | 959 | priv->cru = dev_read_addr_ptr(dev); |
2d143bd6 | 960 | #endif |
08fd82cf SG |
961 | |
962 | return 0; | |
963 | } | |
964 | ||
965 | static int rk3288_clk_probe(struct udevice *dev) | |
966 | { | |
967 | struct rk3288_clk_priv *priv = dev_get_priv(dev); | |
d3cb46aa | 968 | bool init_clocks = false; |
08fd82cf | 969 | |
99c15650 | 970 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
08fd82cf SG |
971 | if (IS_ERR(priv->grf)) |
972 | return PTR_ERR(priv->grf); | |
99c15650 | 973 | #ifdef CONFIG_SPL_BUILD |
2d143bd6 SG |
974 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
975 | struct rk3288_clk_plat *plat = dev_get_platdata(dev); | |
976 | ||
977 | priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); | |
978 | #endif | |
d3cb46aa | 979 | init_clocks = true; |
99c15650 | 980 | #endif |
d3cb46aa SG |
981 | if (!(gd->flags & GD_FLG_RELOC)) { |
982 | u32 reg; | |
983 | ||
984 | /* | |
985 | * Init clocks in U-Boot proper if the NPLL is runnning. This | |
986 | * indicates that a previous boot loader set up the clocks, so | |
987 | * we need to redo it. U-Boot's SPL does not set this clock. | |
988 | */ | |
989 | reg = readl(&priv->cru->cru_mode_con); | |
990 | if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == | |
991 | NPLL_MODE_NORMAL) | |
992 | init_clocks = true; | |
993 | } | |
994 | ||
995 | if (init_clocks) | |
996 | rkclk_init(priv->cru, priv->grf); | |
99c15650 SG |
997 | |
998 | return 0; | |
999 | } | |
1000 | ||
99c15650 SG |
1001 | static int rk3288_clk_bind(struct udevice *dev) |
1002 | { | |
135aa950 | 1003 | int ret; |
f24e36da KY |
1004 | struct udevice *sys_child; |
1005 | struct sysreset_reg *priv; | |
99c15650 SG |
1006 | |
1007 | /* The reset driver does not have a device node, so bind it here */ | |
f24e36da KY |
1008 | ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", |
1009 | &sys_child); | |
1010 | if (ret) { | |
1011 | debug("Warning: No sysreset driver: ret=%d\n", ret); | |
1012 | } else { | |
1013 | priv = malloc(sizeof(struct sysreset_reg)); | |
b52a199e | 1014 | priv->glb_srst_fst_value = offsetof(struct rockchip_cru, |
f24e36da | 1015 | cru_glb_srst_fst_value); |
b52a199e | 1016 | priv->glb_srst_snd_value = offsetof(struct rockchip_cru, |
f24e36da KY |
1017 | cru_glb_srst_snd_value); |
1018 | sys_child->priv = priv; | |
1019 | } | |
99c15650 | 1020 | |
a5ada25e | 1021 | #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) |
b52a199e | 1022 | ret = offsetof(struct rockchip_cru, cru_softrst_con[0]); |
538f67c3 EZ |
1023 | ret = rockchip_reset_bind(dev, ret, 12); |
1024 | if (ret) | |
1025 | debug("Warning: software reset driver bind faile\n"); | |
1026 | #endif | |
1027 | ||
99c15650 SG |
1028 | return 0; |
1029 | } | |
1030 | ||
1031 | static const struct udevice_id rk3288_clk_ids[] = { | |
1032 | { .compatible = "rockchip,rk3288-cru" }, | |
1033 | { } | |
1034 | }; | |
1035 | ||
2d143bd6 SG |
1036 | U_BOOT_DRIVER(rockchip_rk3288_cru) = { |
1037 | .name = "rockchip_rk3288_cru", | |
99c15650 SG |
1038 | .id = UCLASS_CLK, |
1039 | .of_match = rk3288_clk_ids, | |
1040 | .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), | |
2d143bd6 | 1041 | .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), |
99c15650 SG |
1042 | .ops = &rk3288_clk_ops, |
1043 | .bind = rk3288_clk_bind, | |
08fd82cf | 1044 | .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata, |
99c15650 SG |
1045 | .probe = rk3288_clk_probe, |
1046 | }; |