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dm: core: Create a new header file for 'compat' features
[thirdparty/u-boot.git] / drivers / clk / rockchip / clk_rk3399.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0
b0b3c865
KY		 2/*
3 * (C) Copyright 2015 Google, Inc
8fa6979b 4 * (C) 2017 Theobroma Systems Design und Consulting GmbH
b0b3c865
KY		 5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
5ae2fd97 10#include <dt-structs.h>
b0b3c865 11#include <errno.h>
336d4615 12#include <malloc.h>
5ae2fd97 13#include <mapmem.h>
b0b3c865 14#include <syscon.h>
364fc731 15#include <bitfield.h>
b0b3c865 16#include <asm/io.h>
15f09a1a 17#include <asm/arch-rockchip/clock.h>
b52a199e 18#include <asm/arch-rockchip/cru.h>
15f09a1a 19#include <asm/arch-rockchip/hardware.h>
b0b3c865
KY		 20#include <dm/lists.h>
21#include <dt-bindings/clock/rk3399-cru.h>
22
5ae2fd97
KY		 23#if CONFIG_IS_ENABLED(OF_PLATDATA)
24struct rk3399_clk_plat {
25 struct dtd_rockchip_rk3399_cru dtd;
5e79f443
KY		 26};
27
5ae2fd97
KY		 28struct rk3399_pmuclk_plat {
29 struct dtd_rockchip_rk3399_pmucru dtd;
30};
31#endif
32
b0b3c865
KY		 33struct pll_div {
34 u32 refdiv;
35 u32 fbdiv;
36 u32 postdiv1;
37 u32 postdiv2;
38 u32 frac;
39};
40
41#define RATE_TO_DIV(input_rate, output_rate) \
dd7dfa21
JT		 42 ((input_rate) / (output_rate) - 1)
43#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
b0b3c865
KY		 44
45#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
46 .refdiv = _refdiv,\
47 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
48 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
49
61dff33b 50#if defined(CONFIG_SPL_BUILD)
b0b3c865
KY		 51static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
52static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
61dff33b 53#else
b0b3c865 54static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
61dff33b 55#endif
b0b3c865 56
dd7dfa21
JT		 57static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
58static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
b0b3c865
KY		 59
60static const struct pll_div *apll_l_cfgs[] = {
61 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
62 [APLL_L_600_MHZ] = &apll_l_600_cfg,
63};
64
dd7dfa21 65static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
af765a49
CM		 66static const struct pll_div *apll_b_cfgs[] = {
67 [APLL_B_600_MHZ] = &apll_b_600_cfg,
68};
69
b0b3c865
KY		 70enum {
71 /* PLL_CON0 */
72 PLL_FBDIV_MASK = 0xfff,
73 PLL_FBDIV_SHIFT = 0,
74
75 /* PLL_CON1 */
76 PLL_POSTDIV2_SHIFT = 12,
77 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
78 PLL_POSTDIV1_SHIFT = 8,
79 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
80 PLL_REFDIV_MASK = 0x3f,
81 PLL_REFDIV_SHIFT = 0,
82
83 /* PLL_CON2 */
84 PLL_LOCK_STATUS_SHIFT = 31,
85 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
86 PLL_FRACDIV_MASK = 0xffffff,
87 PLL_FRACDIV_SHIFT = 0,
88
89 /* PLL_CON3 */
90 PLL_MODE_SHIFT = 8,
91 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
92 PLL_MODE_SLOW = 0,
93 PLL_MODE_NORM,
94 PLL_MODE_DEEP,
95 PLL_DSMPD_SHIFT = 3,
96 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
97 PLL_INTEGER_MODE = 1,
98
99 /* PMUCRU_CLKSEL_CON0 */
100 PMU_PCLK_DIV_CON_MASK = 0x1f,
101 PMU_PCLK_DIV_CON_SHIFT = 0,
102
103 /* PMUCRU_CLKSEL_CON1 */
104 SPI3_PLL_SEL_SHIFT = 7,
105 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
106 SPI3_PLL_SEL_24M = 0,
107 SPI3_PLL_SEL_PPLL = 1,
108 SPI3_DIV_CON_SHIFT = 0x0,
109 SPI3_DIV_CON_MASK = 0x7f,
110
111 /* PMUCRU_CLKSEL_CON2 */
112 I2C_DIV_CON_MASK = 0x7f,
5e79f443
KY		 113 CLK_I2C8_DIV_CON_SHIFT = 8,
114 CLK_I2C0_DIV_CON_SHIFT = 0,
b0b3c865
KY		 115
116 /* PMUCRU_CLKSEL_CON3 */
5e79f443 117 CLK_I2C4_DIV_CON_SHIFT = 0,
b0b3c865
KY		 118
119 /* CLKSEL_CON0 */
120 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
121 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
122 CLK_CORE_L_PLL_SEL_SHIFT = 6,
123 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
124 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
125 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
126 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
127 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
128 CLK_CORE_L_DIV_MASK = 0x1f,
129 CLK_CORE_L_DIV_SHIFT = 0,
130
131 /* CLKSEL_CON1 */
132 PCLK_DBG_L_DIV_SHIFT = 0x8,
133 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
134 ATCLK_CORE_L_DIV_SHIFT = 0,
135 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
136
af765a49
CM		 137 /* CLKSEL_CON2 */
138 ACLKM_CORE_B_DIV_CON_SHIFT = 8,
139 ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
140 CLK_CORE_B_PLL_SEL_SHIFT = 6,
141 CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
142 CLK_CORE_B_PLL_SEL_ALPLL = 0x0,
143 CLK_CORE_B_PLL_SEL_ABPLL = 0x1,
144 CLK_CORE_B_PLL_SEL_DPLL = 0x10,
145 CLK_CORE_B_PLL_SEL_GPLL = 0x11,
146 CLK_CORE_B_DIV_MASK = 0x1f,
147 CLK_CORE_B_DIV_SHIFT = 0,
148
149 /* CLKSEL_CON3 */
150 PCLK_DBG_B_DIV_SHIFT = 0x8,
151 PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT,
152 ATCLK_CORE_B_DIV_SHIFT = 0,
153 ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
154
b0b3c865
KY		 155 /* CLKSEL_CON14 */
156 PCLK_PERIHP_DIV_CON_SHIFT = 12,
157 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
158 HCLK_PERIHP_DIV_CON_SHIFT = 8,
159 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
160 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
161 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
162 ACLK_PERIHP_PLL_SEL_CPLL = 0,
163 ACLK_PERIHP_PLL_SEL_GPLL = 1,
164 ACLK_PERIHP_DIV_CON_SHIFT = 0,
165 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
166
167 /* CLKSEL_CON21 */
168 ACLK_EMMC_PLL_SEL_SHIFT = 7,
169 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
170 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
171 ACLK_EMMC_DIV_CON_SHIFT = 0,
172 ACLK_EMMC_DIV_CON_MASK = 0x1f,
173
174 /* CLKSEL_CON22 */
175 CLK_EMMC_PLL_SHIFT = 8,
176 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
177 CLK_EMMC_PLL_SEL_GPLL = 0x1,
fd4b2dc0 178 CLK_EMMC_PLL_SEL_24M = 0x5,
b0b3c865
KY		 179 CLK_EMMC_DIV_CON_SHIFT = 0,
180 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
181
182 /* CLKSEL_CON23 */
183 PCLK_PERILP0_DIV_CON_SHIFT = 12,
184 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
185 HCLK_PERILP0_DIV_CON_SHIFT = 8,
186 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
187 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
188 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
189 ACLK_PERILP0_PLL_SEL_CPLL = 0,
190 ACLK_PERILP0_PLL_SEL_GPLL = 1,
191 ACLK_PERILP0_DIV_CON_SHIFT = 0,
192 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
193
194 /* CLKSEL_CON25 */
195 PCLK_PERILP1_DIV_CON_SHIFT = 8,
196 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
197 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
198 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
199 HCLK_PERILP1_PLL_SEL_CPLL = 0,
200 HCLK_PERILP1_PLL_SEL_GPLL = 1,
201 HCLK_PERILP1_DIV_CON_SHIFT = 0,
202 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
203
204 /* CLKSEL_CON26 */
205 CLK_SARADC_DIV_CON_SHIFT = 8,
364fc731
DW		 206 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
207 CLK_SARADC_DIV_CON_WIDTH = 8,
b0b3c865
KY		 208
209 /* CLKSEL_CON27 */
210 CLK_TSADC_SEL_X24M = 0x0,
211 CLK_TSADC_SEL_SHIFT = 15,
212 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
213 CLK_TSADC_DIV_CON_SHIFT = 0,
214 CLK_TSADC_DIV_CON_MASK = 0x3ff,
215
216 /* CLKSEL_CON47 & CLKSEL_CON48 */
217 ACLK_VOP_PLL_SEL_SHIFT = 6,
218 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
219 ACLK_VOP_PLL_SEL_CPLL = 0x1,
220 ACLK_VOP_DIV_CON_SHIFT = 0,
221 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
222
223 /* CLKSEL_CON49 & CLKSEL_CON50 */
224 DCLK_VOP_DCLK_SEL_SHIFT = 11,
225 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
226 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
227 DCLK_VOP_PLL_SEL_SHIFT = 8,
228 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
229 DCLK_VOP_PLL_SEL_VPLL = 0,
230 DCLK_VOP_DIV_CON_MASK = 0xff,
231 DCLK_VOP_DIV_CON_SHIFT = 0,
232
233 /* CLKSEL_CON58 */
8fa6979b
PT		 234 CLK_SPI_PLL_SEL_WIDTH = 1,
235 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
236 CLK_SPI_PLL_SEL_CPLL = 0,
237 CLK_SPI_PLL_SEL_GPLL = 1,
238 CLK_SPI_PLL_DIV_CON_WIDTH = 7,
239 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
240
241 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
242 CLK_SPI5_PLL_SEL_SHIFT = 15,
b0b3c865
KY		 243
244 /* CLKSEL_CON59 */
245 CLK_SPI1_PLL_SEL_SHIFT = 15,
246 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
247 CLK_SPI0_PLL_SEL_SHIFT = 7,
248 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
249
250 /* CLKSEL_CON60 */
251 CLK_SPI4_PLL_SEL_SHIFT = 15,
252 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
253 CLK_SPI2_PLL_SEL_SHIFT = 7,
254 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
255
256 /* CLKSEL_CON61 */
257 CLK_I2C_PLL_SEL_MASK = 1,
258 CLK_I2C_PLL_SEL_CPLL = 0,
259 CLK_I2C_PLL_SEL_GPLL = 1,
260 CLK_I2C5_PLL_SEL_SHIFT = 15,
261 CLK_I2C5_DIV_CON_SHIFT = 8,
262 CLK_I2C1_PLL_SEL_SHIFT = 7,
263 CLK_I2C1_DIV_CON_SHIFT = 0,
264
265 /* CLKSEL_CON62 */
266 CLK_I2C6_PLL_SEL_SHIFT = 15,
267 CLK_I2C6_DIV_CON_SHIFT = 8,
268 CLK_I2C2_PLL_SEL_SHIFT = 7,
269 CLK_I2C2_DIV_CON_SHIFT = 0,
270
271 /* CLKSEL_CON63 */
272 CLK_I2C7_PLL_SEL_SHIFT = 15,
273 CLK_I2C7_DIV_CON_SHIFT = 8,
274 CLK_I2C3_PLL_SEL_SHIFT = 7,
275 CLK_I2C3_DIV_CON_SHIFT = 0,
276
277 /* CRU_SOFTRST_CON4 */
278 RESETN_DDR0_REQ_SHIFT = 8,
279 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
280 RESETN_DDRPHY0_REQ_SHIFT = 9,
281 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
282 RESETN_DDR1_REQ_SHIFT = 12,
283 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
284 RESETN_DDRPHY1_REQ_SHIFT = 13,
285 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
286};
287
288#define VCO_MAX_KHZ (3200 * (MHz / KHz))
289#define VCO_MIN_KHZ (800 * (MHz / KHz))
290#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
291#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
292
293/*
294 * the div restructions of pll in integer mode, these are defined in
295 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
296 */
297#define PLL_DIV_MIN 16
298#define PLL_DIV_MAX 3200
299
300/*
301 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
302 * Formulas also embedded within the Fractional PLL Verilog model:
303 * If DSMPD = 1 (DSM is disabled, "integer mode")
304 * FOUTVCO = FREF / REFDIV * FBDIV
305 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
306 * Where:
307 * FOUTVCO = Fractional PLL non-divided output frequency
308 * FOUTPOSTDIV = Fractional PLL divided output frequency
309 * (output of second post divider)
310 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
311 * REFDIV = Fractional PLL input reference clock divider
312 * FBDIV = Integer value programmed into feedback divide
313 *
314 */
315static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
316{
317 /* All 8 PLLs have same VCO and output frequency range restrictions. */
318 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
319 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
320
321 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
322 "postdiv2=%d, vco=%u khz, output=%u khz\n",
323 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
324 div->postdiv2, vco_khz, output_khz);
325 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
326 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
327 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
328
329 /*
330 * When power on or changing PLL setting,
331 * we must force PLL into slow mode to ensure output stable clock.
332 */
333 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
334 PLL_MODE_SLOW << PLL_MODE_SHIFT);
335
336 /* use integer mode */
337 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
338 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
339
340 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
341 div->fbdiv << PLL_FBDIV_SHIFT);
342 rk_clrsetreg(&pll_con[1],
343 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
344 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
345 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
346 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
347 (div->refdiv << PLL_REFDIV_SHIFT));
348
349 /* waiting for pll lock */
350 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
351 udelay(1);
352
353 /* pll enter normal mode */
354 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
355 PLL_MODE_NORM << PLL_MODE_SHIFT);
356}
357
358static int pll_para_config(u32 freq_hz, struct pll_div *div)
359{
360 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
361 u32 postdiv1, postdiv2 = 1;
362 u32 fref_khz;
363 u32 diff_khz, best_diff_khz;
364 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
365 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
366 u32 vco_khz;
367 u32 freq_khz = freq_hz / KHz;
368
369 if (!freq_hz) {
370 printf("%s: the frequency can't be 0 Hz\n", __func__);
371 return -1;
372 }
373
374 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
375 if (postdiv1 > max_postdiv1) {
376 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
377 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
378 }
379
380 vco_khz = freq_khz * postdiv1 * postdiv2;
381
382 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
383 postdiv2 > max_postdiv2) {
384 printf("%s: Cannot find out a supported VCO"
385 " for Frequency (%uHz).\n", __func__, freq_hz);
386 return -1;
387 }
388
389 div->postdiv1 = postdiv1;
390 div->postdiv2 = postdiv2;
391
392 best_diff_khz = vco_khz;
393 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
394 fref_khz = ref_khz / refdiv;
395
396 fbdiv = vco_khz / fref_khz;
dd7dfa21 397 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
b0b3c865
KY		 398 continue;
399 diff_khz = vco_khz - fbdiv * fref_khz;
400 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
401 fbdiv++;
402 diff_khz = fref_khz - diff_khz;
403 }
404
405 if (diff_khz >= best_diff_khz)
406 continue;
407
408 best_diff_khz = diff_khz;
409 div->refdiv = refdiv;
410 div->fbdiv = fbdiv;
411 }
412
dd7dfa21 413 if (best_diff_khz > 4 * (MHz / KHz)) {
b0b3c865
KY		 414 printf("%s: Failed to match output frequency %u, "
415 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
416 best_diff_khz * KHz);
417 return -1;
418 }
419 return 0;
420}
421
b52a199e 422void rk3399_configure_cpu_l(struct rockchip_cru *cru,
af765a49 423 enum apll_l_frequencies apll_l_freq)
b0b3c865
KY		 424{
425 u32 aclkm_div;
426 u32 pclk_dbg_div;
427 u32 atclk_div;
428
af765a49 429 /* Setup cluster L */
b0b3c865
KY		 430 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
431
af765a49
CM		 432 aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
433 assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
b0b3c865
KY		 434 aclkm_div < 0x1f);
435
af765a49
CM		 436 pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
437 assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
b0b3c865
KY		 438 pclk_dbg_div < 0x1f);
439
af765a49
CM		 440 atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
441 assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
b0b3c865
KY		 442 atclk_div < 0x1f);
443
444 rk_clrsetreg(&cru->clksel_con[0],
445 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
446 CLK_CORE_L_DIV_MASK,
447 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
448 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
449 0 << CLK_CORE_L_DIV_SHIFT);
450
451 rk_clrsetreg(&cru->clksel_con[1],
452 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
453 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
454 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
455}
af765a49 456
b52a199e 457void rk3399_configure_cpu_b(struct rockchip_cru *cru,
af765a49
CM		 458 enum apll_b_frequencies apll_b_freq)
459{
460 u32 aclkm_div;
461 u32 pclk_dbg_div;
462 u32 atclk_div;
463
464 /* Setup cluster B */
465 rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
466
467 aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
468 assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
469 aclkm_div < 0x1f);
470
471 pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
472 assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
473 pclk_dbg_div < 0x1f);
474
475 atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
476 assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
477 atclk_div < 0x1f);
478
479 rk_clrsetreg(&cru->clksel_con[2],
480 ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
481 CLK_CORE_B_DIV_MASK,
482 aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
483 CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
484 0 << CLK_CORE_B_DIV_SHIFT);
485
486 rk_clrsetreg(&cru->clksel_con[3],
487 PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
488 pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
489 atclk_div << ATCLK_CORE_B_DIV_SHIFT);
490}
491
b0b3c865 492#define I2C_CLK_REG_MASK(bus) \
dd7dfa21
JT		 493 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
494 CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
b0b3c865
KY		 495
496#define I2C_CLK_REG_VALUE(bus, clk_div) \
dd7dfa21
JT		 497 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
498 CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
b0b3c865
KY		 499
500#define I2C_CLK_DIV_VALUE(con, bus) \
dd7dfa21 501 ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
b0b3c865 502
5e79f443 503#define I2C_PMUCLK_REG_MASK(bus) \
dd7dfa21 504 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
5e79f443
KY		 505
506#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
dd7dfa21 507 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
5e79f443 508
b52a199e 509static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
b0b3c865
KY		 510{
511 u32 div, con;
512
513 switch (clk_id) {
514 case SCLK_I2C1:
515 con = readl(&cru->clksel_con[61]);
516 div = I2C_CLK_DIV_VALUE(con, 1);
517 break;
518 case SCLK_I2C2:
519 con = readl(&cru->clksel_con[62]);
520 div = I2C_CLK_DIV_VALUE(con, 2);
521 break;
522 case SCLK_I2C3:
523 con = readl(&cru->clksel_con[63]);
524 div = I2C_CLK_DIV_VALUE(con, 3);
525 break;
526 case SCLK_I2C5:
527 con = readl(&cru->clksel_con[61]);
528 div = I2C_CLK_DIV_VALUE(con, 5);
529 break;
530 case SCLK_I2C6:
531 con = readl(&cru->clksel_con[62]);
532 div = I2C_CLK_DIV_VALUE(con, 6);
533 break;
534 case SCLK_I2C7:
535 con = readl(&cru->clksel_con[63]);
536 div = I2C_CLK_DIV_VALUE(con, 7);
537 break;
538 default:
539 printf("do not support this i2c bus\n");
540 return -EINVAL;
541 }
542
543 return DIV_TO_RATE(GPLL_HZ, div);
544}
545
b52a199e 546static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
b0b3c865
KY		 547{
548 int src_clk_div;
549
550 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
551 src_clk_div = GPLL_HZ / hz;
552 assert(src_clk_div - 1 < 127);
553
554 switch (clk_id) {
555 case SCLK_I2C1:
556 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
557 I2C_CLK_REG_VALUE(1, src_clk_div));
558 break;
559 case SCLK_I2C2:
560 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
561 I2C_CLK_REG_VALUE(2, src_clk_div));
562 break;
563 case SCLK_I2C3:
564 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
565 I2C_CLK_REG_VALUE(3, src_clk_div));
566 break;
567 case SCLK_I2C5:
568 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
569 I2C_CLK_REG_VALUE(5, src_clk_div));
570 break;
571 case SCLK_I2C6:
572 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
573 I2C_CLK_REG_VALUE(6, src_clk_div));
574 break;
575 case SCLK_I2C7:
576 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
577 I2C_CLK_REG_VALUE(7, src_clk_div));
578 break;
579 default:
580 printf("do not support this i2c bus\n");
581 return -EINVAL;
582 }
583
beb90a53 584 return rk3399_i2c_get_clk(cru, clk_id);
b0b3c865
KY		 585}
586
8fa6979b
PT		 587/*
588 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
589 * to select either CPLL or GPLL as the clock-parent. The location within
590 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
591 */
592
593struct spi_clkreg {
dd7dfa21
JT		 594 u8 reg; /* CLKSEL_CON[reg] register in CRU */
595 u8 div_shift;
596 u8 sel_shift;
8fa6979b
PT		 597};
598
599/*
600 * The entries are numbered relative to their offset from SCLK_SPI0.
601 *
602 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
603 * logic is not supported).
604 */
605static const struct spi_clkreg spi_clkregs[] = {
606 [0] = { .reg = 59,
607 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
608 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
609 [1] = { .reg = 59,
610 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
611 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
612 [2] = { .reg = 60,
613 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
614 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
615 [3] = { .reg = 60,
616 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
617 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
618 [4] = { .reg = 58,
619 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
620 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
621};
622
b52a199e 623static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
8fa6979b
PT		 624{
625 const struct spi_clkreg *spiclk = NULL;
626 u32 div, val;
627
628 switch (clk_id) {
629 case SCLK_SPI0 ... SCLK_SPI5:
630 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
631 break;
632
633 default:
9b643e31 634 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
8fa6979b
PT		 635 return -EINVAL;
636 }
637
638 val = readl(&cru->clksel_con[spiclk->reg]);
a8ee98df
PT		 639 div = bitfield_extract(val, spiclk->div_shift,
640 CLK_SPI_PLL_DIV_CON_WIDTH);
8fa6979b
PT		 641
642 return DIV_TO_RATE(GPLL_HZ, div);
643}
644
b52a199e 645static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
8fa6979b
PT		 646{
647 const struct spi_clkreg *spiclk = NULL;
648 int src_clk_div;
649
217273cd
KY		 650 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
651 assert(src_clk_div < 128);
8fa6979b
PT		 652
653 switch (clk_id) {
654 case SCLK_SPI1 ... SCLK_SPI5:
655 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
656 break;
657
658 default:
9b643e31 659 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
8fa6979b
PT		 660 return -EINVAL;
661 }
662
663 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
664 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
665 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
666 ((src_clk_div << spiclk->div_shift) |
667 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
668
beb90a53 669 return rk3399_spi_get_clk(cru, clk_id);
8fa6979b
PT		 670}
671
b52a199e 672static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
b0b3c865
KY		 673{
674 struct pll_div vpll_config = {0};
dd7dfa21 675 int aclk_vop = 198 * MHz;
b0b3c865
KY		 676 void *aclkreg_addr, *dclkreg_addr;
677 u32 div;
678
679 switch (clk_id) {
680 case DCLK_VOP0:
681 aclkreg_addr = &cru->clksel_con[47];
682 dclkreg_addr = &cru->clksel_con[49];
683 break;
684 case DCLK_VOP1:
685 aclkreg_addr = &cru->clksel_con[48];
686 dclkreg_addr = &cru->clksel_con[50];
687 break;
688 default:
689 return -EINVAL;
690 }
691 /* vop aclk source clk: cpll */
692 div = CPLL_HZ / aclk_vop;
693 assert(div - 1 < 32);
694
695 rk_clrsetreg(aclkreg_addr,
696 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
697 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
698 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
699
700 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
701 if (pll_para_config(hz, &vpll_config))
702 return -1;
703
704 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
705
706 rk_clrsetreg(dclkreg_addr,
dd7dfa21 707 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
b0b3c865
KY		 708 DCLK_VOP_DIV_CON_MASK,
709 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
710 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
711 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
712
713 return hz;
714}
715
b52a199e 716static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
b0b3c865
KY		 717{
718 u32 div, con;
719
720 switch (clk_id) {
998c61ae 721 case HCLK_SDMMC:
b0b3c865
KY		 722 case SCLK_SDMMC:
723 con = readl(&cru->clksel_con[16]);
3a94d75d
KY		 724 /* dwmmc controller have internal div 2 */
725 div = 2;
b0b3c865
KY		 726 break;
727 case SCLK_EMMC:
728 con = readl(&cru->clksel_con[21]);
3a94d75d 729 div = 1;
b0b3c865
KY		 730 break;
731 default:
732 return -EINVAL;
733 }
b0b3c865 734
3a94d75d 735 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
fd4b2dc0
KY		 736 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
737 == CLK_EMMC_PLL_SEL_24M)
3a94d75d 738 return DIV_TO_RATE(OSC_HZ, div);
fd4b2dc0
KY		 739 else
740 return DIV_TO_RATE(GPLL_HZ, div);
b0b3c865
KY		 741}
742
b52a199e 743static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
b0b3c865
KY		 744 ulong clk_id, ulong set_rate)
745{
746 int src_clk_div;
dd7dfa21 747 int aclk_emmc = 198 * MHz;
b0b3c865
KY		 748
749 switch (clk_id) {
998c61ae 750 case HCLK_SDMMC:
b0b3c865 751 case SCLK_SDMMC:
fd4b2dc0 752 /* Select clk_sdmmc source from GPLL by default */
3a94d75d
KY		 753 /* mmc clock defaulg div 2 internal, provide double in cru */
754 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
b0b3c865 755
217273cd 756 if (src_clk_div > 128) {
fd4b2dc0 757 /* use 24MHz source for 400KHz clock */
3a94d75d 758 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
217273cd 759 assert(src_clk_div - 1 < 128);
fd4b2dc0
KY		 760 rk_clrsetreg(&cru->clksel_con[16],
761 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
762 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
763 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
764 } else {
765 rk_clrsetreg(&cru->clksel_con[16],
766 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
767 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
768 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
769 }
b0b3c865
KY		 770 break;
771 case SCLK_EMMC:
772 /* Select aclk_emmc source from GPLL */
dd7dfa21 773 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
217273cd 774 assert(src_clk_div - 1 < 32);
b0b3c865
KY		 775
776 rk_clrsetreg(&cru->clksel_con[21],
777 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
778 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
779 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
780
781 /* Select clk_emmc source from GPLL too */
217273cd
KY		 782 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
783 assert(src_clk_div - 1 < 128);
b0b3c865
KY		 784
785 rk_clrsetreg(&cru->clksel_con[22],
786 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
787 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
788 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
789 break;
790 default:
791 return -EINVAL;
792 }
793 return rk3399_mmc_get_clk(cru, clk_id);
794}
795
b52a199e 796static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
a45f17e8
PT		 797{
798 ulong ret;
799
800 /*
801 * The RGMII CLK can be derived either from an external "clkin"
802 * or can be generated from internally by a divider from SCLK_MAC.
803 */
804 if (readl(&cru->clksel_con[19]) & BIT(4)) {
805 /* An external clock will always generate the right rate... */
806 ret = rate;
807 } else {
808 /*
809 * No platform uses an internal clock to date.
810 * Implement this once it becomes necessary and print an error
811 * if someone tries to use it (while it remains unimplemented).
812 */
813 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
814 ret = 0;
815 }
816
817 return ret;
818}
819
5ae2fd97 820#define PMUSGRF_DDR_RGN_CON16 0xff330040
b52a199e 821static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
5ae2fd97
KY		 822 ulong set_rate)
823{
824 struct pll_div dpll_cfg;
825
826 /* IC ECO bug, need to set this register */
827 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
828
829 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
830 switch (set_rate) {
09565686
JT		 831 case 50 * MHz:
832 dpll_cfg = (struct pll_div)
833 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
834 break;
dd7dfa21 835 case 200 * MHz:
5ae2fd97
KY		 836 dpll_cfg = (struct pll_div)
837 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
838 break;
dd7dfa21 839 case 300 * MHz:
5ae2fd97
KY		 840 dpll_cfg = (struct pll_div)
841 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
842 break;
f556d75a
JT		 843 case 400 * MHz:
844 dpll_cfg = (struct pll_div)
845 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
846 break;
dd7dfa21 847 case 666 * MHz:
5ae2fd97
KY		 848 dpll_cfg = (struct pll_div)
849 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
850 break;
dd7dfa21 851 case 800 * MHz:
5ae2fd97
KY		 852 dpll_cfg = (struct pll_div)
853 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
854 break;
dd7dfa21 855 case 933 * MHz:
5ae2fd97
KY		 856 dpll_cfg = (struct pll_div)
857 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
858 break;
859 default:
9b643e31 860 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
5ae2fd97
KY		 861 }
862 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
863
864 return set_rate;
865}
364fc731 866
b52a199e 867static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
364fc731
DW		 868{
869 u32 div, val;
870
871 val = readl(&cru->clksel_con[26]);
872 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
873 CLK_SARADC_DIV_CON_WIDTH);
874
875 return DIV_TO_RATE(OSC_HZ, div);
876}
877
b52a199e 878static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
364fc731
DW		 879{
880 int src_clk_div;
881
882 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
883 assert(src_clk_div < 128);
884
885 rk_clrsetreg(&cru->clksel_con[26],
886 CLK_SARADC_DIV_CON_MASK,
887 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
888
889 return rk3399_saradc_get_clk(cru);
890}
891
b0b3c865
KY		 892static ulong rk3399_clk_get_rate(struct clk *clk)
893{
894 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
895 ulong rate = 0;
896
897 switch (clk->id) {
898 case 0 ... 63:
899 return 0;
998c61ae 900 case HCLK_SDMMC:
b0b3c865
KY		 901 case SCLK_SDMMC:
902 case SCLK_EMMC:
903 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
904 break;
905 case SCLK_I2C1:
906 case SCLK_I2C2:
907 case SCLK_I2C3:
908 case SCLK_I2C5:
909 case SCLK_I2C6:
910 case SCLK_I2C7:
911 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
912 break;
8fa6979b
PT		 913 case SCLK_SPI0...SCLK_SPI5:
914 rate = rk3399_spi_get_clk(priv->cru, clk->id);
915 break;
916 case SCLK_UART0:
24615436 917 case SCLK_UART1:
8fa6979b 918 case SCLK_UART2:
24615436 919 case SCLK_UART3:
8fa6979b 920 return 24000000;
ffc1fac5
PT		 921 case PCLK_HDMI_CTRL:
922 break;
b0b3c865
KY		 923 case DCLK_VOP0:
924 case DCLK_VOP1:
925 break;
a70feb46
PT		 926 case PCLK_EFUSE1024NS:
927 break;
364fc731
DW		 928 case SCLK_SARADC:
929 rate = rk3399_saradc_get_clk(priv->cru);
930 break;
5328af17
SG		 931 case ACLK_VIO:
932 case ACLK_HDCP:
933 case ACLK_GIC_PRE:
934 case PCLK_DDR:
935 break;
b0b3c865 936 default:
5328af17 937 log_debug("Unknown clock %lu\n", clk->id);
b0b3c865
KY		 938 return -ENOENT;
939 }
940
941 return rate;
942}
943
944static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
945{
946 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
947 ulong ret = 0;
948
949 switch (clk->id) {
950 case 0 ... 63:
951 return 0;
d2f1f1ab
PT		 952
953 case ACLK_PERIHP:
954 case HCLK_PERIHP:
955 case PCLK_PERIHP:
956 return 0;
957
958 case ACLK_PERILP0:
959 case HCLK_PERILP0:
960 case PCLK_PERILP0:
961 return 0;
962
963 case ACLK_CCI:
964 return 0;
965
966 case HCLK_PERILP1:
967 case PCLK_PERILP1:
968 return 0;
969
998c61ae 970 case HCLK_SDMMC:
b0b3c865
KY		 971 case SCLK_SDMMC:
972 case SCLK_EMMC:
973 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
974 break;
65d83303 975 case SCLK_MAC:
a45f17e8 976 ret = rk3399_gmac_set_clk(priv->cru, rate);
65d83303 977 break;
b0b3c865
KY		 978 case SCLK_I2C1:
979 case SCLK_I2C2:
980 case SCLK_I2C3:
981 case SCLK_I2C5:
982 case SCLK_I2C6:
983 case SCLK_I2C7:
984 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
985 break;
8fa6979b
PT		 986 case SCLK_SPI0...SCLK_SPI5:
987 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
988 break;
ffc1fac5
PT		 989 case PCLK_HDMI_CTRL:
990 case PCLK_VIO_GRF:
991 /* the PCLK gates for video are enabled by default */
992 break;
b0b3c865
KY		 993 case DCLK_VOP0:
994 case DCLK_VOP1:
5e79f443 995 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
b0b3c865 996 break;
5ae2fd97
KY		 997 case SCLK_DDRCLK:
998 ret = rk3399_ddr_set_clk(priv->cru, rate);
999 break;
a70feb46
PT		 1000 case PCLK_EFUSE1024NS:
1001 break;
364fc731
DW		 1002 case SCLK_SARADC:
1003 ret = rk3399_saradc_set_clk(priv->cru, rate);
1004 break;
5328af17
SG		 1005 case ACLK_VIO:
1006 case ACLK_HDCP:
1007 case ACLK_GIC_PRE:
1008 case PCLK_DDR:
1009 return 0;
b0b3c865 1010 default:
5328af17 1011 log_debug("Unknown clock %lu\n", clk->id);
b0b3c865
KY		 1012 return -ENOENT;
1013 }
1014
1015 return ret;
1016}
1017
dd7dfa21
JT		 1018static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1019 struct clk *parent)
a45f17e8
PT		 1020{
1021 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1022 const char *clock_output_name;
1023 int ret;
1024
1025 /*
1026 * If the requested parent is in the same clock-controller and
1027 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1028 */
dd7dfa21 1029 if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
a45f17e8
PT		 1030 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1031 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1032 return 0;
1033 }
1034
1035 /*
1036 * Otherwise, we need to check the clock-output-names of the
1037 * requested parent to see if the requested id is "clkin_gmac".
1038 */
1039 ret = dev_read_string_index(parent->dev, "clock-output-names",
1040 parent->id, &clock_output_name);
1041 if (ret < 0)
1042 return -ENODATA;
1043
1044 /* If this is "clkin_gmac", switch to the external clock input */
1045 if (!strcmp(clock_output_name, "clkin_gmac")) {
1046 debug("%s: switching RGMII to CLKIN\n", __func__);
1047 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1048 return 0;
1049 }
1050
1051 return -EINVAL;
1052}
1053
dd7dfa21
JT		 1054static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1055 struct clk *parent)
a45f17e8
PT		 1056{
1057 switch (clk->id) {
1058 case SCLK_RMII_SRC:
1059 return rk3399_gmac_set_parent(clk, parent);
1060 }
1061
1062 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1063 return -ENOENT;
1064}
1065
b0b3c865
KY		 1066static struct clk_ops rk3399_clk_ops = {
1067 .get_rate = rk3399_clk_get_rate,
1068 .set_rate = rk3399_clk_set_rate,
75b381aa 1069#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a45f17e8 1070 .set_parent = rk3399_clk_set_parent,
75b381aa 1071#endif
b0b3c865
KY		 1072};
1073
9f636a24 1074#ifdef CONFIG_SPL_BUILD
b52a199e 1075static void rkclk_init(struct rockchip_cru *cru)
9f636a24
KY		 1076{
1077 u32 aclk_div;
1078 u32 hclk_div;
1079 u32 pclk_div;
1080
af765a49
CM		 1081 rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1082 rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
9f636a24
KY		 1083 /*
1084 * some cru registers changed by bootrom, we'd better reset them to
1085 * reset/default values described in TRM to avoid confusion in kernel.
1086 * Please consider these three lines as a fix of bootrom bug.
1087 */
1088 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1089 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1090 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1091
1092 /* configure gpll cpll */
1093 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1094 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1095
1096 /* configure perihp aclk, hclk, pclk */
1097 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1098 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1099
1100 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1101 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1102 PERIHP_ACLK_HZ && (hclk_div < 0x4));
1103
1104 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1105 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1106 PERIHP_ACLK_HZ && (pclk_div < 0x7));
1107
1108 rk_clrsetreg(&cru->clksel_con[14],
1109 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1110 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1111 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1112 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1113 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1114 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1115
1116 /* configure perilp0 aclk, hclk, pclk */
1117 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1118 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1119
1120 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1121 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1122 PERILP0_ACLK_HZ && (hclk_div < 0x4));
1123
1124 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1125 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1126 PERILP0_ACLK_HZ && (pclk_div < 0x7));
1127
1128 rk_clrsetreg(&cru->clksel_con[23],
1129 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1130 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1131 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1132 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1133 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1134 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1135
1136 /* perilp1 hclk select gpll as source */
1137 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1138 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1139 GPLL_HZ && (hclk_div < 0x1f));
1140
1141 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1142 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1143 PERILP1_HCLK_HZ && (hclk_div < 0x7));
1144
1145 rk_clrsetreg(&cru->clksel_con[25],
1146 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1147 HCLK_PERILP1_PLL_SEL_MASK,
1148 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1149 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1150 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1151}
1152#endif
1153
b0b3c865
KY		 1154static int rk3399_clk_probe(struct udevice *dev)
1155{
5ae2fd97 1156#ifdef CONFIG_SPL_BUILD
b0b3c865
KY		 1157 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1158
5ae2fd97
KY		 1159#if CONFIG_IS_ENABLED(OF_PLATDATA)
1160 struct rk3399_clk_plat *plat = dev_get_platdata(dev);
b0b3c865 1161
c20ee0ed 1162 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
5ae2fd97
KY		 1163#endif
1164 rkclk_init(priv->cru);
1165#endif
b0b3c865
KY		 1166 return 0;
1167}
1168
1169static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1170{
5ae2fd97 1171#if !CONFIG_IS_ENABLED(OF_PLATDATA)
b0b3c865
KY		 1172 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1173
75c78598 1174 priv->cru = dev_read_addr_ptr(dev);
5ae2fd97 1175#endif
b0b3c865
KY		 1176 return 0;
1177}
1178
1179static int rk3399_clk_bind(struct udevice *dev)
1180{
1181 int ret;
f24e36da
KY		 1182 struct udevice *sys_child;
1183 struct sysreset_reg *priv;
b0b3c865
KY		 1184
1185 /* The reset driver does not have a device node, so bind it here */
f24e36da
KY		 1186 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1187 &sys_child);
1188 if (ret) {
1189 debug("Warning: No sysreset driver: ret=%d\n", ret);
1190 } else {
1191 priv = malloc(sizeof(struct sysreset_reg));
b52a199e 1192 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
f24e36da 1193 glb_srst_fst_value);
b52a199e 1194 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
f24e36da
KY		 1195 glb_srst_snd_value);
1196 sys_child->priv = priv;
1197 }
b0b3c865 1198
a5ada25e 1199#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
b52a199e 1200 ret = offsetof(struct rockchip_cru, softrst_con[0]);
538f67c3
EZ		 1201 ret = rockchip_reset_bind(dev, ret, 21);
1202 if (ret)
1203 debug("Warning: software reset driver bind faile\n");
1204#endif
1205
b0b3c865
KY		 1206 return 0;
1207}
1208
1209static const struct udevice_id rk3399_clk_ids[] = {
1210 { .compatible = "rockchip,rk3399-cru" },
1211 { }
1212};
1213
1214U_BOOT_DRIVER(clk_rk3399) = {
5ae2fd97 1215 .name = "rockchip_rk3399_cru",
b0b3c865
KY		 1216 .id = UCLASS_CLK,
1217 .of_match = rk3399_clk_ids,
1218 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1219 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1220 .ops = &rk3399_clk_ops,
1221 .bind = rk3399_clk_bind,
1222 .probe = rk3399_clk_probe,
5ae2fd97
KY		 1223#if CONFIG_IS_ENABLED(OF_PLATDATA)
1224 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1225#endif
b0b3c865 1226};
5e79f443
KY		 1227
1228static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1229{
1230 u32 div, con;
1231
1232 switch (clk_id) {
1233 case SCLK_I2C0_PMU:
1234 con = readl(&pmucru->pmucru_clksel[2]);
1235 div = I2C_CLK_DIV_VALUE(con, 0);
1236 break;
1237 case SCLK_I2C4_PMU:
1238 con = readl(&pmucru->pmucru_clksel[3]);
1239 div = I2C_CLK_DIV_VALUE(con, 4);
1240 break;
1241 case SCLK_I2C8_PMU:
1242 con = readl(&pmucru->pmucru_clksel[2]);
1243 div = I2C_CLK_DIV_VALUE(con, 8);
1244 break;
1245 default:
1246 printf("do not support this i2c bus\n");
1247 return -EINVAL;
1248 }
1249
1250 return DIV_TO_RATE(PPLL_HZ, div);
1251}
1252
1253static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1254 uint hz)
1255{
1256 int src_clk_div;
1257
1258 src_clk_div = PPLL_HZ / hz;
1259 assert(src_clk_div - 1 < 127);
1260
1261 switch (clk_id) {
1262 case SCLK_I2C0_PMU:
1263 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1264 I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1265 break;
1266 case SCLK_I2C4_PMU:
1267 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1268 I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1269 break;
1270 case SCLK_I2C8_PMU:
1271 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1272 I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1273 break;
1274 default:
1275 printf("do not support this i2c bus\n");
1276 return -EINVAL;
1277 }
1278
1279 return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1280}
1281
1282static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1283{
1284 u32 div, con;
1285
1286 /* PWM closk rate is same as pclk_pmu */
1287 con = readl(&pmucru->pmucru_clksel[0]);
1288 div = con & PMU_PCLK_DIV_CON_MASK;
1289
1290 return DIV_TO_RATE(PPLL_HZ, div);
1291}
1292
1293static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1294{
1295 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1296 ulong rate = 0;
1297
1298 switch (clk->id) {
434d5a00
PT		 1299 case PLL_PPLL:
1300 return PPLL_HZ;
5e79f443
KY		 1301 case PCLK_RKPWM_PMU:
1302 rate = rk3399_pwm_get_clk(priv->pmucru);
1303 break;
1304 case SCLK_I2C0_PMU:
1305 case SCLK_I2C4_PMU:
1306 case SCLK_I2C8_PMU:
1307 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1308 break;
1309 default:
1310 return -ENOENT;
1311 }
1312
1313 return rate;
1314}
1315
1316static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1317{
1318 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1319 ulong ret = 0;
1320
1321 switch (clk->id) {
434d5a00
PT		 1322 case PLL_PPLL:
1323 /*
1324 * This has already been set up and we don't want/need
1325 * to change it here. Accept the request though, as the
1326 * device-tree has this in an 'assigned-clocks' list.
1327 */
1328 return PPLL_HZ;
5e79f443
KY		 1329 case SCLK_I2C0_PMU:
1330 case SCLK_I2C4_PMU:
1331 case SCLK_I2C8_PMU:
1332 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1333 break;
1334 default:
1335 return -ENOENT;
1336 }
1337
1338 return ret;
1339}
1340
1341static struct clk_ops rk3399_pmuclk_ops = {
1342 .get_rate = rk3399_pmuclk_get_rate,
1343 .set_rate = rk3399_pmuclk_set_rate,
1344};
1345
5ae2fd97 1346#ifndef CONFIG_SPL_BUILD
5e79f443
KY		 1347static void pmuclk_init(struct rk3399_pmucru *pmucru)
1348{
1349 u32 pclk_div;
1350
1351 /* configure pmu pll(ppll) */
1352 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1353
1354 /* configure pmu pclk */
1355 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
5e79f443
KY		 1356 rk_clrsetreg(&pmucru->pmucru_clksel[0],
1357 PMU_PCLK_DIV_CON_MASK,
1358 pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1359}
5ae2fd97 1360#endif
5e79f443
KY		 1361
1362static int rk3399_pmuclk_probe(struct udevice *dev)
1363{
61dff33b 1364#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
5e79f443 1365 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
61dff33b 1366#endif
5e79f443 1367
5ae2fd97
KY		 1368#if CONFIG_IS_ENABLED(OF_PLATDATA)
1369 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1370
c20ee0ed 1371 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
5ae2fd97 1372#endif
5e79f443 1373
5ae2fd97
KY		 1374#ifndef CONFIG_SPL_BUILD
1375 pmuclk_init(priv->pmucru);
1376#endif
5e79f443
KY		 1377 return 0;
1378}
1379
1380static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1381{
5ae2fd97 1382#if !CONFIG_IS_ENABLED(OF_PLATDATA)
5e79f443
KY		 1383 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1384
75c78598 1385 priv->pmucru = dev_read_addr_ptr(dev);
5ae2fd97 1386#endif
5e79f443
KY		 1387 return 0;
1388}
1389
538f67c3
EZ		 1390static int rk3399_pmuclk_bind(struct udevice *dev)
1391{
1392#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1393 int ret;
1394
1395 ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1396 ret = rockchip_reset_bind(dev, ret, 2);
1397 if (ret)
1398 debug("Warning: software reset driver bind faile\n");
1399#endif
1400 return 0;
1401}
1402
5e79f443
KY		 1403static const struct udevice_id rk3399_pmuclk_ids[] = {
1404 { .compatible = "rockchip,rk3399-pmucru" },
1405 { }
1406};
1407
c8a6bc96 1408U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
5ae2fd97 1409 .name = "rockchip_rk3399_pmucru",
5e79f443
KY		 1410 .id = UCLASS_CLK,
1411 .of_match = rk3399_pmuclk_ids,
1412 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1413 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1414 .ops = &rk3399_pmuclk_ops,
1415 .probe = rk3399_pmuclk_probe,
538f67c3 1416 .bind = rk3399_pmuclk_bind,
5ae2fd97
KY		 1417#if CONFIG_IS_ENABLED(OF_PLATDATA)
1418 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1419#endif
5e79f443 1420};
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