[thirdparty/kernel/stable.git] / drivers / clk / samsung / clk-pll.h

/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Copyright (c) 2013 Linaro Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for all PLL's in Samsung platforms
*/

#ifndef __SAMSUNG_CLK_PLL_H
#define __SAMSUNG_CLK_PLL_H

enum samsung_pll_type {
	pll_35xx,
	pll_36xx,
	pll_2550,
	pll_2650,
	pll_4500,
	pll_4502,
	pll_4508,
	pll_6552,
	pll_6553,
};

#define PLL_35XX_RATE(_rate, _m, _p, _s)			\
	{							\
		.rate	=	(_rate),				\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
	}

#define PLL_36XX_RATE(_rate, _m, _p, _s, _k)			\
	{							\
		.rate	=	(_rate),				\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
	}

/* NOTE: Rate table should be kept sorted in descending order. */

struct samsung_pll_rate_table {
	unsigned int rate;
	unsigned int pdiv;
	unsigned int mdiv;
	unsigned int sdiv;
	unsigned int kdiv;
};

enum pll46xx_type {
	pll_4600,
	pll_4650,
	pll_4650c,
};

extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
			const char *pname, const void __iomem *con_reg,
			enum pll46xx_type type);
extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
			const char *pname, const void __iomem *reg_base,
			const unsigned long offset);

#endif /* __SAMSUNG_CLK_PLL_H */
Commit	Line	Data
1c4c5fe0 TA	1	/*
	2	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	3	* Copyright (c) 2013 Linaro Ltd.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* Common Clock Framework support for all PLL's in Samsung platforms
	10	*/
	11
	12	#ifndef __SAMSUNG_CLK_PLL_H
	13	#define __SAMSUNG_CLK_PLL_H
	14
07dc76fa YSB	15	enum samsung_pll_type {
	16	pll_35xx,
	17	pll_36xx,
	18	pll_2550,
	19	pll_2650,
52b06016 TF	20	pll_4500,
	21	pll_4502,
	22	pll_4508,
40ef723c TF	23	pll_6552,
40ef723c TF	24	pll_6553,
07dc76fa YSB	25	};
07dc76fa YSB	26
3ff6e0d8 YSB	27	#define PLL_35XX_RATE(_rate, _m, _p, _s) \
	28	{ \
	29	.rate = (_rate), \
	30	.mdiv = (_m), \
	31	.pdiv = (_p), \
	32	.sdiv = (_s), \
	33	}
	34
	35	#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \
	36	{ \
	37	.rate = (_rate), \
	38	.mdiv = (_m), \
	39	.pdiv = (_p), \
	40	.sdiv = (_s), \
	41	.kdiv = (_k), \
	42	}
	43
	44	/* NOTE: Rate table should be kept sorted in descending order. */
	45
	46	struct samsung_pll_rate_table {
	47	unsigned int rate;
	48	unsigned int pdiv;
	49	unsigned int mdiv;
	50	unsigned int sdiv;
	51	unsigned int kdiv;
	52	};
	53
1c4c5fe0 TA	54	enum pll46xx_type {
	55	pll_4600,
	56	pll_4650,
	57	pll_4650c,
	58	};
	59
1c4c5fe0 TA	60	extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
	61	const char pname, const void __iomem con_reg,
	62	enum pll46xx_type type);
	63	extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
	64	const char pname, const void __iomem reg_base,
	65	const unsigned long offset);
	66
	67	#endif /* __SAMSUNG_CLK_PLL_H */