projects / thirdparty / kernel / stable.git / blame
| Commit | Line | Data |
|---|---|---|
| 1c4c5fe0 TA |
1 | /* |
| 2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
| 3 | * Copyright (c) 2013 Linaro Ltd. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * Common Clock Framework support for all PLL's in Samsung platforms | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __SAMSUNG_CLK_PLL_H | |
| 13 | #define __SAMSUNG_CLK_PLL_H | |
| 14 | ||
| 07dc76fa YSB |
15 | enum samsung_pll_type { |
| 16 | pll_35xx, | |
| 17 | pll_36xx, | |
| 18 | pll_2550, | |
| 19 | pll_2650, | |
| 52b06016 TF |
20 | pll_4500, |
| 21 | pll_4502, | |
| 22 | pll_4508, | |
| 40ef723c TF |
23 | pll_6552, |
| 24 | pll_6553, | |
| 07dc76fa YSB |
25 | }; |
| 26 | ||
| 3ff6e0d8 YSB |
27 | #define PLL_35XX_RATE(_rate, _m, _p, _s) \ |
| 28 | { \ | |
| 29 | .rate = (_rate), \ | |
| 30 | .mdiv = (_m), \ | |
| 31 | .pdiv = (_p), \ | |
| 32 | .sdiv = (_s), \ | |
| 33 | } | |
| 34 | ||
| 35 | #define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \ | |
| 36 | { \ | |
| 37 | .rate = (_rate), \ | |
| 38 | .mdiv = (_m), \ | |
| 39 | .pdiv = (_p), \ | |
| 40 | .sdiv = (_s), \ | |
| 41 | .kdiv = (_k), \ | |
| 42 | } | |
| 43 | ||
| b4054ac6 TF |
44 | #define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \ |
| 45 | { \ | |
| 46 | .rate = (_rate), \ | |
| 47 | .mdiv = (_m), \ | |
| 48 | .pdiv = (_p), \ | |
| 49 | .sdiv = (_s), \ | |
| 50 | .afc = (_afc), \ | |
| 51 | } | |
| 52 | ||
| 3ff6e0d8 YSB |
53 | /* NOTE: Rate table should be kept sorted in descending order. */ |
| 54 | ||
| 55 | struct samsung_pll_rate_table { | |
| 56 | unsigned int rate; | |
| 57 | unsigned int pdiv; | |
| 58 | unsigned int mdiv; | |
| 59 | unsigned int sdiv; | |
| 60 | unsigned int kdiv; | |
| b4054ac6 | 61 | unsigned int afc; |
| 3ff6e0d8 YSB |
62 | }; |
| 63 | ||
| 1c4c5fe0 TA |
64 | enum pll46xx_type { |
| 65 | pll_4600, | |
| 66 | pll_4650, | |
| 67 | pll_4650c, | |
| 68 | }; | |
| 69 | ||
| 1c4c5fe0 TA |
70 | extern struct clk * __init samsung_clk_register_pll46xx(const char *name, |
| 71 | const char *pname, const void __iomem *con_reg, | |
| 72 | enum pll46xx_type type); | |
| 73 | extern struct clk * __init samsung_clk_register_pll2550x(const char *name, | |
| 74 | const char *pname, const void __iomem *reg_base, | |
| 75 | const unsigned long offset); | |
| 76 | ||
| 77 | #endif /* __SAMSUNG_CLK_PLL_H */ |