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clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
[thirdparty/kernel/stable.git] / drivers / clk / samsung / clk-pll.h
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1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for all PLL's in Samsung platforms
10*/
11
12#ifndef __SAMSUNG_CLK_PLL_H
13#define __SAMSUNG_CLK_PLL_H
14
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15enum samsung_pll_type {
16 pll_35xx,
17 pll_36xx,
18 pll_2550,
19 pll_2650,
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20 pll_6552,
21 pll_6553,
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22};
23
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24#define PLL_35XX_RATE(_rate, _m, _p, _s) \
25 { \
26 .rate = (_rate), \
27 .mdiv = (_m), \
28 .pdiv = (_p), \
29 .sdiv = (_s), \
30 }
31
32#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \
33 { \
34 .rate = (_rate), \
35 .mdiv = (_m), \
36 .pdiv = (_p), \
37 .sdiv = (_s), \
38 .kdiv = (_k), \
39 }
40
41/* NOTE: Rate table should be kept sorted in descending order. */
42
43struct samsung_pll_rate_table {
44 unsigned int rate;
45 unsigned int pdiv;
46 unsigned int mdiv;
47 unsigned int sdiv;
48 unsigned int kdiv;
49};
50
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51enum pll45xx_type {
52 pll_4500,
53 pll_4502,
54 pll_4508
55};
56
57enum pll46xx_type {
58 pll_4600,
59 pll_4650,
60 pll_4650c,
61};
62
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63extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
64 const char *pname, const void __iomem *con_reg,
65 enum pll45xx_type type);
66extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
67 const char *pname, const void __iomem *con_reg,
68 enum pll46xx_type type);
69extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
70 const char *pname, const void __iomem *reg_base,
71 const unsigned long offset);
72
73#endif /* __SAMSUNG_CLK_PLL_H */