[thirdparty/kernel/stable.git] / drivers / clk / samsung / clk-pll.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Copyright (c) 2013 Linaro Ltd.
 *
 * Common Clock Framework support for all PLL's in Samsung platforms
*/

#ifndef __SAMSUNG_CLK_PLL_H
#define __SAMSUNG_CLK_PLL_H

enum samsung_pll_type {
	pll_2126,
	pll_3000,
	pll_35xx,
	pll_36xx,
	pll_2550,
	pll_2650,
	pll_4500,
	pll_4502,
	pll_4508,
	pll_4600,
	pll_4650,
	pll_4650c,
	pll_6552,
	pll_6552_s3c2416,
	pll_6553,
	pll_2550x,
	pll_2550xx,
	pll_2650x,
	pll_2650xx,
	pll_1417x,
	pll_1450x,
	pll_1451x,
	pll_1452x,
	pll_1460x,
	pll_0818x,
	pll_0822x,
	pll_0831x,
	pll_142xx,
	pll_0516x,
	pll_0517x,
	pll_0518x,
};

#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
	((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
	BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))

#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)			\
	{							\
		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
				_m, _p, _s, 0, 16),		\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
	}

#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)		\
	{							\
		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
				_m, _p, _s, _k, 16),		\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
	}

#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)		\
	{							\
		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
				_m, _p, _s - 1, 0, 16),		\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.afc	=	(_afc),				\
	}

#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)	\
	{							\
		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
				_m, _p, _s, _k, 16),		\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
		.vsel	=	(_vsel),			\
	}

#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
	{							\
		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
				_m, _p, _s, _k, 10),		\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
		.mfr	=	(_mfr),				\
		.mrr	=	(_mrr),				\
		.vsel	=	(_vsel),			\
	}

/* NOTE: Rate table should be kept sorted in descending order. */

struct samsung_pll_rate_table {
	unsigned int rate;
	unsigned int pdiv;
	unsigned int mdiv;
	unsigned int sdiv;
	unsigned int kdiv;
	unsigned int afc;
	unsigned int mfr;
	unsigned int mrr;
	unsigned int vsel;
};

#endif /* __SAMSUNG_CLK_PLL_H */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
1c4c5fe0 TA	2	/*
	3	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	4	* Copyright (c) 2013 Linaro Ltd.
	5	*
1c4c5fe0 TA	6	* Common Clock Framework support for all PLL's in Samsung platforms
	7	*/
	8
	9	#ifndef __SAMSUNG_CLK_PLL_H
	10	#define __SAMSUNG_CLK_PLL_H
	11
07dc76fa	12	enum samsung_pll_type {
a951b1d9 HS	13	pll_2126,
a951b1d9 HS	14	pll_3000,
07dc76fa YSB	15	pll_35xx,
	16	pll_36xx,
	17	pll_2550,
	18	pll_2650,
52b06016 TF	19	pll_4500,
	20	pll_4502,
	21	pll_4508,
c50d11f3 TF	22	pll_4600,
	23	pll_4650,
	24	pll_4650c,
40ef723c	25	pll_6552,
06654acb	26	pll_6552_s3c2416,
40ef723c	27	pll_6553,
1d9aa64c	28	pll_2550x,
84329847	29	pll_2550xx,
be95d2c7	30	pll_2650x,
eefe119b	31	pll_2650xx,
c703a2f4	32	pll_1417x,
0c23e2af NKC	33	pll_1450x,
	34	pll_1451x,
	35	pll_1452x,
	36	pll_1460x,
f2819ea1	37	pll_0818x,
8f90f43a	38	pll_0822x,
6a734b37	39	pll_0831x,
4f346005	40	pll_142xx,
13ff3bda PG	41	pll_0516x,
	42	pll_0517x,
	43	pll_0518x,
07dc76fa YSB	44	};
07dc76fa YSB	45
1d5013f1 AH	46	#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
	47	((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
	48	#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
	49	BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
	50
	51	#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \
	52	{ \
	53	.rate = PLL_VALID_RATE(_fin, _rate, \
	54	_m, _p, _s, 0, 16), \
	55	.mdiv = (_m), \
	56	.pdiv = (_p), \
	57	.sdiv = (_s), \
	58	}
	59
1d5013f1	60	#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
3ff6e0d8	61	{ \
1d5013f1 AH	62	.rate = PLL_VALID_RATE(_fin, _rate, \
1d5013f1 AH	63	_m, _p, _s, _k, 16), \
3ff6e0d8 YSB	64	.mdiv = (_m), \
	65	.pdiv = (_p), \
	66	.sdiv = (_s), \
	67	.kdiv = (_k), \
	68	}
	69
1d5013f1	70	#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \
b4054ac6	71	{ \
1d5013f1 AH	72	.rate = PLL_VALID_RATE(_fin, _rate, \
1d5013f1 AH	73	_m, _p, _s - 1, 0, 16), \
b4054ac6 TF	74	.mdiv = (_m), \
	75	.pdiv = (_p), \
	76	.sdiv = (_s), \
	77	.afc = (_afc), \
	78	}
	79
1d5013f1	80	#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \
5c89658a	81	{ \
1d5013f1 AH	82	.rate = PLL_VALID_RATE(_fin, _rate, \
1d5013f1 AH	83	_m, _p, _s, _k, 16), \
5c89658a TF	84	.mdiv = (_m), \
	85	.pdiv = (_p), \
	86	.sdiv = (_s), \
	87	.kdiv = (_k), \
	88	.vsel = (_vsel), \
	89	}
	90
1d5013f1	91	#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
5c89658a	92	{ \
1d5013f1 AH	93	.rate = PLL_VALID_RATE(_fin, _rate, \
1d5013f1 AH	94	_m, _p, _s, _k, 10), \
5c89658a TF	95	.mdiv = (_m), \
	96	.pdiv = (_p), \
	97	.sdiv = (_s), \
	98	.kdiv = (_k), \
	99	.mfr = (_mfr), \
	100	.mrr = (_mrr), \
	101	.vsel = (_vsel), \
	102	}
	103
3ff6e0d8 YSB	104	/* NOTE: Rate table should be kept sorted in descending order. */
	105
	106	struct samsung_pll_rate_table {
	107	unsigned int rate;
	108	unsigned int pdiv;
	109	unsigned int mdiv;
	110	unsigned int sdiv;
	111	unsigned int kdiv;
b4054ac6	112	unsigned int afc;
5c89658a TF	113	unsigned int mfr;
	114	unsigned int mrr;
	115	unsigned int vsel;
3ff6e0d8 YSB	116	};
3ff6e0d8 YSB	117
1c4c5fe0	118	#endif /* __SAMSUNG_CLK_PLL_H */