[thirdparty/kernel/stable.git] / drivers / clk / sunxi / clk-sun9i-mmc.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2015 Chen-Yu Tsai
 *
 * Chen-Yu Tsai	<wens@csie.org>
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/reset.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define SUN9I_MMC_WIDTH		4

#define SUN9I_MMC_GATE_BIT	16
#define SUN9I_MMC_RESET_BIT	18

struct sun9i_mmc_clk_data {
	spinlock_t			lock;
	void __iomem			*membase;
	struct clk			*clk;
	struct reset_control		*reset;
	struct clk_onecell_data		clk_data;
	struct reset_controller_dev	rcdev;
};

static int sun9i_mmc_reset_assert(struct reset_controller_dev *rcdev,
			      unsigned long id)
{
	struct sun9i_mmc_clk_data *data = container_of(rcdev,
						       struct sun9i_mmc_clk_data,
						       rcdev);
	unsigned long flags;
	void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
	u32 val;

	clk_prepare_enable(data->clk);
	spin_lock_irqsave(&data->lock, flags);

	val = readl(reg);
	writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);

	spin_unlock_irqrestore(&data->lock, flags);
	clk_disable_unprepare(data->clk);

	return 0;
}

static int sun9i_mmc_reset_deassert(struct reset_controller_dev *rcdev,
				unsigned long id)
{
	struct sun9i_mmc_clk_data *data = container_of(rcdev,
						       struct sun9i_mmc_clk_data,
						       rcdev);
	unsigned long flags;
	void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
	u32 val;

	clk_prepare_enable(data->clk);
	spin_lock_irqsave(&data->lock, flags);

	val = readl(reg);
	writel(val | BIT(SUN9I_MMC_RESET_BIT), reg);

	spin_unlock_irqrestore(&data->lock, flags);
	clk_disable_unprepare(data->clk);

	return 0;
}

static int sun9i_mmc_reset_reset(struct reset_controller_dev *rcdev,
				 unsigned long id)
{
	sun9i_mmc_reset_assert(rcdev, id);
	udelay(10);
	sun9i_mmc_reset_deassert(rcdev, id);

	return 0;
}

static const struct reset_control_ops sun9i_mmc_reset_ops = {
	.assert		= sun9i_mmc_reset_assert,
	.deassert	= sun9i_mmc_reset_deassert,
	.reset		= sun9i_mmc_reset_reset,
};

static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct sun9i_mmc_clk_data *data;
	struct clk_onecell_data *clk_data;
	const char *clk_name = np->name;
	const char *clk_parent;
	struct resource *r;
	int count, i, ret;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	spin_lock_init(&data->lock);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	/* one clock/reset pair per word */
	count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
	data->membase = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(data->membase))
		return PTR_ERR(data->membase);

	clk_data = &data->clk_data;
	clk_data->clk_num = count;
	clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
				      GFP_KERNEL);
	if (!clk_data->clks)
		return -ENOMEM;

	data->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(data->clk)) {
		dev_err(&pdev->dev, "Could not get clock\n");
		return PTR_ERR(data->clk);
	}

	data->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
	if (IS_ERR(data->reset)) {
		dev_err(&pdev->dev, "Could not get reset control\n");
		return PTR_ERR(data->reset);
	}

	ret = reset_control_deassert(data->reset);
	if (ret) {
		dev_err(&pdev->dev, "Reset deassert err %d\n", ret);
		return ret;
	}

	clk_parent = __clk_get_name(data->clk);
	for (i = 0; i < count; i++) {
		of_property_read_string_index(np, "clock-output-names",
					      i, &clk_name);

		clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
						      clk_parent, 0,
						      data->membase + SUN9I_MMC_WIDTH * i,
						      SUN9I_MMC_GATE_BIT, 0,
						      &data->lock);

		if (IS_ERR(clk_data->clks[i])) {
			ret = PTR_ERR(clk_data->clks[i]);
			goto err_clk_register;
		}
	}

	ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
	if (ret)
		goto err_clk_provider;

	data->rcdev.owner = THIS_MODULE;
	data->rcdev.nr_resets = count;
	data->rcdev.ops = &sun9i_mmc_reset_ops;
	data->rcdev.of_node = pdev->dev.of_node;

	ret = reset_controller_register(&data->rcdev);
	if (ret)
		goto err_rc_reg;

	platform_set_drvdata(pdev, data);

	return 0;

err_rc_reg:
	of_clk_del_provider(np);

err_clk_provider:
	for (i = 0; i < count; i++)
		clk_unregister(clk_data->clks[i]);

err_clk_register:
	reset_control_assert(data->reset);

	return ret;
}

static const struct of_device_id sun9i_a80_mmc_config_clk_dt_ids[] = {
	{ .compatible = "allwinner,sun9i-a80-mmc-config-clk" },
	{ /* sentinel */ }
};

static struct platform_driver sun9i_a80_mmc_config_clk_driver = {
	.driver = {
		.name = "sun9i-a80-mmc-config-clk",
		.suppress_bind_attrs = true,
		.of_match_table = sun9i_a80_mmc_config_clk_dt_ids,
	},
	.probe = sun9i_a80_mmc_config_clk_probe,
};
builtin_platform_driver(sun9i_a80_mmc_config_clk_driver);
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
7a6fca87 CYT	2	/*
	3	* Copyright 2015 Chen-Yu Tsai
	4	*
	5	* Chen-Yu Tsai <wens@csie.org>
7a6fca87 CYT	6	*/
7a6fca87 CYT	7
9dfefe8c	8	#include <linux/clk.h>
7a6fca87	9	#include <linux/clk-provider.h>
61d2f2a0	10	#include <linux/delay.h>
439a36d7	11	#include <linux/init.h>
62e59c4e	12	#include <linux/io.h>
7a6fca87 CYT	13	#include <linux/of.h>
	14	#include <linux/of_device.h>
	15	#include <linux/reset.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/reset-controller.h>
9dfefe8c	18	#include <linux/slab.h>
7a6fca87 CYT	19	#include <linux/spinlock.h>
	20
	21	#define SUN9I_MMC_WIDTH 4
	22
	23	#define SUN9I_MMC_GATE_BIT 16
	24	#define SUN9I_MMC_RESET_BIT 18
	25
	26	struct sun9i_mmc_clk_data {
	27	spinlock_t lock;
	28	void __iomem *membase;
	29	struct clk *clk;
	30	struct reset_control *reset;
	31	struct clk_onecell_data clk_data;
	32	struct reset_controller_dev rcdev;
	33	};
	34
	35	static int sun9i_mmc_reset_assert(struct reset_controller_dev *rcdev,
	36	unsigned long id)
	37	{
	38	struct sun9i_mmc_clk_data *data = container_of(rcdev,
	39	struct sun9i_mmc_clk_data,
	40	rcdev);
	41	unsigned long flags;
	42	void __iomem reg = data->membase + SUN9I_MMC_WIDTH id;
	43	u32 val;
	44
	45	clk_prepare_enable(data->clk);
	46	spin_lock_irqsave(&data->lock, flags);
	47
	48	val = readl(reg);
	49	writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);
	50
	51	spin_unlock_irqrestore(&data->lock, flags);
	52	clk_disable_unprepare(data->clk);
	53
	54	return 0;
	55	}
	56
	57	static int sun9i_mmc_reset_deassert(struct reset_controller_dev *rcdev,
	58	unsigned long id)
	59	{
	60	struct sun9i_mmc_clk_data *data = container_of(rcdev,
	61	struct sun9i_mmc_clk_data,
	62	rcdev);
	63	unsigned long flags;
	64	void __iomem reg = data->membase + SUN9I_MMC_WIDTH id;
	65	u32 val;
	66
	67	clk_prepare_enable(data->clk);
	68	spin_lock_irqsave(&data->lock, flags);
	69
	70	val = readl(reg);
	71	writel(val \| BIT(SUN9I_MMC_RESET_BIT), reg);
	72
	73	spin_unlock_irqrestore(&data->lock, flags);
	74	clk_disable_unprepare(data->clk);
	75
	76	return 0;
	77	}
	78
61d2f2a0 CYT	79	static int sun9i_mmc_reset_reset(struct reset_controller_dev *rcdev,
	80	unsigned long id)
	81	{
	82	sun9i_mmc_reset_assert(rcdev, id);
	83	udelay(10);
	84	sun9i_mmc_reset_deassert(rcdev, id);
	85
	86	return 0;
	87	}
	88
5e7bc9c6	89	static const struct reset_control_ops sun9i_mmc_reset_ops = {
7a6fca87 CYT	90	.assert = sun9i_mmc_reset_assert,
7a6fca87 CYT	91	.deassert = sun9i_mmc_reset_deassert,
61d2f2a0	92	.reset = sun9i_mmc_reset_reset,
7a6fca87 CYT	93	};
	94
	95	static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
	96	{
	97	struct device_node *np = pdev->dev.of_node;
	98	struct sun9i_mmc_clk_data *data;
	99	struct clk_onecell_data *clk_data;
	100	const char *clk_name = np->name;
	101	const char *clk_parent;
	102	struct resource *r;
	103	int count, i, ret;
	104
	105	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	106	if (!data)
	107	return -ENOMEM;
	108
	109	spin_lock_init(&data->lock);
	110
	111	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	112	/* one clock/reset pair per word */
f4b9ef65	113	count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
7a6fca87 CYT	114	data->membase = devm_ioremap_resource(&pdev->dev, r);
	115	if (IS_ERR(data->membase))
	116	return PTR_ERR(data->membase);
	117
	118	clk_data = &data->clk_data;
	119	clk_data->clk_num = count;
	120	clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
	121	GFP_KERNEL);
	122	if (!clk_data->clks)
	123	return -ENOMEM;
	124
	125	data->clk = devm_clk_get(&pdev->dev, NULL);
	126	if (IS_ERR(data->clk)) {
	127	dev_err(&pdev->dev, "Could not get clock\n");
	128	return PTR_ERR(data->clk);
	129	}
	130
cb92a19b	131	data->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
7a6fca87 CYT	132	if (IS_ERR(data->reset)) {
	133	dev_err(&pdev->dev, "Could not get reset control\n");
	134	return PTR_ERR(data->reset);
	135	}
	136
	137	ret = reset_control_deassert(data->reset);
	138	if (ret) {
	139	dev_err(&pdev->dev, "Reset deassert err %d\n", ret);
	140	return ret;
	141	}
	142
	143	clk_parent = __clk_get_name(data->clk);
	144	for (i = 0; i < count; i++) {
	145	of_property_read_string_index(np, "clock-output-names",
	146	i, &clk_name);
	147
	148	clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
	149	clk_parent, 0,
	150	data->membase + SUN9I_MMC_WIDTH * i,
	151	SUN9I_MMC_GATE_BIT, 0,
	152	&data->lock);
	153
	154	if (IS_ERR(clk_data->clks[i])) {
	155	ret = PTR_ERR(clk_data->clks[i]);
	156	goto err_clk_register;
	157	}
	158	}
	159
	160	ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
	161	if (ret)
	162	goto err_clk_provider;
	163
	164	data->rcdev.owner = THIS_MODULE;
	165	data->rcdev.nr_resets = count;
	166	data->rcdev.ops = &sun9i_mmc_reset_ops;
	167	data->rcdev.of_node = pdev->dev.of_node;
	168
	169	ret = reset_controller_register(&data->rcdev);
	170	if (ret)
	171	goto err_rc_reg;
	172
	173	platform_set_drvdata(pdev, data);
	174
	175	return 0;
	176
	177	err_rc_reg:
	178	of_clk_del_provider(np);
	179
	180	err_clk_provider:
	181	for (i = 0; i < count; i++)
	182	clk_unregister(clk_data->clks[i]);
	183
	184	err_clk_register:
	185	reset_control_assert(data->reset);
	186
	187	return ret;
	188	}
	189
7a6fca87 CYT	190	static const struct of_device_id sun9i_a80_mmc_config_clk_dt_ids[] = {
	191	{ .compatible = "allwinner,sun9i-a80-mmc-config-clk" },
	192	{ /* sentinel */ }
	193	};
	194
	195	static struct platform_driver sun9i_a80_mmc_config_clk_driver = {
	196	.driver = {
	197	.name = "sun9i-a80-mmc-config-clk",
439a36d7	198	.suppress_bind_attrs = true,
7a6fca87 CYT	199	.of_match_table = sun9i_a80_mmc_config_clk_dt_ids,
	200	},
	201	.probe = sun9i_a80_mmc_config_clk_probe,
7a6fca87	202	};
439a36d7	203	builtin_platform_driver(sun9i_a80_mmc_config_clk_driver);