[people/arne_f/kernel.git] / drivers / clocksource / dw_apb_timer.c

/*
 * (C) Copyright 2009 Intel Corporation
 * Author: Jacob Pan (jacob.jun.pan@intel.com)
 *
 * Shared with ARM platforms, Jamie Iles, Picochip 2011
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Support for the Synopsys DesignWare APB Timers.
 */
#include <linux/dw_apb_timer.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/slab.h>

#define APBT_MIN_PERIOD			4
#define APBT_MIN_DELTA_USEC		200

#define APBTMR_N_LOAD_COUNT		0x00
#define APBTMR_N_CURRENT_VALUE		0x04
#define APBTMR_N_CONTROL		0x08
#define APBTMR_N_EOI			0x0c
#define APBTMR_N_INT_STATUS		0x10

#define APBTMRS_INT_STATUS		0xa0
#define APBTMRS_EOI			0xa4
#define APBTMRS_RAW_INT_STATUS		0xa8
#define APBTMRS_COMP_VERSION		0xac

#define APBTMR_CONTROL_ENABLE		(1 << 0)
/* 1: periodic, 0:free running. */
#define APBTMR_CONTROL_MODE_PERIODIC	(1 << 1)
#define APBTMR_CONTROL_INT		(1 << 2)

static inline struct dw_apb_clock_event_device *
ced_to_dw_apb_ced(struct clock_event_device *evt)
{
	return container_of(evt, struct dw_apb_clock_event_device, ced);
}

static inline struct dw_apb_clocksource *
clocksource_to_dw_apb_clocksource(struct clocksource *cs)
{
	return container_of(cs, struct dw_apb_clocksource, cs);
}

static inline u32 apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
{
	return readl(timer->base + offs);
}

static inline void apbt_writel(struct dw_apb_timer *timer, u32 val,
			unsigned long offs)
{
	writel(val, timer->base + offs);
}

static inline u32 apbt_readl_relaxed(struct dw_apb_timer *timer, unsigned long offs)
{
	return readl_relaxed(timer->base + offs);
}

static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val,
			unsigned long offs)
{
	writel_relaxed(val, timer->base + offs);
}

static void apbt_disable_int(struct dw_apb_timer *timer)
{
	u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);

	ctrl |= APBTMR_CONTROL_INT;
	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
}

/**
 * dw_apb_clockevent_pause() - stop the clock_event_device from running
 *
 * @dw_ced:	The APB clock to stop generating events.
 */
void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
{
	disable_irq(dw_ced->timer.irq);
	apbt_disable_int(&dw_ced->timer);
}

static void apbt_eoi(struct dw_apb_timer *timer)
{
	apbt_readl_relaxed(timer, APBTMR_N_EOI);
}

static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
{
	struct clock_event_device *evt = data;
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);

	if (!evt->event_handler) {
		pr_info("Spurious APBT timer interrupt %d\n", irq);
		return IRQ_NONE;
	}

	if (dw_ced->eoi)
		dw_ced->eoi(&dw_ced->timer);

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static void apbt_enable_int(struct dw_apb_timer *timer)
{
	u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
	/* clear pending intr */
	apbt_readl(timer, APBTMR_N_EOI);
	ctrl &= ~APBTMR_CONTROL_INT;
	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
}

static int apbt_shutdown(struct clock_event_device *evt)
{
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	u32 ctrl;

	pr_debug("%s CPU %d state=shutdown\n", __func__,
		 cpumask_first(evt->cpumask));

	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	ctrl &= ~APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	return 0;
}

static int apbt_set_oneshot(struct clock_event_device *evt)
{
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	u32 ctrl;

	pr_debug("%s CPU %d state=oneshot\n", __func__,
		 cpumask_first(evt->cpumask));

	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	/*
	 * set free running mode, this mode will let timer reload max
	 * timeout which will give time (3min on 25MHz clock) to rearm
	 * the next event, therefore emulate the one-shot mode.
	 */
	ctrl &= ~APBTMR_CONTROL_ENABLE;
	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;

	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	/* write again to set free running mode */
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);

	/*
	 * DW APB p. 46, load counter with all 1s before starting free
	 * running mode.
	 */
	apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
	ctrl &= ~APBTMR_CONTROL_INT;
	ctrl |= APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	return 0;
}

static int apbt_set_periodic(struct clock_event_device *evt)
{
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
	u32 ctrl;

	pr_debug("%s CPU %d state=periodic\n", __func__,
		 cpumask_first(evt->cpumask));

	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	/*
	 * DW APB p. 46, have to disable timer before load counter,
	 * may cause sync problem.
	 */
	ctrl &= ~APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	udelay(1);
	pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
	apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
	ctrl |= APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	return 0;
}

static int apbt_resume(struct clock_event_device *evt)
{
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);

	pr_debug("%s CPU %d state=resume\n", __func__,
		 cpumask_first(evt->cpumask));

	apbt_enable_int(&dw_ced->timer);
	return 0;
}

static int apbt_next_event(unsigned long delta,
			   struct clock_event_device *evt)
{
	u32 ctrl;
	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);

	/* Disable timer */
	ctrl = apbt_readl_relaxed(&dw_ced->timer, APBTMR_N_CONTROL);
	ctrl &= ~APBTMR_CONTROL_ENABLE;
	apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	/* write new count */
	apbt_writel_relaxed(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
	ctrl |= APBTMR_CONTROL_ENABLE;
	apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);

	return 0;
}

/**
 * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
 *
 * @cpu:	The CPU the events will be targeted at or -1 if CPU affiliation
 *		isn't required.
 * @name:	The name used for the timer and the IRQ for it.
 * @rating:	The rating to give the timer.
 * @base:	I/O base for the timer registers.
 * @irq:	The interrupt number to use for the timer.
 * @freq:	The frequency that the timer counts at.
 *
 * This creates a clock_event_device for using with the generic clock layer
 * but does not start and register it.  This should be done with
 * dw_apb_clockevent_register() as the next step.  If this is the first time
 * it has been called for a timer then the IRQ will be requested, if not it
 * just be enabled to allow CPU hotplug to avoid repeatedly requesting and
 * releasing the IRQ.
 */
struct dw_apb_clock_event_device *
dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
		       void __iomem *base, int irq, unsigned long freq)
{
	struct dw_apb_clock_event_device *dw_ced =
		kzalloc(sizeof(*dw_ced), GFP_KERNEL);
	int err;

	if (!dw_ced)
		return NULL;

	dw_ced->timer.base = base;
	dw_ced->timer.irq = irq;
	dw_ced->timer.freq = freq;

	clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
	dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
						       &dw_ced->ced);
	dw_ced->ced.max_delta_ticks = 0x7fffffff;
	dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
	dw_ced->ced.min_delta_ticks = 5000;
	dw_ced->ced.cpumask = cpu < 0 ? cpu_possible_mask : cpumask_of(cpu);
	dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC |
				CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
	dw_ced->ced.set_state_shutdown = apbt_shutdown;
	dw_ced->ced.set_state_periodic = apbt_set_periodic;
	dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
	dw_ced->ced.set_state_oneshot_stopped = apbt_shutdown;
	dw_ced->ced.tick_resume = apbt_resume;
	dw_ced->ced.set_next_event = apbt_next_event;
	dw_ced->ced.irq = dw_ced->timer.irq;
	dw_ced->ced.rating = rating;
	dw_ced->ced.name = name;

	dw_ced->irqaction.name		= dw_ced->ced.name;
	dw_ced->irqaction.handler	= dw_apb_clockevent_irq;
	dw_ced->irqaction.dev_id	= &dw_ced->ced;
	dw_ced->irqaction.irq		= irq;
	dw_ced->irqaction.flags		= IRQF_TIMER | IRQF_IRQPOLL |
					  IRQF_NOBALANCING;

	dw_ced->eoi = apbt_eoi;
	err = setup_irq(irq, &dw_ced->irqaction);
	if (err) {
		pr_err("failed to request timer irq\n");
		kfree(dw_ced);
		dw_ced = NULL;
	}

	return dw_ced;
}

/**
 * dw_apb_clockevent_resume() - resume a clock that has been paused.
 *
 * @dw_ced:	The APB clock to resume.
 */
void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
{
	enable_irq(dw_ced->timer.irq);
}

/**
 * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
 *
 * @dw_ced:	The APB clock to stop generating the events.
 */
void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
{
	free_irq(dw_ced->timer.irq, &dw_ced->ced);
}

/**
 * dw_apb_clockevent_register() - register the clock with the generic layer
 *
 * @dw_ced:	The APB clock to register as a clock_event_device.
 */
void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
{
	apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
	clockevents_register_device(&dw_ced->ced);
	apbt_enable_int(&dw_ced->timer);
}

/**
 * dw_apb_clocksource_start() - start the clocksource counting.
 *
 * @dw_cs:	The clocksource to start.
 *
 * This is used to start the clocksource before registration and can be used
 * to enable calibration of timers.
 */
void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
{
	/*
	 * start count down from 0xffff_ffff. this is done by toggling the
	 * enable bit then load initial load count to ~0.
	 */
	u32 ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);

	ctrl &= ~APBTMR_CONTROL_ENABLE;
	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
	apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
	/* enable, mask interrupt */
	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
	ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
	/* read it once to get cached counter value initialized */
	dw_apb_clocksource_read(dw_cs);
}

static u64 __apbt_read_clocksource(struct clocksource *cs)
{
	u32 current_count;
	struct dw_apb_clocksource *dw_cs =
		clocksource_to_dw_apb_clocksource(cs);

	current_count = apbt_readl_relaxed(&dw_cs->timer,
					APBTMR_N_CURRENT_VALUE);

	return (u64)~current_count;
}

static void apbt_restart_clocksource(struct clocksource *cs)
{
	struct dw_apb_clocksource *dw_cs =
		clocksource_to_dw_apb_clocksource(cs);

	dw_apb_clocksource_start(dw_cs);
}

/**
 * dw_apb_clocksource_init() - use an APB timer as a clocksource.
 *
 * @rating:	The rating to give the clocksource.
 * @name:	The name for the clocksource.
 * @base:	The I/O base for the timer registers.
 * @freq:	The frequency that the timer counts at.
 *
 * This creates a clocksource using an APB timer but does not yet register it
 * with the clocksource system.  This should be done with
 * dw_apb_clocksource_register() as the next step.
 */
struct dw_apb_clocksource *
dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
			unsigned long freq)
{
	struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL);

	if (!dw_cs)
		return NULL;

	dw_cs->timer.base = base;
	dw_cs->timer.freq = freq;
	dw_cs->cs.name = name;
	dw_cs->cs.rating = rating;
	dw_cs->cs.read = __apbt_read_clocksource;
	dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
	dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	dw_cs->cs.resume = apbt_restart_clocksource;

	return dw_cs;
}

/**
 * dw_apb_clocksource_register() - register the APB clocksource.
 *
 * @dw_cs:	The clocksource to register.
 */
void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
{
	clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
}

/**
 * dw_apb_clocksource_read() - read the current value of a clocksource.
 *
 * @dw_cs:	The clocksource to read.
 */
u64 dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
{
	return (u64)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
}
Commit	Line	Data
06c3df49 JI	1	/*
	2	* (C) Copyright 2009 Intel Corporation
	3	* Author: Jacob Pan (jacob.jun.pan@intel.com)
	4	*
	5	* Shared with ARM platforms, Jamie Iles, Picochip 2011
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Support for the Synopsys DesignWare APB Timers.
	12	*/
	13	#include <linux/dw_apb_timer.h>
	14	#include <linux/delay.h>
	15	#include <linux/kernel.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/io.h>
	19	#include <linux/slab.h>
	20
	21	#define APBT_MIN_PERIOD 4
	22	#define APBT_MIN_DELTA_USEC 200
	23
d3d8fee4 JS	24	#define APBTMR_N_LOAD_COUNT 0x00
	25	#define APBTMR_N_CURRENT_VALUE 0x04
	26	#define APBTMR_N_CONTROL 0x08
	27	#define APBTMR_N_EOI 0x0c
	28	#define APBTMR_N_INT_STATUS 0x10
	29
06c3df49 JI	30	#define APBTMRS_INT_STATUS 0xa0
	31	#define APBTMRS_EOI 0xa4
	32	#define APBTMRS_RAW_INT_STATUS 0xa8
	33	#define APBTMRS_COMP_VERSION 0xac
	34
	35	#define APBTMR_CONTROL_ENABLE (1 << 0)
	36	/* 1: periodic, 0:free running. */
	37	#define APBTMR_CONTROL_MODE_PERIODIC (1 << 1)
	38	#define APBTMR_CONTROL_INT (1 << 2)
	39
	40	static inline struct dw_apb_clock_event_device *
	41	ced_to_dw_apb_ced(struct clock_event_device *evt)
	42	{
	43	return container_of(evt, struct dw_apb_clock_event_device, ced);
	44	}
	45
	46	static inline struct dw_apb_clocksource *
	47	clocksource_to_dw_apb_clocksource(struct clocksource *cs)
	48	{
	49	return container_of(cs, struct dw_apb_clocksource, cs);
	50	}
	51
520ddad4	52	static inline u32 apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
06c3df49 JI	53	{
	54	return readl(timer->base + offs);
	55	}
	56
520ddad4 JZ	57	static inline void apbt_writel(struct dw_apb_timer *timer, u32 val,
520ddad4 JZ	58	unsigned long offs)
06c3df49 JI	59	{
	60	writel(val, timer->base + offs);
	61	}
	62
39d3611f JZ	63	static inline u32 apbt_readl_relaxed(struct dw_apb_timer *timer, unsigned long offs)
	64	{
	65	return readl_relaxed(timer->base + offs);
	66	}
	67
	68	static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val,
	69	unsigned long offs)
	70	{
	71	writel_relaxed(val, timer->base + offs);
	72	}
	73
06c3df49 JI	74	static void apbt_disable_int(struct dw_apb_timer *timer)
06c3df49 JI	75	{
9f4165dc	76	u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
06c3df49 JI	77
	78	ctrl \|= APBTMR_CONTROL_INT;
	79	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
	80	}
	81
	82	/**
	83	* dw_apb_clockevent_pause() - stop the clock_event_device from running
	84	*
	85	* @dw_ced: The APB clock to stop generating events.
	86	*/
	87	void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
	88	{
	89	disable_irq(dw_ced->timer.irq);
	90	apbt_disable_int(&dw_ced->timer);
	91	}
	92
	93	static void apbt_eoi(struct dw_apb_timer *timer)
	94	{
39d3611f	95	apbt_readl_relaxed(timer, APBTMR_N_EOI);
06c3df49 JI	96	}
	97
	98	static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
	99	{
	100	struct clock_event_device *evt = data;
	101	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	102
	103	if (!evt->event_handler) {
ac9ce6d1	104	pr_info("Spurious APBT timer interrupt %d\n", irq);
06c3df49 JI	105	return IRQ_NONE;
	106	}
	107
	108	if (dw_ced->eoi)
	109	dw_ced->eoi(&dw_ced->timer);
	110
	111	evt->event_handler(evt);
	112	return IRQ_HANDLED;
	113	}
	114
	115	static void apbt_enable_int(struct dw_apb_timer *timer)
	116	{
9f4165dc	117	u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
06c3df49 JI	118	/* clear pending intr */
	119	apbt_readl(timer, APBTMR_N_EOI);
	120	ctrl &= ~APBTMR_CONTROL_INT;
	121	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
	122	}
	123
226be92b	124	static int apbt_shutdown(struct clock_event_device *evt)
06c3df49	125	{
226be92b	126	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
9f4165dc	127	u32 ctrl;
226be92b VK	128
	129	pr_debug("%s CPU %d state=shutdown\n", __func__,
	130	cpumask_first(evt->cpumask));
	131
	132	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	133	ctrl &= ~APBTMR_CONTROL_ENABLE;
	134	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	135	return 0;
	136	}
	137
	138	static int apbt_set_oneshot(struct clock_event_device *evt)
	139	{
06c3df49	140	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
9f4165dc	141	u32 ctrl;
06c3df49	142
226be92b VK	143	pr_debug("%s CPU %d state=oneshot\n", __func__,
	144	cpumask_first(evt->cpumask));
	145
	146	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	147	/*
	148	* set free running mode, this mode will let timer reload max
	149	* timeout which will give time (3min on 25MHz clock) to rearm
	150	* the next event, therefore emulate the one-shot mode.
	151	*/
	152	ctrl &= ~APBTMR_CONTROL_ENABLE;
	153	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
	154
	155	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	156	/* write again to set free running mode */
	157	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	158
	159	/*
	160	* DW APB p. 46, load counter with all 1s before starting free
	161	* running mode.
	162	*/
	163	apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
	164	ctrl &= ~APBTMR_CONTROL_INT;
	165	ctrl \|= APBTMR_CONTROL_ENABLE;
	166	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	167	return 0;
	168	}
	169
	170	static int apbt_set_periodic(struct clock_event_device *evt)
	171	{
	172	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	173	unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
9f4165dc	174	u32 ctrl;
226be92b VK	175
	176	pr_debug("%s CPU %d state=periodic\n", __func__,
	177	cpumask_first(evt->cpumask));
	178
	179	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
	180	ctrl \|= APBTMR_CONTROL_MODE_PERIODIC;
	181	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	182	/*
	183	* DW APB p. 46, have to disable timer before load counter,
	184	* may cause sync problem.
	185	*/
	186	ctrl &= ~APBTMR_CONTROL_ENABLE;
	187	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	188	udelay(1);
	189	pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
	190	apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
	191	ctrl \|= APBTMR_CONTROL_ENABLE;
	192	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
	193	return 0;
	194	}
	195
	196	static int apbt_resume(struct clock_event_device *evt)
	197	{
	198	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	199
	200	pr_debug("%s CPU %d state=resume\n", __func__,
	201	cpumask_first(evt->cpumask));
	202
	203	apbt_enable_int(&dw_ced->timer);
	204	return 0;
06c3df49 JI	205	}
	206
	207	static int apbt_next_event(unsigned long delta,
	208	struct clock_event_device *evt)
	209	{
9f4165dc	210	u32 ctrl;
06c3df49 JI	211	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
	212
	213	/* Disable timer */
39d3611f	214	ctrl = apbt_readl_relaxed(&dw_ced->timer, APBTMR_N_CONTROL);
06c3df49	215	ctrl &= ~APBTMR_CONTROL_ENABLE;
39d3611f	216	apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
06c3df49	217	/* write new count */
39d3611f	218	apbt_writel_relaxed(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
06c3df49	219	ctrl \|= APBTMR_CONTROL_ENABLE;
39d3611f	220	apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
06c3df49 JI	221
	222	return 0;
	223	}
	224
	225	/**
	226	* dw_apb_clockevent_init() - use an APB timer as a clock_event_device
	227	*
9580a652 SS	228	* @cpu: The CPU the events will be targeted at or -1 if CPU affiliation
9580a652 SS	229	* isn't required.
06c3df49 JI	230	* @name: The name used for the timer and the IRQ for it.
	231	* @rating: The rating to give the timer.
	232	* @base: I/O base for the timer registers.
	233	* @irq: The interrupt number to use for the timer.
	234	* @freq: The frequency that the timer counts at.
	235	*
	236	* This creates a clock_event_device for using with the generic clock layer
	237	* but does not start and register it. This should be done with
	238	* dw_apb_clockevent_register() as the next step. If this is the first time
	239	* it has been called for a timer then the IRQ will be requested, if not it
	240	* just be enabled to allow CPU hotplug to avoid repeatedly requesting and
	241	* releasing the IRQ.
	242	*/
	243	struct dw_apb_clock_event_device *
	244	dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
	245	void __iomem *base, int irq, unsigned long freq)
	246	{
	247	struct dw_apb_clock_event_device *dw_ced =
	248	kzalloc(sizeof(*dw_ced), GFP_KERNEL);
	249	int err;
	250
	251	if (!dw_ced)
	252	return NULL;
	253
	254	dw_ced->timer.base = base;
	255	dw_ced->timer.irq = irq;
	256	dw_ced->timer.freq = freq;
	257
	258	clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
	259	dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
	260	&dw_ced->ced);
8317b53f	261	dw_ced->ced.max_delta_ticks = 0x7fffffff;
06c3df49	262	dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
8317b53f	263	dw_ced->ced.min_delta_ticks = 5000;
9580a652	264	dw_ced->ced.cpumask = cpu < 0 ? cpu_possible_mask : cpumask_of(cpu);
8b5f0010 JZ	265	dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC \|
8b5f0010 JZ	266	CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_DYNIRQ;
226be92b VK	267	dw_ced->ced.set_state_shutdown = apbt_shutdown;
	268	dw_ced->ced.set_state_periodic = apbt_set_periodic;
	269	dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
45735326	270	dw_ced->ced.set_state_oneshot_stopped = apbt_shutdown;
226be92b	271	dw_ced->ced.tick_resume = apbt_resume;
06c3df49 JI	272	dw_ced->ced.set_next_event = apbt_next_event;
	273	dw_ced->ced.irq = dw_ced->timer.irq;
	274	dw_ced->ced.rating = rating;
	275	dw_ced->ced.name = name;
	276
	277	dw_ced->irqaction.name = dw_ced->ced.name;
	278	dw_ced->irqaction.handler = dw_apb_clockevent_irq;
	279	dw_ced->irqaction.dev_id = &dw_ced->ced;
	280	dw_ced->irqaction.irq = irq;
	281	dw_ced->irqaction.flags = IRQF_TIMER \| IRQF_IRQPOLL \|
38c30a84	282	IRQF_NOBALANCING;
06c3df49 JI	283
	284	dw_ced->eoi = apbt_eoi;
	285	err = setup_irq(irq, &dw_ced->irqaction);
	286	if (err) {
	287	pr_err("failed to request timer irq\n");
	288	kfree(dw_ced);
	289	dw_ced = NULL;
	290	}
	291
	292	return dw_ced;
	293	}
	294
	295	/**
	296	* dw_apb_clockevent_resume() - resume a clock that has been paused.
	297	*
	298	* @dw_ced: The APB clock to resume.
	299	*/
	300	void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
	301	{
	302	enable_irq(dw_ced->timer.irq);
	303	}
	304
	305	/**
	306	* dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
	307	*
	308	* @dw_ced: The APB clock to stop generating the events.
	309	*/
	310	void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
	311	{
	312	free_irq(dw_ced->timer.irq, &dw_ced->ced);
	313	}
	314
	315	/**
	316	* dw_apb_clockevent_register() - register the clock with the generic layer
	317	*
	318	* @dw_ced: The APB clock to register as a clock_event_device.
	319	*/
	320	void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
	321	{
	322	apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
	323	clockevents_register_device(&dw_ced->ced);
	324	apbt_enable_int(&dw_ced->timer);
	325	}
	326
	327	/**
	328	* dw_apb_clocksource_start() - start the clocksource counting.
	329	*
	330	* @dw_cs: The clocksource to start.
	331	*
	332	* This is used to start the clocksource before registration and can be used
	333	* to enable calibration of timers.
	334	*/
	335	void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
	336	{
	337	/*
	338	* start count down from 0xffff_ffff. this is done by toggling the
	339	* enable bit then load initial load count to ~0.
	340	*/
9f4165dc	341	u32 ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
06c3df49 JI	342
	343	ctrl &= ~APBTMR_CONTROL_ENABLE;
	344	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
	345	apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
	346	/* enable, mask interrupt */
	347	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
	348	ctrl \|= (APBTMR_CONTROL_ENABLE \| APBTMR_CONTROL_INT);
	349	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
	350	/* read it once to get cached counter value initialized */
	351	dw_apb_clocksource_read(dw_cs);
	352	}
	353
a5a1d1c2	354	static u64 __apbt_read_clocksource(struct clocksource *cs)
06c3df49	355	{
9f4165dc	356	u32 current_count;
06c3df49 JI	357	struct dw_apb_clocksource *dw_cs =
	358	clocksource_to_dw_apb_clocksource(cs);
	359
39d3611f JZ	360	current_count = apbt_readl_relaxed(&dw_cs->timer,
39d3611f JZ	361	APBTMR_N_CURRENT_VALUE);
06c3df49	362
a5a1d1c2	363	return (u64)~current_count;
06c3df49 JI	364	}
	365
	366	static void apbt_restart_clocksource(struct clocksource *cs)
	367	{
	368	struct dw_apb_clocksource *dw_cs =
	369	clocksource_to_dw_apb_clocksource(cs);
	370
	371	dw_apb_clocksource_start(dw_cs);
	372	}
	373
	374	/**
	375	* dw_apb_clocksource_init() - use an APB timer as a clocksource.
	376	*
	377	* @rating: The rating to give the clocksource.
	378	* @name: The name for the clocksource.
	379	* @base: The I/O base for the timer registers.
	380	* @freq: The frequency that the timer counts at.
	381	*
	382	* This creates a clocksource using an APB timer but does not yet register it
	383	* with the clocksource system. This should be done with
	384	* dw_apb_clocksource_register() as the next step.
	385	*/
	386	struct dw_apb_clocksource *
a1330228	387	dw_apb_clocksource_init(unsigned rating, const char name, void __iomem base,
06c3df49 JI	388	unsigned long freq)
	389	{
	390	struct dw_apb_clocksource dw_cs = kzalloc(sizeof(dw_cs), GFP_KERNEL);
	391
	392	if (!dw_cs)
	393	return NULL;
	394
	395	dw_cs->timer.base = base;
	396	dw_cs->timer.freq = freq;
	397	dw_cs->cs.name = name;
	398	dw_cs->cs.rating = rating;
	399	dw_cs->cs.read = __apbt_read_clocksource;
	400	dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
	401	dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	402	dw_cs->cs.resume = apbt_restart_clocksource;
	403
	404	return dw_cs;
	405	}
	406
	407	/**
	408	* dw_apb_clocksource_register() - register the APB clocksource.
	409	*
	410	* @dw_cs: The clocksource to register.
	411	*/
	412	void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
	413	{
	414	clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
	415	}
	416
	417	/**
	418	* dw_apb_clocksource_read() - read the current value of a clocksource.
	419	*
	420	* @dw_cs: The clocksource to read.
	421	*/
a5a1d1c2	422	u64 dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
06c3df49	423	{
a5a1d1c2	424	return (u64)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
06c3df49	425	}