[people/arne_f/kernel.git] / drivers / clocksource / timer-atmel-pit.c

/*
 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
 *
 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
 * Revision	 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
 * Converted to ClockSource/ClockEvents by David Brownell.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	"AT91: PIT: " fmt

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>

#define AT91_PIT_MR		0x00			/* Mode Register */
#define AT91_PIT_PITIEN			BIT(25)			/* Timer Interrupt Enable */
#define AT91_PIT_PITEN			BIT(24)			/* Timer Enabled */
#define AT91_PIT_PIV			GENMASK(19, 0)		/* Periodic Interval Value */

#define AT91_PIT_SR		0x04			/* Status Register */
#define AT91_PIT_PITS			BIT(0)			/* Timer Status */

#define AT91_PIT_PIVR		0x08			/* Periodic Interval Value Register */
#define AT91_PIT_PIIR		0x0c			/* Periodic Interval Image Register */
#define AT91_PIT_PICNT			GENMASK(31, 20)		/* Interval Counter */
#define AT91_PIT_CPIV			GENMASK(19, 0)		/* Inverval Value */

#define PIT_CPIV(x)	((x) & AT91_PIT_CPIV)
#define PIT_PICNT(x)	(((x) & AT91_PIT_PICNT) >> 20)

struct pit_data {
	struct clock_event_device	clkevt;
	struct clocksource		clksrc;

	void __iomem	*base;
	u32		cycle;
	u32		cnt;
	unsigned int	irq;
	struct clk	*mck;
};

static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc)
{
	return container_of(clksrc, struct pit_data, clksrc);
}

static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clkevt)
{
	return container_of(clkevt, struct pit_data, clkevt);
}

static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
{
	return readl_relaxed(base + reg_offset);
}

static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
{
	writel_relaxed(value, base + reg_offset);
}

/*
 * Clocksource:  just a monotonic counter of MCK/16 cycles.
 * We don't care whether or not PIT irqs are enabled.
 */
static u64 read_pit_clk(struct clocksource *cs)
{
	struct pit_data *data = clksrc_to_pit_data(cs);
	unsigned long flags;
	u32 elapsed;
	u32 t;

	raw_local_irq_save(flags);
	elapsed = data->cnt;
	t = pit_read(data->base, AT91_PIT_PIIR);
	raw_local_irq_restore(flags);

	elapsed += PIT_PICNT(t) * data->cycle;
	elapsed += PIT_CPIV(t);
	return elapsed;
}

static int pit_clkevt_shutdown(struct clock_event_device *dev)
{
	struct pit_data *data = clkevt_to_pit_data(dev);

	/* disable irq, leaving the clocksource active */
	pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN);
	return 0;
}

/*
 * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
 */
static int pit_clkevt_set_periodic(struct clock_event_device *dev)
{
	struct pit_data *data = clkevt_to_pit_data(dev);

	/* update clocksource counter */
	data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
	pit_write(data->base, AT91_PIT_MR,
		  (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN);
	return 0;
}

static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
{
	struct pit_data *data = clkevt_to_pit_data(cedev);

	/* Disable timer */
	pit_write(data->base, AT91_PIT_MR, 0);
}

static void at91sam926x_pit_reset(struct pit_data *data)
{
	/* Disable timer and irqs */
	pit_write(data->base, AT91_PIT_MR, 0);

	/* Clear any pending interrupts, wait for PIT to stop counting */
	while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)
		cpu_relax();

	/* Start PIT but don't enable IRQ */
	pit_write(data->base, AT91_PIT_MR,
		  (data->cycle - 1) | AT91_PIT_PITEN);
}

static void at91sam926x_pit_resume(struct clock_event_device *cedev)
{
	struct pit_data *data = clkevt_to_pit_data(cedev);

	at91sam926x_pit_reset(data);
}

/*
 * IRQ handler for the timer.
 */
static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
{
	struct pit_data *data = dev_id;

	/* The PIT interrupt may be disabled, and is shared */
	if (clockevent_state_periodic(&data->clkevt) &&
	    (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {
		/* Get number of ticks performed before irq, and ack it */
		data->cnt += data->cycle * PIT_PICNT(pit_read(data->base,
							      AT91_PIT_PIVR));
		data->clkevt.event_handler(&data->clkevt);

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

/*
 * Set up both clocksource and clockevent support.
 */
static int __init at91sam926x_pit_dt_init(struct device_node *node)
{
	unsigned long   pit_rate;
	unsigned        bits;
	int             ret;
	struct pit_data *data;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->base = of_iomap(node, 0);
	if (!data->base) {
		pr_err("Could not map PIT address\n");
		ret = -ENXIO;
		goto exit;
	}

	data->mck = of_clk_get(node, 0);
	if (IS_ERR(data->mck)) {
		pr_err("Unable to get mck clk\n");
		ret = PTR_ERR(data->mck);
		goto exit;
	}

	ret = clk_prepare_enable(data->mck);
	if (ret) {
		pr_err("Unable to enable mck\n");
		goto exit;
	}

	/* Get the interrupts property */
	data->irq = irq_of_parse_and_map(node, 0);
	if (!data->irq) {
		pr_err("Unable to get IRQ from DT\n");
		ret = -EINVAL;
		goto exit;
	}

	/*
	 * Use our actual MCK to figure out how many MCK/16 ticks per
	 * 1/HZ period (instead of a compile-time constant LATCH).
	 */
	pit_rate = clk_get_rate(data->mck) / 16;
	data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);
	WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);

	/* Initialize and enable the timer */
	at91sam926x_pit_reset(data);

	/*
	 * Register clocksource.  The high order bits of PIV are unused,
	 * so this isn't a 32-bit counter unless we get clockevent irqs.
	 */
	bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */;
	data->clksrc.mask = CLOCKSOURCE_MASK(bits);
	data->clksrc.name = "pit";
	data->clksrc.rating = 175;
	data->clksrc.read = read_pit_clk;
	data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	
	ret = clocksource_register_hz(&data->clksrc, pit_rate);
	if (ret) {
		pr_err("Failed to register clocksource\n");
		goto exit;
	}

	/* Set up irq handler */
	ret = request_irq(data->irq, at91sam926x_pit_interrupt,
			  IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
			  "at91_tick", data);
	if (ret) {
		pr_err("Unable to setup IRQ\n");
		clocksource_unregister(&data->clksrc);
		goto exit;
	}

	/* Set up and register clockevents */
	data->clkevt.name = "pit";
	data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
	data->clkevt.shift = 32;
	data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);
	data->clkevt.rating = 100;
	data->clkevt.cpumask = cpumask_of(0);

	data->clkevt.set_state_shutdown = pit_clkevt_shutdown;
	data->clkevt.set_state_periodic = pit_clkevt_set_periodic;
	data->clkevt.resume = at91sam926x_pit_resume;
	data->clkevt.suspend = at91sam926x_pit_suspend;
	clockevents_register_device(&data->clkevt);

	return 0;

exit:
	kfree(data);
	return ret;
}
TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
		       at91sam926x_pit_dt_init);
Commit	Line	Data
1a0ed732	1	/*
ad48ce74	2	* at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
1a0ed732 AV	3	*
	4	* Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
	5	* Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
ad48ce74	6	* Converted to ClockSource/ClockEvents by David Brownell.
1a0ed732 AV	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
52c3ffb0	12
cffbfe63 MR	13	#define pr_fmt(fmt) "AT91: PIT: " fmt
cffbfe63 MR	14
52c3ffb0 MR	15	#include <linux/clk.h>
52c3ffb0 MR	16	#include <linux/clockchips.h>
1a0ed732 AV	17	#include <linux/interrupt.h>
	18	#include <linux/irq.h>
	19	#include <linux/kernel.h>
23fa648f JCPV	20	#include <linux/of.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_irq.h>
64568d1d	23	#include <linux/slab.h>
1a0ed732	24
ffe5cd8e	25	#define AT91_PIT_MR 0x00 /* Mode Register */
52c3ffb0 MR	26	#define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */
	27	#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
	28	#define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */
ffe5cd8e JCPV	29
ffe5cd8e JCPV	30	#define AT91_PIT_SR 0x04 /* Status Register */
52c3ffb0	31	#define AT91_PIT_PITS BIT(0) /* Timer Status */
ffe5cd8e JCPV	32
	33	#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
	34	#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
52c3ffb0 MR	35	#define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */
52c3ffb0 MR	36	#define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */
1a0ed732 AV	37
	38	#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
	39	#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
	40
64568d1d MR	41	struct pit_data {
	42	struct clock_event_device clkevt;
	43	struct clocksource clksrc;
ad48ce74	44
64568d1d MR	45	void __iomem *base;
	46	u32 cycle;
	47	u32 cnt;
	48	unsigned int irq;
	49	struct clk *mck;
	50	};
	51
	52	static inline struct pit_data clksrc_to_pit_data(struct clocksource clksrc)
4ab0c599	53	{
64568d1d	54	return container_of(clksrc, struct pit_data, clksrc);
4ab0c599 JCPV	55	}
4ab0c599 JCPV	56
64568d1d	57	static inline struct pit_data clkevt_to_pit_data(struct clock_event_device clkevt)
4ab0c599	58	{
64568d1d MR	59	return container_of(clkevt, struct pit_data, clkevt);
	60	}
	61
	62	static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
	63	{
4806c87f	64	return readl_relaxed(base + reg_offset);
64568d1d MR	65	}
	66
	67	static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
	68	{
4806c87f	69	writel_relaxed(value, base + reg_offset);
4ab0c599	70	}
ad48ce74	71
1a0ed732	72	/*
ad48ce74 AV	73	* Clocksource: just a monotonic counter of MCK/16 cycles.
ad48ce74 AV	74	* We don't care whether or not PIT irqs are enabled.
1a0ed732	75	*/
a5a1d1c2	76	static u64 read_pit_clk(struct clocksource *cs)
1a0ed732	77	{
64568d1d	78	struct pit_data *data = clksrc_to_pit_data(cs);
ad48ce74 AV	79	unsigned long flags;
	80	u32 elapsed;
	81	u32 t;
	82
	83	raw_local_irq_save(flags);
64568d1d MR	84	elapsed = data->cnt;
64568d1d MR	85	t = pit_read(data->base, AT91_PIT_PIIR);
ad48ce74 AV	86	raw_local_irq_restore(flags);
ad48ce74 AV	87
64568d1d	88	elapsed += PIT_PICNT(t) * data->cycle;
ad48ce74 AV	89	elapsed += PIT_CPIV(t);
	90	return elapsed;
	91	}
	92
85250fb8 VK	93	static int pit_clkevt_shutdown(struct clock_event_device *dev)
	94	{
	95	struct pit_data *data = clkevt_to_pit_data(dev);
	96
	97	/* disable irq, leaving the clocksource active */
	98	pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) \| AT91_PIT_PITEN);
	99	return 0;
	100	}
	101
ad48ce74 AV	102	/*
	103	* Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
	104	*/
85250fb8	105	static int pit_clkevt_set_periodic(struct clock_event_device *dev)
ad48ce74	106	{
64568d1d MR	107	struct pit_data *data = clkevt_to_pit_data(dev);
64568d1d MR	108
85250fb8 VK	109	/* update clocksource counter */
	110	data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
	111	pit_write(data->base, AT91_PIT_MR,
	112	(data->cycle - 1) \| AT91_PIT_PITEN \| AT91_PIT_PITIEN);
	113	return 0;
1a0ed732 AV	114	}
1a0ed732 AV	115
49356ae9 SW	116	static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
49356ae9 SW	117	{
64568d1d MR	118	struct pit_data *data = clkevt_to_pit_data(cedev);
64568d1d MR	119
49356ae9	120	/* Disable timer */
64568d1d	121	pit_write(data->base, AT91_PIT_MR, 0);
49356ae9 SW	122	}
49356ae9 SW	123
64568d1d	124	static void at91sam926x_pit_reset(struct pit_data *data)
49356ae9 SW	125	{
49356ae9 SW	126	/* Disable timer and irqs */
64568d1d	127	pit_write(data->base, AT91_PIT_MR, 0);
49356ae9 SW	128
49356ae9 SW	129	/* Clear any pending interrupts, wait for PIT to stop counting */
64568d1d	130	while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)
49356ae9 SW	131	cpu_relax();
	132
	133	/* Start PIT but don't enable IRQ */
64568d1d MR	134	pit_write(data->base, AT91_PIT_MR,
64568d1d MR	135	(data->cycle - 1) \| AT91_PIT_PITEN);
49356ae9 SW	136	}
	137
	138	static void at91sam926x_pit_resume(struct clock_event_device *cedev)
	139	{
64568d1d	140	struct pit_data *data = clkevt_to_pit_data(cedev);
ad48ce74	141
64568d1d MR	142	at91sam926x_pit_reset(data);
64568d1d MR	143	}
ad48ce74	144
1a0ed732 AV	145	/*
	146	* IRQ handler for the timer.
	147	*/
ad48ce74	148	static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
1a0ed732	149	{
64568d1d MR	150	struct pit_data *data = dev_id;
64568d1d MR	151
ad48ce74	152	/* The PIT interrupt may be disabled, and is shared */
85250fb8	153	if (clockevent_state_periodic(&data->clkevt) &&
64568d1d	154	(pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {
ad48ce74	155	/* Get number of ticks performed before irq, and ack it */
2783e5d6 AB	156	data->cnt += data->cycle * PIT_PICNT(pit_read(data->base,
	157	AT91_PIT_PIVR));
	158	data->clkevt.event_handler(&data->clkevt);
1a0ed732	159
1a0ed732	160	return IRQ_HANDLED;
ad48ce74 AV	161	}
	162
	163	return IRQ_NONE;
1a0ed732 AV	164	}
1a0ed732 AV	165
1a0ed732	166	/*
ad48ce74	167	* Set up both clocksource and clockevent support.
1a0ed732	168	*/
a17686c4	169	static int __init at91sam926x_pit_dt_init(struct device_node *node)
1a0ed732	170	{
a17686c4 AB	171	unsigned long pit_rate;
	172	unsigned bits;
	173	int ret;
	174	struct pit_data *data;
	175
	176	data = kzalloc(sizeof(*data), GFP_KERNEL);
	177	if (!data)
	178	return -ENOMEM;
	179
	180	data->base = of_iomap(node, 0);
	181	if (!data->base) {
	182	pr_err("Could not map PIT address\n");
88736169 AB	183	ret = -ENXIO;
88736169 AB	184	goto exit;
a17686c4 AB	185	}
	186
	187	data->mck = of_clk_get(node, 0);
	188	if (IS_ERR(data->mck)) {
	189	pr_err("Unable to get mck clk\n");
88736169 AB	190	ret = PTR_ERR(data->mck);
88736169 AB	191	goto exit;
a17686c4 AB	192	}
	193
	194	ret = clk_prepare_enable(data->mck);
	195	if (ret) {
	196	pr_err("Unable to enable mck\n");
88736169	197	goto exit;
a17686c4 AB	198	}
	199
	200	/* Get the interrupts property */
	201	data->irq = irq_of_parse_and_map(node, 0);
	202	if (!data->irq) {
	203	pr_err("Unable to get IRQ from DT\n");
88736169 AB	204	ret = -EINVAL;
88736169 AB	205	goto exit;
a17686c4	206	}
ad48ce74 AV	207
	208	/*
	209	* Use our actual MCK to figure out how many MCK/16 ticks per
	210	* 1/HZ period (instead of a compile-time constant LATCH).
	211	*/
64568d1d MR	212	pit_rate = clk_get_rate(data->mck) / 16;
	213	data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);
	214	WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);
1a0ed732	215
ad48ce74	216	/* Initialize and enable the timer */
64568d1d	217	at91sam926x_pit_reset(data);
ad48ce74 AV	218
	219	/*
	220	* Register clocksource. The high order bits of PIV are unused,
	221	* so this isn't a 32-bit counter unless we get clockevent irqs.
	222	*/
64568d1d MR	223	bits = 12 /* PICNT / + ilog2(data->cycle) / PIV */;
	224	data->clksrc.mask = CLOCKSOURCE_MASK(bits);
	225	data->clksrc.name = "pit";
	226	data->clksrc.rating = 175;
005e5627 DL	227	data->clksrc.read = read_pit_clk;
005e5627 DL	228	data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
504f34c9 DL	229
	230	ret = clocksource_register_hz(&data->clksrc, pit_rate);
	231	if (ret) {
ac9ce6d1	232	pr_err("Failed to register clocksource\n");
88736169	233	goto exit;
504f34c9	234	}
ad48ce74 AV	235
ad48ce74 AV	236	/* Set up irq handler */
64568d1d	237	ret = request_irq(data->irq, at91sam926x_pit_interrupt,
7f282e01	238	IRQF_SHARED \| IRQF_TIMER \| IRQF_IRQPOLL,
64568d1d	239	"at91_tick", data);
504f34c9 DL	240	if (ret) {
504f34c9 DL	241	pr_err("Unable to setup IRQ\n");
88736169 AB	242	clocksource_unregister(&data->clksrc);
88736169 AB	243	goto exit;
504f34c9	244	}
ad48ce74 AV	245
ad48ce74 AV	246	/* Set up and register clockevents */
64568d1d MR	247	data->clkevt.name = "pit";
	248	data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
	249	data->clkevt.shift = 32;
	250	data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);
	251	data->clkevt.rating = 100;
	252	data->clkevt.cpumask = cpumask_of(0);
	253
85250fb8 VK	254	data->clkevt.set_state_shutdown = pit_clkevt_shutdown;
85250fb8 VK	255	data->clkevt.set_state_periodic = pit_clkevt_set_periodic;
64568d1d MR	256	data->clkevt.resume = at91sam926x_pit_resume;
	257	data->clkevt.suspend = at91sam926x_pit_suspend;
	258	clockevents_register_device(&data->clkevt);
504f34c9 DL	259
504f34c9 DL	260	return 0;
88736169 AB	261
	262	exit:
	263	kfree(data);
	264	return ret;
1a0ed732	265	}
17273395	266	TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
f807a89c	267	at91sam926x_pit_dt_init);