[people/arne_f/kernel.git] / drivers / clocksource / timer-integrator-ap.c

/*
 * Integrator/AP timer driver
 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
 * Copyright (c) 2014, Linaro Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/sched_clock.h>

#include "timer-sp.h"

static void __iomem * sched_clk_base;

static u64 notrace integrator_read_sched_clock(void)
{
	return -readl(sched_clk_base + TIMER_VALUE);
}

static int __init integrator_clocksource_init(unsigned long inrate,
					      void __iomem *base)
{
	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
	unsigned long rate = inrate;
	int ret;

	if (rate >= 1500000) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}

	writel(0xffff, base + TIMER_LOAD);
	writel(ctrl, base + TIMER_CTRL);

	ret = clocksource_mmio_init(base + TIMER_VALUE, "timer2",
				    rate, 200, 16, clocksource_mmio_readl_down);
	if (ret)
		return ret;

	sched_clk_base = base;
	sched_clock_register(integrator_read_sched_clock, 16, rate);

	return 0;
}

static unsigned long timer_reload;
static void __iomem * clkevt_base;

/*
 * IRQ handler for the timer
 */
static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int clkevt_shutdown(struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);
	return 0;
}

static int clkevt_set_oneshot(struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) &
		   ~(TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC);

	/* Leave the timer disabled, .set_next_event will enable it */
	writel(ctrl, clkevt_base + TIMER_CTRL);
	return 0;
}

static int clkevt_set_periodic(struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);

	/* Enable the timer and start the periodic tick */
	writel(timer_reload, clkevt_base + TIMER_LOAD);
	ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
	writel(ctrl, clkevt_base + TIMER_CTRL);
	return 0;
}

static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device integrator_clockevent = {
	.name			= "timer1",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown	= clkevt_shutdown,
	.set_state_periodic	= clkevt_set_periodic,
	.set_state_oneshot	= clkevt_set_oneshot,
	.tick_resume		= clkevt_shutdown,
	.set_next_event		= clkevt_set_next_event,
	.rating			= 300,
};

static struct irqaction integrator_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= integrator_timer_interrupt,
	.dev_id		= &integrator_clockevent,
};

static int integrator_clockevent_init(unsigned long inrate,
				      void __iomem *base, int irq)
{
	unsigned long rate = inrate;
	unsigned int ctrl = 0;
	int ret;

	clkevt_base = base;
	/* Calculate and program a divisor */
	if (rate > 0x100000 * HZ) {
		rate /= 256;
		ctrl |= TIMER_CTRL_DIV256;
	} else if (rate > 0x10000 * HZ) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}
	timer_reload = rate / HZ;
	writel(ctrl, clkevt_base + TIMER_CTRL);

	ret = setup_irq(irq, &integrator_timer_irq);
	if (ret)
		return ret;

	clockevents_config_and_register(&integrator_clockevent,
					rate,
					1,
					0xffffU);
	return 0;
}

static int __init integrator_ap_timer_init_of(struct device_node *node)
{
	const char *path;
	void __iomem *base;
	int err;
	int irq;
	struct clk *clk;
	unsigned long rate;
	struct device_node *alias_node;

	base = of_io_request_and_map(node, 0, "integrator-timer");
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("No clock for %s\n", node->name);
		return PTR_ERR(clk);
	}
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);
	writel(0, base + TIMER_CTRL);

	err = of_property_read_string(of_aliases,
				"arm,timer-primary", &path);
	if (err) {
		pr_warn("Failed to read property\n");
		return err;
	}

	alias_node = of_find_node_by_path(path);

	/*
	 * The pointer is used as an identifier not as a pointer, we
	 * can drop the refcount on the of__node immediately after
	 * getting it.
	 */
	of_node_put(alias_node);

	if (node == alias_node)
		/* The primary timer lacks IRQ, use as clocksource */
		return integrator_clocksource_init(rate, base);

	err = of_property_read_string(of_aliases,
				"arm,timer-secondary", &path);
	if (err) {
		pr_warn("Failed to read property\n");
		return err;
	}

	alias_node = of_find_node_by_path(path);

	of_node_put(alias_node);

	if (node == alias_node) {
		/* The secondary timer will drive the clock event */
		irq = irq_of_parse_and_map(node, 0);
		return integrator_clockevent_init(rate, base, irq);
	}

	pr_info("Timer @%p unused\n", base);
	clk_disable_unprepare(clk);

	return 0;
}

TIMER_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
		       integrator_ap_timer_init_of);
Commit	Line	Data
beb5818b LW	1	/*
	2	* Integrator/AP timer driver
	3	* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
	4	* Copyright (c) 2014, Linaro Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	#include <linux/clk.h>
	22	#include <linux/clocksource.h>
	23	#include <linux/of_irq.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_platform.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/sched_clock.h>
0b7402dc SH	29
0b7402dc SH	30	#include "timer-sp.h"
beb5818b LW	31
	32	static void __iomem * sched_clk_base;
	33
	34	static u64 notrace integrator_read_sched_clock(void)
	35	{
	36	return -readl(sched_clk_base + TIMER_VALUE);
	37	}
	38
8fce3dc5 AB	39	static int __init integrator_clocksource_init(unsigned long inrate,
8fce3dc5 AB	40	void __iomem *base)
beb5818b LW	41	{
	42	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;
	43	unsigned long rate = inrate;
76804d05	44	int ret;
beb5818b LW	45
	46	if (rate >= 1500000) {
	47	rate /= 16;
	48	ctrl \|= TIMER_CTRL_DIV16;
	49	}
	50
	51	writel(0xffff, base + TIMER_LOAD);
	52	writel(ctrl, base + TIMER_CTRL);
	53
76804d05 DL	54	ret = clocksource_mmio_init(base + TIMER_VALUE, "timer2",
	55	rate, 200, 16, clocksource_mmio_readl_down);
	56	if (ret)
	57	return ret;
beb5818b LW	58
	59	sched_clk_base = base;
	60	sched_clock_register(integrator_read_sched_clock, 16, rate);
76804d05 DL	61
76804d05 DL	62	return 0;
beb5818b LW	63	}
	64
	65	static unsigned long timer_reload;
	66	static void __iomem * clkevt_base;
	67
	68	/*
	69	* IRQ handler for the timer
	70	*/
	71	static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
	72	{
	73	struct clock_event_device *evt = dev_id;
	74
	75	/* clear the interrupt */
	76	writel(1, clkevt_base + TIMER_INTCLR);
	77
	78	evt->event_handler(evt);
	79
	80	return IRQ_HANDLED;
	81	}
	82
f710bdee	83	static int clkevt_shutdown(struct clock_event_device *evt)
beb5818b LW	84	{
	85	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	86
	87	/* Disable timer */
	88	writel(ctrl, clkevt_base + TIMER_CTRL);
f710bdee VK	89	return 0;
f710bdee VK	90	}
beb5818b	91
f710bdee VK	92	static int clkevt_set_oneshot(struct clock_event_device *evt)
	93	{
	94	u32 ctrl = readl(clkevt_base + TIMER_CTRL) &
	95	~(TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC);
	96
	97	/* Leave the timer disabled, .set_next_event will enable it */
	98	writel(ctrl, clkevt_base + TIMER_CTRL);
	99	return 0;
	100	}
beb5818b	101
f710bdee VK	102	static int clkevt_set_periodic(struct clock_event_device *evt)
	103	{
	104	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	105
	106	/* Disable timer */
	107	writel(ctrl, clkevt_base + TIMER_CTRL);
	108
	109	/* Enable the timer and start the periodic tick */
	110	writel(timer_reload, clkevt_base + TIMER_LOAD);
	111	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
	112	writel(ctrl, clkevt_base + TIMER_CTRL);
	113	return 0;
beb5818b LW	114	}
	115
	116	static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
	117	{
	118	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	119
	120	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	121	writel(next, clkevt_base + TIMER_LOAD);
	122	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	123
	124	return 0;
	125	}
	126
	127	static struct clock_event_device integrator_clockevent = {
f710bdee VK	128	.name = "timer1",
	129	.features = CLOCK_EVT_FEAT_PERIODIC \|
	130	CLOCK_EVT_FEAT_ONESHOT,
	131	.set_state_shutdown = clkevt_shutdown,
	132	.set_state_periodic = clkevt_set_periodic,
	133	.set_state_oneshot = clkevt_set_oneshot,
	134	.tick_resume = clkevt_shutdown,
	135	.set_next_event = clkevt_set_next_event,
	136	.rating = 300,
beb5818b LW	137	};
	138
	139	static struct irqaction integrator_timer_irq = {
	140	.name = "timer",
	141	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	142	.handler = integrator_timer_interrupt,
	143	.dev_id = &integrator_clockevent,
	144	};
	145
76804d05 DL	146	static int integrator_clockevent_init(unsigned long inrate,
76804d05 DL	147	void __iomem *base, int irq)
beb5818b LW	148	{
	149	unsigned long rate = inrate;
	150	unsigned int ctrl = 0;
76804d05	151	int ret;
beb5818b LW	152
	153	clkevt_base = base;
	154	/* Calculate and program a divisor */
	155	if (rate > 0x100000 * HZ) {
	156	rate /= 256;
	157	ctrl \|= TIMER_CTRL_DIV256;
	158	} else if (rate > 0x10000 * HZ) {
	159	rate /= 16;
	160	ctrl \|= TIMER_CTRL_DIV16;
	161	}
	162	timer_reload = rate / HZ;
	163	writel(ctrl, clkevt_base + TIMER_CTRL);
	164
76804d05 DL	165	ret = setup_irq(irq, &integrator_timer_irq);
	166	if (ret)
	167	return ret;
	168
beb5818b LW	169	clockevents_config_and_register(&integrator_clockevent,
	170	rate,
	171	1,
	172	0xffffU);
76804d05	173	return 0;
beb5818b LW	174	}
beb5818b LW	175
76804d05	176	static int __init integrator_ap_timer_init_of(struct device_node *node)
beb5818b LW	177	{
	178	const char *path;
	179	void __iomem *base;
	180	int err;
	181	int irq;
	182	struct clk *clk;
	183	unsigned long rate;
16df3ffc	184	struct device_node *alias_node;
beb5818b LW	185
beb5818b LW	186	base = of_io_request_and_map(node, 0, "integrator-timer");
bd580e7e	187	if (IS_ERR(base))
76804d05	188	return PTR_ERR(base);
beb5818b LW	189
	190	clk = of_clk_get(node, 0);
	191	if (IS_ERR(clk)) {
	192	pr_err("No clock for %s\n", node->name);
76804d05	193	return PTR_ERR(clk);
beb5818b LW	194	}
	195	clk_prepare_enable(clk);
	196	rate = clk_get_rate(clk);
	197	writel(0, base + TIMER_CTRL);
	198
	199	err = of_property_read_string(of_aliases,
	200	"arm,timer-primary", &path);
76804d05	201	if (err) {
ac9ce6d1	202	pr_warn("Failed to read property\n");
76804d05 DL	203	return err;
	204	}
	205
16df3ffc YL	206	alias_node = of_find_node_by_path(path);
	207
	208	/*
	209	* The pointer is used as an identifier not as a pointer, we
	210	* can drop the refcount on the of__node immediately after
	211	* getting it.
	212	*/
	213	of_node_put(alias_node);
	214
	215	if (node == alias_node)
	216	/* The primary timer lacks IRQ, use as clocksource */
	217	return integrator_clocksource_init(rate, base);
76804d05	218
beb5818b LW	219	err = of_property_read_string(of_aliases,
beb5818b LW	220	"arm,timer-secondary", &path);
76804d05	221	if (err) {
ac9ce6d1	222	pr_warn("Failed to read property\n");
76804d05 DL	223	return err;
	224	}
	225
16df3ffc	226	alias_node = of_find_node_by_path(path);
76804d05	227
16df3ffc	228	of_node_put(alias_node);
beb5818b	229
16df3ffc	230	if (node == alias_node) {
beb5818b LW	231	/* The secondary timer will drive the clock event */
beb5818b LW	232	irq = irq_of_parse_and_map(node, 0);
76804d05	233	return integrator_clockevent_init(rate, base, irq);
beb5818b LW	234	}
	235
	236	pr_info("Timer @%p unused\n", base);
	237	clk_disable_unprepare(clk);
76804d05 DL	238
76804d05 DL	239	return 0;
beb5818b LW	240	}
beb5818b LW	241
17273395	242	TIMER_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
beb5818b	243	integrator_ap_timer_init_of);