[thirdparty/kernel/stable.git] / drivers / cpufreq / s3c2410-cpufreq.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2006-2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 CPU Frequency scaling
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include <mach/regs-clock.h>

#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>

/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */

static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
{
	u32 clkdiv = 0;

	if (cfg->divs.h_divisor == 2)
		clkdiv |= S3C2410_CLKDIVN_HDIVN;

	if (cfg->divs.p_divisor != cfg->divs.h_divisor)
		clkdiv |= S3C2410_CLKDIVN_PDIVN;

	__raw_writel(clkdiv, S3C2410_CLKDIVN);
}

static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
{
	unsigned long hclk, fclk, pclk;
	unsigned int hdiv, pdiv;
	unsigned long hclk_max;

	fclk = cfg->freq.fclk;
	hclk_max = cfg->max.hclk;

	cfg->freq.armclk = fclk;

	s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
		      __func__, fclk, hclk_max);

	hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
	hclk = fclk / hdiv;

	if (hclk > cfg->max.hclk) {
		s3c_freq_dbg("%s: hclk too big\n", __func__);
		return -EINVAL;
	}

	pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
	pclk = hclk / pdiv;

	if (pclk > cfg->max.pclk) {
		s3c_freq_dbg("%s: pclk too big\n", __func__);
		return -EINVAL;
	}

	pdiv *= hdiv;

	/* record the result */
	cfg->divs.p_divisor = pdiv;
	cfg->divs.h_divisor = hdiv;

	return 0;
}

static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
	.max		= {
		.fclk	= 200000000,
		.hclk	= 100000000,
		.pclk	=  50000000,
	},

	/* transition latency is about 5ms worst-case, so
	 * set 10ms to be sure */
	.latency	= 10000000,

	.locktime_m	= 150,
	.locktime_u	= 150,
	.locktime_bits	= 12,

	.need_pll	= 1,

	.name		= "s3c2410",
	.calc_iotiming	= s3c2410_iotiming_calc,
	.set_iotiming	= s3c2410_iotiming_set,
	.get_iotiming	= s3c2410_iotiming_get,

	.set_fvco	= s3c2410_set_fvco,
	.set_refresh	= s3c2410_cpufreq_setrefresh,
	.set_divs	= s3c2410_cpufreq_setdivs,
	.calc_divs	= s3c2410_cpufreq_calcdivs,

	.debug_io_show	= s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
};

static int s3c2410_cpufreq_add(struct device *dev,
			       struct subsys_interface *sif)
{
	return s3c_cpufreq_register(&s3c2410_cpufreq_info);
}

static struct subsys_interface s3c2410_cpufreq_interface = {
	.name		= "s3c2410_cpufreq",
	.subsys		= &s3c2410_subsys,
	.add_dev	= s3c2410_cpufreq_add,
};

static int __init s3c2410_cpufreq_init(void)
{
	return subsys_interface_register(&s3c2410_cpufreq_interface);
}
arch_initcall(s3c2410_cpufreq_init);

static int s3c2410a_cpufreq_add(struct device *dev,
				struct subsys_interface *sif)
{
	/* alter the maximum freq settings for S3C2410A. If a board knows
	 * it only has a maximum of 200, then it should register its own
	 * limits. */

	s3c2410_cpufreq_info.max.fclk = 266000000;
	s3c2410_cpufreq_info.max.hclk = 133000000;
	s3c2410_cpufreq_info.max.pclk =  66500000;
	s3c2410_cpufreq_info.name = "s3c2410a";

	return s3c2410_cpufreq_add(dev, sif);
}

static struct subsys_interface s3c2410a_cpufreq_interface = {
	.name		= "s3c2410a_cpufreq",
	.subsys		= &s3c2410a_subsys,
	.add_dev	= s3c2410a_cpufreq_add,
};

static int __init s3c2410a_cpufreq_init(void)
{
	return subsys_interface_register(&s3c2410a_cpufreq_interface);
}
arch_initcall(s3c2410a_cpufreq_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
98713e40	2	/*
ccae941e	3	* Copyright (c) 2006-2008 Simtec Electronics
a24c091d BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C2410 CPU Frequency scaling
a24c091d BD	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/module.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/ioport.h>
	14	#include <linux/cpufreq.h>
4a858cfc	15	#include <linux/device.h>
a24c091d BD	16	#include <linux/clk.h>
	17	#include <linux/err.h>
	18	#include <linux/io.h>
	19
	20	#include <asm/mach/arch.h>
	21	#include <asm/mach/map.h>
	22
	23	#include <mach/regs-clock.h>
	24
	25	#include <plat/cpu.h>
a24c091d BD	26	#include <plat/cpu-freq-core.h>
	27
	28	/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
	29
	30	static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
	31	{
	32	u32 clkdiv = 0;
	33
	34	if (cfg->divs.h_divisor == 2)
	35	clkdiv \|= S3C2410_CLKDIVN_HDIVN;
	36
	37	if (cfg->divs.p_divisor != cfg->divs.h_divisor)
	38	clkdiv \|= S3C2410_CLKDIVN_PDIVN;
	39
	40	__raw_writel(clkdiv, S3C2410_CLKDIVN);
	41	}
	42
	43	static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
	44	{
	45	unsigned long hclk, fclk, pclk;
	46	unsigned int hdiv, pdiv;
	47	unsigned long hclk_max;
	48
	49	fclk = cfg->freq.fclk;
	50	hclk_max = cfg->max.hclk;
	51
	52	cfg->freq.armclk = fclk;
	53
	54	s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
	55	__func__, fclk, hclk_max);
	56
	57	hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
	58	hclk = fclk / hdiv;
	59
	60	if (hclk > cfg->max.hclk) {
	61	s3c_freq_dbg("%s: hclk too big\n", __func__);
	62	return -EINVAL;
	63	}
	64
	65	pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
	66	pclk = hclk / pdiv;
	67
	68	if (pclk > cfg->max.pclk) {
	69	s3c_freq_dbg("%s: pclk too big\n", __func__);
	70	return -EINVAL;
	71	}
	72
	73	pdiv *= hdiv;
	74
	75	/* record the result */
	76	cfg->divs.p_divisor = pdiv;
	77	cfg->divs.h_divisor = hdiv;
	78
98713e40	79	return 0;
a24c091d BD	80	}
	81
	82	static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
	83	.max = {
	84	.fclk = 200000000,
	85	.hclk = 100000000,
	86	.pclk = 50000000,
	87	},
	88
	89	/* transition latency is about 5ms worst-case, so
	90	* set 10ms to be sure */
	91	.latency = 10000000,
	92
	93	.locktime_m = 150,
	94	.locktime_u = 150,
	95	.locktime_bits = 12,
	96
	97	.need_pll = 1,
	98
	99	.name = "s3c2410",
	100	.calc_iotiming = s3c2410_iotiming_calc,
	101	.set_iotiming = s3c2410_iotiming_set,
	102	.get_iotiming = s3c2410_iotiming_get,
a24c091d BD	103
	104	.set_fvco = s3c2410_set_fvco,
	105	.set_refresh = s3c2410_cpufreq_setrefresh,
	106	.set_divs = s3c2410_cpufreq_setdivs,
	107	.calc_divs = s3c2410_cpufreq_calcdivs,
e6d197a6 BD	108
e6d197a6 BD	109	.debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
a24c091d BD	110	};
a24c091d BD	111
04511a6f HS	112	static int s3c2410_cpufreq_add(struct device *dev,
04511a6f HS	113	struct subsys_interface *sif)
a24c091d BD	114	{
	115	return s3c_cpufreq_register(&s3c2410_cpufreq_info);
	116	}
	117
4a858cfc KS	118	static struct subsys_interface s3c2410_cpufreq_interface = {
	119	.name = "s3c2410_cpufreq",
	120	.subsys = &s3c2410_subsys,
	121	.add_dev = s3c2410_cpufreq_add,
a24c091d BD	122	};
	123
	124	static int __init s3c2410_cpufreq_init(void)
	125	{
4a858cfc	126	return subsys_interface_register(&s3c2410_cpufreq_interface);
a24c091d	127	}
a24c091d BD	128	arch_initcall(s3c2410_cpufreq_init);
a24c091d BD	129
04511a6f HS	130	static int s3c2410a_cpufreq_add(struct device *dev,
04511a6f HS	131	struct subsys_interface *sif)
a24c091d BD	132	{
	133	/* alter the maximum freq settings for S3C2410A. If a board knows
	134	* it only has a maximum of 200, then it should register its own
	135	* limits. */
	136
	137	s3c2410_cpufreq_info.max.fclk = 266000000;
	138	s3c2410_cpufreq_info.max.hclk = 133000000;
	139	s3c2410_cpufreq_info.max.pclk = 66500000;
	140	s3c2410_cpufreq_info.name = "s3c2410a";
	141
04511a6f	142	return s3c2410_cpufreq_add(dev, sif);
a24c091d BD	143	}
a24c091d BD	144
4a858cfc KS	145	static struct subsys_interface s3c2410a_cpufreq_interface = {
	146	.name = "s3c2410a_cpufreq",
	147	.subsys = &s3c2410a_subsys,
	148	.add_dev = s3c2410a_cpufreq_add,
a24c091d BD	149	};
	150
	151	static int __init s3c2410a_cpufreq_init(void)
	152	{
4a858cfc	153	return subsys_interface_register(&s3c2410a_cpufreq_interface);
a24c091d	154	}
a24c091d	155	arch_initcall(s3c2410a_cpufreq_init);