[thirdparty/kernel/stable.git] / drivers / crypto / marvell / tdma.c

/*
 * Provide TDMA helper functions used by cipher and hash algorithm
 * implementations.
 *
 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
 * Author: Arnaud Ebalard <arno@natisbad.org>
 *
 * This work is based on an initial version written by
 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#include "cesa.h"

bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *iter,
					struct mv_cesa_sg_dma_iter *sgiter,
					unsigned int len)
{
	if (!sgiter->sg)
		return false;

	sgiter->op_offset += len;
	sgiter->offset += len;
	if (sgiter->offset == sg_dma_len(sgiter->sg)) {
		if (sg_is_last(sgiter->sg))
			return false;
		sgiter->offset = 0;
		sgiter->sg = sg_next(sgiter->sg);
	}

	if (sgiter->op_offset == iter->op_len)
		return false;

	return true;
}

void mv_cesa_dma_step(struct mv_cesa_tdma_req *dreq)
{
	struct mv_cesa_engine *engine = dreq->base.engine;

	writel_relaxed(0, engine->regs + CESA_SA_CFG);

	mv_cesa_set_int_mask(engine, CESA_SA_INT_ACC0_IDMA_DONE);
	writel_relaxed(CESA_TDMA_DST_BURST_128B | CESA_TDMA_SRC_BURST_128B |
		       CESA_TDMA_NO_BYTE_SWAP | CESA_TDMA_EN,
		       engine->regs + CESA_TDMA_CONTROL);

	writel_relaxed(CESA_SA_CFG_ACT_CH0_IDMA | CESA_SA_CFG_MULTI_PKT |
		       CESA_SA_CFG_CH0_W_IDMA | CESA_SA_CFG_PARA_DIS,
		       engine->regs + CESA_SA_CFG);
	writel_relaxed(dreq->chain.first->cur_dma,
		       engine->regs + CESA_TDMA_NEXT_ADDR);
	writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
}

void mv_cesa_dma_cleanup(struct mv_cesa_tdma_req *dreq)
{
	struct mv_cesa_tdma_desc *tdma;

	for (tdma = dreq->chain.first; tdma;) {
		struct mv_cesa_tdma_desc *old_tdma = tdma;

		if (tdma->flags & CESA_TDMA_OP)
			dma_pool_free(cesa_dev->dma->op_pool, tdma->op,
				      le32_to_cpu(tdma->src));

		tdma = tdma->next;
		dma_pool_free(cesa_dev->dma->tdma_desc_pool, old_tdma,
			      le32_to_cpu(old_tdma->cur_dma));
	}

	dreq->chain.first = NULL;
	dreq->chain.last = NULL;
}

void mv_cesa_dma_prepare(struct mv_cesa_tdma_req *dreq,
			 struct mv_cesa_engine *engine)
{
	struct mv_cesa_tdma_desc *tdma;

	for (tdma = dreq->chain.first; tdma; tdma = tdma->next) {
		if (tdma->flags & CESA_TDMA_DST_IN_SRAM)
			tdma->dst = cpu_to_le32(tdma->dst + engine->sram_dma);

		if (tdma->flags & CESA_TDMA_SRC_IN_SRAM)
			tdma->src = cpu_to_le32(tdma->src + engine->sram_dma);

		if (tdma->flags & CESA_TDMA_OP)
			mv_cesa_adjust_op(engine, tdma->op);
	}
}

static struct mv_cesa_tdma_desc *
mv_cesa_dma_add_desc(struct mv_cesa_tdma_chain *chain, gfp_t flags)
{
	struct mv_cesa_tdma_desc *new_tdma = NULL;
	dma_addr_t dma_handle;

	new_tdma = dma_pool_alloc(cesa_dev->dma->tdma_desc_pool, flags,
				  &dma_handle);
	if (!new_tdma)
		return ERR_PTR(-ENOMEM);

	memset(new_tdma, 0, sizeof(*new_tdma));
	new_tdma->cur_dma = cpu_to_le32(dma_handle);
	if (chain->last) {
		chain->last->next_dma = new_tdma->cur_dma;
		chain->last->next = new_tdma;
	} else {
		chain->first = new_tdma;
	}

	chain->last = new_tdma;

	return new_tdma;
}

struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
					const struct mv_cesa_op_ctx *op_templ,
					bool skip_ctx,
					gfp_t flags)
{
	struct mv_cesa_tdma_desc *tdma;
	struct mv_cesa_op_ctx *op;
	dma_addr_t dma_handle;

	tdma = mv_cesa_dma_add_desc(chain, flags);
	if (IS_ERR(tdma))
		return ERR_CAST(tdma);

	op = dma_pool_alloc(cesa_dev->dma->op_pool, flags, &dma_handle);
	if (!op)
		return ERR_PTR(-ENOMEM);

	*op = *op_templ;

	tdma = chain->last;
	tdma->op = op;
	tdma->byte_cnt = (skip_ctx ? sizeof(op->desc) : sizeof(*op)) | BIT(31);
	tdma->src = dma_handle;
	tdma->flags = CESA_TDMA_DST_IN_SRAM | CESA_TDMA_OP;

	return op;
}

int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
				  dma_addr_t dst, dma_addr_t src, u32 size,
				  u32 flags, gfp_t gfp_flags)
{
	struct mv_cesa_tdma_desc *tdma;

	tdma = mv_cesa_dma_add_desc(chain, gfp_flags);
	if (IS_ERR(tdma))
		return PTR_ERR(tdma);

	tdma->byte_cnt = size | BIT(31);
	tdma->src = src;
	tdma->dst = dst;

	flags &= (CESA_TDMA_DST_IN_SRAM | CESA_TDMA_SRC_IN_SRAM);
	tdma->flags = flags | CESA_TDMA_DATA;

	return 0;
}

int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain,
				 u32 flags)
{
	struct mv_cesa_tdma_desc *tdma;

	tdma = mv_cesa_dma_add_desc(chain, flags);
	if (IS_ERR(tdma))
		return PTR_ERR(tdma);

	return 0;
}

int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, u32 flags)
{
	struct mv_cesa_tdma_desc *tdma;

	tdma = mv_cesa_dma_add_desc(chain, flags);
	if (IS_ERR(tdma))
		return PTR_ERR(tdma);

	tdma->byte_cnt = BIT(31);

	return 0;
}

int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
				 struct mv_cesa_dma_iter *dma_iter,
				 struct mv_cesa_sg_dma_iter *sgiter,
				 gfp_t gfp_flags)
{
	u32 flags = sgiter->dir == DMA_TO_DEVICE ?
		    CESA_TDMA_DST_IN_SRAM : CESA_TDMA_SRC_IN_SRAM;
	unsigned int len;

	do {
		dma_addr_t dst, src;
		int ret;

		len = mv_cesa_req_dma_iter_transfer_len(dma_iter, sgiter);
		if (sgiter->dir == DMA_TO_DEVICE) {
			dst = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
			src = sg_dma_address(sgiter->sg) + sgiter->offset;
		} else {
			dst = sg_dma_address(sgiter->sg) + sgiter->offset;
			src = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
		}

		ret = mv_cesa_dma_add_data_transfer(chain, dst, src, len,
						    flags, gfp_flags);
		if (ret)
			return ret;

	} while (mv_cesa_req_dma_iter_next_transfer(dma_iter, sgiter, len));

	return 0;
}
Commit	Line	Data
db509a45 BB	1	/*
	2	* Provide TDMA helper functions used by cipher and hash algorithm
	3	* implementations.
	4	*
	5	* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
	6	* Author: Arnaud Ebalard <arno@natisbad.org>
	7	*
	8	* This work is based on an initial version written by
	9	* Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License version 2 as published
	13	* by the Free Software Foundation.
	14	*/
	15
	16	#include "cesa.h"
	17
	18	bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *iter,
	19	struct mv_cesa_sg_dma_iter *sgiter,
	20	unsigned int len)
	21	{
	22	if (!sgiter->sg)
	23	return false;
	24
	25	sgiter->op_offset += len;
	26	sgiter->offset += len;
	27	if (sgiter->offset == sg_dma_len(sgiter->sg)) {
	28	if (sg_is_last(sgiter->sg))
	29	return false;
	30	sgiter->offset = 0;
	31	sgiter->sg = sg_next(sgiter->sg);
	32	}
	33
	34	if (sgiter->op_offset == iter->op_len)
	35	return false;
	36
	37	return true;
	38	}
	39
	40	void mv_cesa_dma_step(struct mv_cesa_tdma_req *dreq)
	41	{
	42	struct mv_cesa_engine *engine = dreq->base.engine;
	43
b1508561	44	writel_relaxed(0, engine->regs + CESA_SA_CFG);
db509a45 BB	45
db509a45 BB	46	mv_cesa_set_int_mask(engine, CESA_SA_INT_ACC0_IDMA_DONE);
b1508561 RK	47	writel_relaxed(CESA_TDMA_DST_BURST_128B \| CESA_TDMA_SRC_BURST_128B \|
	48	CESA_TDMA_NO_BYTE_SWAP \| CESA_TDMA_EN,
	49	engine->regs + CESA_TDMA_CONTROL);
	50
	51	writel_relaxed(CESA_SA_CFG_ACT_CH0_IDMA \| CESA_SA_CFG_MULTI_PKT \|
	52	CESA_SA_CFG_CH0_W_IDMA \| CESA_SA_CFG_PARA_DIS,
	53	engine->regs + CESA_SA_CFG);
	54	writel_relaxed(dreq->chain.first->cur_dma,
	55	engine->regs + CESA_TDMA_NEXT_ADDR);
db509a45 BB	56	writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
	57	}
	58
	59	void mv_cesa_dma_cleanup(struct mv_cesa_tdma_req *dreq)
	60	{
	61	struct mv_cesa_tdma_desc *tdma;
	62
	63	for (tdma = dreq->chain.first; tdma;) {
	64	struct mv_cesa_tdma_desc *old_tdma = tdma;
	65
	66	if (tdma->flags & CESA_TDMA_OP)
	67	dma_pool_free(cesa_dev->dma->op_pool, tdma->op,
	68	le32_to_cpu(tdma->src));
	69
	70	tdma = tdma->next;
	71	dma_pool_free(cesa_dev->dma->tdma_desc_pool, old_tdma,
	72	le32_to_cpu(old_tdma->cur_dma));
	73	}
	74
	75	dreq->chain.first = NULL;
	76	dreq->chain.last = NULL;
	77	}
	78
	79	void mv_cesa_dma_prepare(struct mv_cesa_tdma_req *dreq,
	80	struct mv_cesa_engine *engine)
	81	{
	82	struct mv_cesa_tdma_desc *tdma;
	83
	84	for (tdma = dreq->chain.first; tdma; tdma = tdma->next) {
	85	if (tdma->flags & CESA_TDMA_DST_IN_SRAM)
	86	tdma->dst = cpu_to_le32(tdma->dst + engine->sram_dma);
	87
	88	if (tdma->flags & CESA_TDMA_SRC_IN_SRAM)
	89	tdma->src = cpu_to_le32(tdma->src + engine->sram_dma);
	90
	91	if (tdma->flags & CESA_TDMA_OP)
	92	mv_cesa_adjust_op(engine, tdma->op);
	93	}
	94	}
	95
	96	static struct mv_cesa_tdma_desc *
	97	mv_cesa_dma_add_desc(struct mv_cesa_tdma_chain *chain, gfp_t flags)
	98	{
	99	struct mv_cesa_tdma_desc *new_tdma = NULL;
	100	dma_addr_t dma_handle;
	101
	102	new_tdma = dma_pool_alloc(cesa_dev->dma->tdma_desc_pool, flags,
	103	&dma_handle);
	104	if (!new_tdma)
	105	return ERR_PTR(-ENOMEM);
	106
	107	memset(new_tdma, 0, sizeof(*new_tdma));
	108	new_tdma->cur_dma = cpu_to_le32(dma_handle);
	109	if (chain->last) {
	110	chain->last->next_dma = new_tdma->cur_dma;
	111	chain->last->next = new_tdma;
	112	} else {
	113	chain->first = new_tdma;
	114	}
	115
	116	chain->last = new_tdma;
	117
	118	return new_tdma;
	119	}
120
121	struct mv_cesa_op_ctx mv_cesa_dma_add_op(struct mv_cesa_tdma_chain chain,
122	const struct mv_cesa_op_ctx *op_templ,
123	bool skip_ctx,
124	gfp_t flags)
125	{
126	struct mv_cesa_tdma_desc *tdma;
127	struct mv_cesa_op_ctx *op;
128	dma_addr_t dma_handle;
129
130	tdma = mv_cesa_dma_add_desc(chain, flags);
131	if (IS_ERR(tdma))
132	return ERR_CAST(tdma);
133
134	op = dma_pool_alloc(cesa_dev->dma->op_pool, flags, &dma_handle);
135	if (!op)
136	return ERR_PTR(-ENOMEM);
137
138	op = op_templ;
139
140	tdma = chain->last;
141	tdma->op = op;
142	tdma->byte_cnt = (skip_ctx ? sizeof(op->desc) : sizeof(*op)) \| BIT(31);
143	tdma->src = dma_handle;
144	tdma->flags = CESA_TDMA_DST_IN_SRAM \| CESA_TDMA_OP;
145
146	return op;
147	}
148
149	int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
150	dma_addr_t dst, dma_addr_t src, u32 size,
151	u32 flags, gfp_t gfp_flags)
152	{
153	struct mv_cesa_tdma_desc *tdma;
154
155	tdma = mv_cesa_dma_add_desc(chain, gfp_flags);
156	if (IS_ERR(tdma))
157	return PTR_ERR(tdma);
158
159	tdma->byte_cnt = size \| BIT(31);
160	tdma->src = src;
161	tdma->dst = dst;
162
163	flags &= (CESA_TDMA_DST_IN_SRAM \| CESA_TDMA_SRC_IN_SRAM);
164	tdma->flags = flags \| CESA_TDMA_DATA;
165
166	return 0;
167	}
168
169	int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain,
170	u32 flags)
171	{
172	struct mv_cesa_tdma_desc *tdma;
173
174	tdma = mv_cesa_dma_add_desc(chain, flags);
175	if (IS_ERR(tdma))
176	return PTR_ERR(tdma);
177
178	return 0;
179	}
180
181	int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, u32 flags)
182	{
183	struct mv_cesa_tdma_desc *tdma;
184
185	tdma = mv_cesa_dma_add_desc(chain, flags);
186	if (IS_ERR(tdma))
187	return PTR_ERR(tdma);
188
189	tdma->byte_cnt = BIT(31);
190
191	return 0;
192	}
193
194	int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
195	struct mv_cesa_dma_iter *dma_iter,
196	struct mv_cesa_sg_dma_iter *sgiter,
197	gfp_t gfp_flags)
198	{
199	u32 flags = sgiter->dir == DMA_TO_DEVICE ?
200	CESA_TDMA_DST_IN_SRAM : CESA_TDMA_SRC_IN_SRAM;
201	unsigned int len;
202
203	do {
204	dma_addr_t dst, src;
205	int ret;
206
207	len = mv_cesa_req_dma_iter_transfer_len(dma_iter, sgiter);
208	if (sgiter->dir == DMA_TO_DEVICE) {
209	dst = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
210	src = sg_dma_address(sgiter->sg) + sgiter->offset;
211	} else {
212	dst = sg_dma_address(sgiter->sg) + sgiter->offset;
213	src = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
214	}
215
216	ret = mv_cesa_dma_add_data_transfer(chain, dst, src, len,
217	flags, gfp_flags);
218	if (ret)
219	return ret;
220
221	} while (mv_cesa_req_dma_iter_next_transfer(dma_iter, sgiter, len));
222
223	return 0;
224	}