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fe8c2806 WD |
1 | /* |
2 | * Cirrus Logic CS8900A Ethernet | |
3 | * | |
4 | * (C) Copyright 2002 | |
5 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
6 | * Marius Groeger <mgroeger@sysgo.de> | |
7 | * | |
8 | * Copyright (C) 1999 Ben Williamson <benw@pobox.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is loaded into SRAM in bootstrap mode, where it waits | |
14 | * for commands on UART1 to read and write memory, jump to code etc. | |
15 | * A design goal for this program is to be entirely independent of the | |
16 | * target board. Anything with a CL-PS7111 or EP7211 should be able to run | |
17 | * this code in bootstrap mode. All the board specifics can be handled on | |
18 | * the host. | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, write to the Free Software | |
32 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | */ | |
34 | ||
35 | #include <asm/types.h> | |
36 | #include <config.h> | |
37 | ||
38 | #ifdef CONFIG_DRIVER_CS8900 | |
39 | ||
40 | /* although the registers are 16 bit, they are 32-bit aligned on the | |
41 | EDB7111. so we have to read them as 32-bit registers and ignore the | |
42 | upper 16-bits. i'm not sure if this holds for the EDB7211. */ | |
43 | ||
44 | #ifdef CS8900_BUS16 | |
45 | /* 16 bit aligned registers, 16 bit wide */ | |
46 | #define CS8900_REG u16 | |
47 | #define CS8900_OFF 0x02 | |
48 | #define CS8900_BUS16_0 *(volatile u8 *)(CS8900_BASE+0x00) | |
49 | #define CS8900_BUS16_1 *(volatile u8 *)(CS8900_BASE+0x01) | |
42dfe7a1 | 50 | #elif defined(CS8900_BUS32) |
fe8c2806 WD |
51 | /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */ |
52 | #define CS8900_REG u32 | |
53 | #define CS8900_OFF 0x04 | |
54 | #else | |
55 | #error unknown bussize ... | |
56 | #endif | |
57 | ||
58 | #define CS8900_RTDATA *(volatile CS8900_REG *)(CS8900_BASE+0x00*CS8900_OFF) | |
59 | #define CS8900_TxCMD *(volatile CS8900_REG *)(CS8900_BASE+0x02*CS8900_OFF) | |
60 | #define CS8900_TxLEN *(volatile CS8900_REG *)(CS8900_BASE+0x03*CS8900_OFF) | |
61 | #define CS8900_ISQ *(volatile CS8900_REG *)(CS8900_BASE+0x04*CS8900_OFF) | |
62 | #define CS8900_PPTR *(volatile CS8900_REG *)(CS8900_BASE+0x05*CS8900_OFF) | |
63 | #define CS8900_PDATA *(volatile CS8900_REG *)(CS8900_BASE+0x06*CS8900_OFF) | |
64 | ||
65 | ||
66 | #define ISQ_RxEvent 0x04 | |
67 | #define ISQ_TxEvent 0x08 | |
68 | #define ISQ_BufEvent 0x0C | |
69 | #define ISQ_RxMissEvent 0x10 | |
70 | #define ISQ_TxColEvent 0x12 | |
71 | #define ISQ_EventMask 0x3F | |
72 | ||
73 | /* packet page register offsets */ | |
74 | ||
75 | /* bus interface registers */ | |
76 | #define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */ | |
77 | #define PP_ChipRev 0x0002 /* Chip revision, model codes */ | |
78 | ||
79 | #define PP_IntReg 0x0022 /* Interrupt configuration */ | |
80 | #define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */ | |
81 | #define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */ | |
82 | #define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */ | |
83 | #define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */ | |
84 | ||
85 | /* status and control registers */ | |
86 | ||
87 | #define PP_RxCFG 0x0102 /* Receiver configuration */ | |
88 | #define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */ | |
89 | #define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */ | |
90 | #define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */ | |
91 | #define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */ | |
92 | #define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */ | |
93 | #define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */ | |
94 | #define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */ | |
95 | #define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */ | |
96 | #define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */ | |
97 | ||
98 | #define PP_RxCTL 0x0104 /* Receiver control */ | |
99 | #define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */ | |
100 | #define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */ | |
101 | #define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */ | |
102 | #define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */ | |
103 | #define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */ | |
104 | #define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */ | |
105 | #define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */ | |
106 | #define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */ | |
107 | #define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */ | |
108 | ||
109 | #define PP_TxCFG 0x0106 /* Transmit configuration */ | |
110 | #define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */ | |
111 | #define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */ | |
112 | #define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */ | |
113 | #define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */ | |
114 | #define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */ | |
115 | #define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */ | |
116 | #define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */ | |
117 | ||
118 | #define PP_TxCmd 0x0108 /* Transmit command status */ | |
119 | #define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */ | |
120 | #define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */ | |
121 | #define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */ | |
122 | #define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */ | |
123 | #define PP_TxCmd_Force 0x0100 /* Discard any pending packets */ | |
124 | #define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */ | |
125 | #define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */ | |
126 | #define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */ | |
127 | ||
128 | #define PP_BufCFG 0x010A /* Buffer configuration */ | |
129 | #define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */ | |
130 | #define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */ | |
131 | #define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */ | |
132 | #define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */ | |
133 | #define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */ | |
134 | #define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */ | |
135 | #define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */ | |
136 | #define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */ | |
137 | #define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */ | |
138 | ||
139 | #define PP_LineCTL 0x0112 /* Line control */ | |
140 | #define PP_LineCTL_Rx 0x0040 /* Enable receiver */ | |
141 | #define PP_LineCTL_Tx 0x0080 /* Enable transmitter */ | |
142 | #define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */ | |
143 | #define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */ | |
144 | #define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */ | |
145 | #define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */ | |
146 | #define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */ | |
147 | #define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */ | |
148 | ||
149 | #define PP_SelfCTL 0x0114 /* Chip self control */ | |
150 | #define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */ | |
151 | #define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */ | |
152 | #define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */ | |
153 | #define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */ | |
154 | #define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */ | |
155 | #define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */ | |
156 | #define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */ | |
157 | #define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */ | |
158 | ||
159 | #define PP_BusCTL 0x0116 /* Bus control */ | |
160 | #define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */ | |
161 | #define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */ | |
162 | #define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */ | |
163 | #define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */ | |
164 | #define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */ | |
165 | #define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */ | |
166 | #define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */ | |
167 | #define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */ | |
168 | ||
169 | #define PP_TestCTL 0x0118 /* Test control */ | |
170 | #define PP_TestCTL_DisableLT 0x0080 /* Disable link status */ | |
171 | #define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */ | |
172 | #define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */ | |
173 | #define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */ | |
174 | #define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */ | |
175 | ||
176 | #define PP_ISQ 0x0120 /* Interrupt Status Queue */ | |
177 | ||
178 | #define PP_RER 0x0124 /* Receive event */ | |
179 | #define PP_RER_IAHash 0x0040 /* Frame hash match */ | |
180 | #define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */ | |
181 | #define PP_RER_RxOK 0x0100 /* Frame received with no errors */ | |
182 | #define PP_RER_Hashed 0x0200 /* Frame address hashed OK */ | |
183 | #define PP_RER_IA 0x0400 /* Frame address matched IA */ | |
184 | #define PP_RER_Broadcast 0x0800 /* Broadcast frame */ | |
185 | #define PP_RER_CRC 0x1000 /* Frame had CRC error */ | |
186 | #define PP_RER_RUNT 0x2000 /* Runt frame */ | |
187 | #define PP_RER_EXTRA 0x4000 /* Frame was too long */ | |
188 | ||
189 | #define PP_TER 0x0128 /* Transmit event */ | |
190 | #define PP_TER_CRS 0x0040 /* Carrier lost */ | |
191 | #define PP_TER_SQE 0x0080 /* Signal Quality Error */ | |
192 | #define PP_TER_TxOK 0x0100 /* Packet sent without error */ | |
193 | #define PP_TER_Late 0x0200 /* Out of window */ | |
194 | #define PP_TER_Jabber 0x0400 /* Stuck transmit? */ | |
195 | #define PP_TER_NumCollisions 0x7800 /* Number of collisions */ | |
196 | #define PP_TER_16Collisions 0x8000 /* > 16 collisions */ | |
197 | ||
198 | #define PP_BER 0x012C /* Buffer event */ | |
199 | #define PP_BER_SWint 0x0040 /* Software interrupt */ | |
200 | #define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */ | |
201 | #define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */ | |
202 | #define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */ | |
203 | #define PP_BER_RxMiss 0x0400 /* Received frame missed */ | |
204 | #define PP_BER_Rx128 0x0800 /* 128 bytes received */ | |
205 | #define PP_BER_RxDest 0x8000 /* Received framed passed address filter */ | |
206 | ||
207 | #define PP_RxMiss 0x0130 /* Receiver miss counter */ | |
208 | ||
209 | #define PP_TxCol 0x0132 /* Transmit collision counter */ | |
210 | ||
211 | #define PP_LineSTAT 0x0134 /* Line status */ | |
212 | #define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */ | |
213 | #define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */ | |
214 | #define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */ | |
215 | #define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */ | |
216 | #define PP_LineSTAT_CRS 0x4000 /* Frame being received */ | |
217 | ||
218 | #define PP_SelfSTAT 0x0136 /* Chip self status */ | |
219 | #define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */ | |
220 | #define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */ | |
221 | #define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */ | |
222 | #define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */ | |
223 | #define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */ | |
224 | #define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */ | |
225 | #define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */ | |
226 | ||
227 | #define PP_BusSTAT 0x0138 /* Bus status */ | |
228 | #define PP_BusSTAT_TxBid 0x0080 /* Tx error */ | |
229 | #define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */ | |
230 | ||
231 | #define PP_TDR 0x013C /* AUI Time Domain Reflectometer */ | |
232 | ||
233 | /* initiate transmit registers */ | |
234 | ||
235 | #define PP_TxCommand 0x0144 /* Tx Command */ | |
236 | #define PP_TxLength 0x0146 /* Tx Length */ | |
237 | ||
238 | ||
239 | /* address filter registers */ | |
240 | ||
241 | #define PP_LAF 0x0150 /* Logical address filter (6 bytes) */ | |
242 | #define PP_IA 0x0158 /* Individual address (MAC) */ | |
243 | ||
244 | /* EEPROM Kram */ | |
245 | #define SI_BUSY 0x0100 | |
246 | #define PP_SelfST 0x0136 /* Self State register */ | |
247 | #define PP_EECMD 0x0040 /* NVR Interface Command register */ | |
248 | #define PP_EEData 0x0042 /* NVR Interface Data Register */ | |
249 | #define EEPROM_WRITE_EN 0x00F0 | |
250 | #define EEPROM_WRITE_DIS 0x0000 | |
251 | #define EEPROM_WRITE_CMD 0x0100 | |
252 | #define EEPROM_READ_CMD 0x0200 | |
1cb8e980 | 253 | #define EEPROM_ERASE_CMD 0x0300 |
fe8c2806 | 254 | |
1cb8e980 | 255 | extern int cs8900_e2prom_read(uchar, ushort *); |
06d01dbe | 256 | extern int cs8900_e2prom_write(uchar, ushort); |
fe8c2806 WD |
257 | |
258 | #endif /* CONFIG_DRIVER_CS8900 */ |