[people/ms/u-boot.git] / drivers / dc2114x.c

/*
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
	&& defined(CONFIG_TULIP)

#include <malloc.h>
#include <net.h>
#include <pci.h>

#undef DEBUG
#undef DEBUG_SROM
#undef DEBUG_SROM2

#undef UPDATE_SROM

/* PCI Registers.
 */
#define PCI_CFDA_PSM		0x43

#define CFRV_RN		0x000000f0	/* Revision Number */

#define WAKEUP		0x00		/* Power Saving Wakeup */
#define SLEEP		0x80		/* Power Saving Sleep Mode */

#define DC2114x_BRK	0x0020		/* CFRV break between DC21142 & DC21143 */

/* Ethernet chip registers.
 */
#define DE4X5_BMR	0x000		/* Bus Mode Register */
#define DE4X5_TPD	0x008		/* Transmit Poll Demand Reg */
#define DE4X5_RRBA	0x018		/* RX Ring Base Address Reg */
#define DE4X5_TRBA	0x020		/* TX Ring Base Address Reg */
#define DE4X5_STS	0x028		/* Status Register */
#define DE4X5_OMR	0x030		/* Operation Mode Register */
#define DE4X5_SICR	0x068		/* SIA Connectivity Register */
#define DE4X5_APROM	0x048		/* Ethernet Address PROM */

/* Register bits.
 */
#define BMR_SWR		0x00000001	/* Software Reset */
#define STS_TS		0x00700000	/* Transmit Process State */
#define STS_RS		0x000e0000	/* Receive Process State */
#define OMR_ST		0x00002000	/* Start/Stop Transmission Command */
#define OMR_SR		0x00000002	/* Start/Stop Receive */
#define OMR_PS		0x00040000	/* Port Select */
#define OMR_SDP		0x02000000	/* SD Polarity - MUST BE ASSERTED */
#define OMR_PM		0x00000080	/* Pass All Multicast */

/* Descriptor bits.
 */
#define R_OWN		0x80000000	/* Own Bit */
#define RD_RER		0x02000000	/* Receive End Of Ring */
#define RD_LS		0x00000100	/* Last Descriptor */
#define RD_ES		0x00008000	/* Error Summary */
#define TD_TER		0x02000000	/* Transmit End Of Ring */
#define T_OWN		0x80000000	/* Own Bit */
#define TD_LS		0x40000000	/* Last Segment */
#define TD_FS		0x20000000	/* First Segment */
#define TD_ES		0x00008000	/* Error Summary */
#define TD_SET		0x08000000	/* Setup Packet */

/* The EEPROM commands include the alway-set leading bit. */
#define SROM_WRITE_CMD	5
#define SROM_READ_CMD	6
#define SROM_ERASE_CMD	7

#define SROM_HWADD	    0x0014	/* Hardware Address offset in SROM */
#define SROM_RD		0x00004000	/* Read from Boot ROM */
#define EE_DATA_WRITE	0x04	/* EEPROM chip data in. */
#define EE_WRITE_0		0x4801
#define EE_WRITE_1		0x4805
#define EE_DATA_READ	0x08	/* EEPROM chip data out. */
#define SROM_SR		0x00000800	/* Select Serial ROM when set */

#define DT_IN		0x00000004	/* Serial Data In */
#define DT_CLK		0x00000002	/* Serial ROM Clock */
#define DT_CS		0x00000001	/* Serial ROM Chip Select */

#define POLL_DEMAND	1

#define RESET_DE4X5(dev) {\
    int i;\
    i=INL(dev, DE4X5_BMR);\
    udelay(1000);\
    OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
    udelay(1000);\
    OUTL(dev, i, DE4X5_BMR);\
    udelay(1000);\
    for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
    udelay(1000);\
}

#define START_DE4X5(dev) {\
    s32 omr; \
    omr = INL(dev, DE4X5_OMR);\
    omr |= OMR_ST | OMR_SR;\
    OUTL(dev, omr, DE4X5_OMR);		/* Enable the TX and/or RX */\
}

#define STOP_DE4X5(dev) {\
    s32 omr; \
    omr = INL(dev, DE4X5_OMR);\
    omr &= ~(OMR_ST|OMR_SR);\
    OUTL(dev, omr, DE4X5_OMR);		/* Disable the TX and/or RX */ \
}

#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 1			/* Number of TX descriptors   */
#define RX_BUFF_SZ  PKTSIZE_ALIGN

#define TOUT_LOOP   1000000

#define SETUP_FRAME_LEN 192
#define ETH_ALEN	6


struct de4x5_desc {
	volatile s32 status;
	u32 des1;
	u32 buf;
	u32 next;
};

static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring         */
static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring         */
static int rx_new;                             /* RX descriptor ring pointer */
static int tx_new;                             /* TX descriptor ring pointer */

static char rxRingSize;
static char txRingSize;

static void  sendto_srom(struct eth_device* dev, u_int command, u_long addr);
static int   getfrom_srom(struct eth_device* dev, u_long addr);
static int   do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len);
static int   do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len);
static int   read_srom(struct eth_device *dev, u_long ioaddr, int index);
#ifdef UPDATE_SROM
static int   write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
static void  update_srom(struct eth_device *dev, bd_t *bis);
#endif
static void  read_hw_addr(struct eth_device* dev, bd_t * bis);
static void  send_setup_frame(struct eth_device* dev, bd_t * bis);

static int   dc21x4x_init(struct eth_device* dev, bd_t* bis);
static int   dc21x4x_send(struct eth_device* dev, volatile void *packet, int length);
static int   dc21x4x_recv(struct eth_device* dev);
static void  dc21x4x_halt(struct eth_device* dev);
#ifdef CONFIG_TULIP_SELECT_MEDIA
extern void  dc21x4x_select_media(struct eth_device* dev);
#endif

#if defined(CONFIG_E500)
#define phys_to_bus(a) (a)
#else
#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
#endif

static int INL(struct eth_device* dev, u_long addr)
{
	return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
}

static void OUTL(struct eth_device* dev, int command, u_long addr)
{
	*(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
}

static struct pci_device_id supported[] = {
	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
	{ }
};

int dc21x4x_initialize(bd_t *bis)
{
	int             	idx=0;
	int             	card_number = 0;
	int             	cfrv;
	unsigned char   	timer;
	pci_dev_t		devbusfn;
	unsigned int		iobase;
	unsigned short		status;
	struct eth_device* 	dev;

	while(1) {
		devbusfn =  pci_find_devices(supported, idx++);
		if (devbusfn == -1) {
			break;
		}

		/* Get the chip configuration revision register. */
		pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);

		if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
			printf("Error: The chip is not DC21143.\n");
			continue;
		}

		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
		status |=
#ifdef CONFIG_TULIP_USE_IO
		  PCI_COMMAND_IO |
#else
		  PCI_COMMAND_MEMORY |
#endif
		  PCI_COMMAND_MASTER;
		pci_write_config_word(devbusfn, PCI_COMMAND, status);

		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
		if (!(status & PCI_COMMAND_IO)) {
			printf("Error: Can not enable I/O access.\n");
			continue;
		}

		if (!(status & PCI_COMMAND_IO)) {
			printf("Error: Can not enable I/O access.\n");
			continue;
		}

		if (!(status & PCI_COMMAND_MASTER)) {
			printf("Error: Can not enable Bus Mastering.\n");
			continue;
		}

		/* Check the latency timer for values >= 0x60. */
		pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);

		if (timer < 0x60) {
			pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
		}

#ifdef CONFIG_TULIP_USE_IO
		/* read BAR for memory space access */
		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
		iobase &= PCI_BASE_ADDRESS_IO_MASK;
#else
		/* read BAR for memory space access */
		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
		iobase &= PCI_BASE_ADDRESS_MEM_MASK;
#endif

#ifdef DEBUG
		printf("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
#endif

		dev = (struct eth_device*) malloc(sizeof *dev);

		sprintf(dev->name, "dc21x4x#%d", card_number);
#ifdef CONFIG_TULIP_USE_IO
		dev->iobase = pci_io_to_phys(devbusfn, iobase);
#else
		dev->iobase = pci_mem_to_phys(devbusfn, iobase);
#endif
		dev->priv   = (void*) devbusfn;
		dev->init   = dc21x4x_init;
		dev->halt   = dc21x4x_halt;
		dev->send   = dc21x4x_send;
		dev->recv   = dc21x4x_recv;

		/* Ensure we're not sleeping. */
		pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);

		udelay(10 * 1000);

		read_hw_addr(dev, bis);

		eth_register(dev);

		card_number++;
	}

	return card_number;
}

static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
{
	int		i;
	int		devbusfn = (int) dev->priv;

	/* Ensure we're not sleeping. */
	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);

	RESET_DE4X5(dev);

	if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
		printf("Error: Cannot reset ethernet controller.\n");
		return 0;
	}

#ifdef CONFIG_TULIP_SELECT_MEDIA
	dc21x4x_select_media(dev);
#else
	OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
#endif

	for (i = 0; i < NUM_RX_DESC; i++) {
		rx_ring[i].status = cpu_to_le32(R_OWN);
		rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
		rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i]));
		rx_ring[i].next = 0;
	}

	for (i=0; i < NUM_TX_DESC; i++) {
		tx_ring[i].status = 0;
		tx_ring[i].des1 = 0;
		tx_ring[i].buf = 0;
		tx_ring[i].next = 0;
	}

	rxRingSize = NUM_RX_DESC;
	txRingSize = NUM_TX_DESC;

	/* Write the end of list marker to the descriptor lists. */
	rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
	tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);

	/* Tell the adapter where the TX/RX rings are located. */
	OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
	OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);

	START_DE4X5(dev);

	tx_new = 0;
	rx_new = 0;

	send_setup_frame(dev, bis);

	return 1;
}

static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length)
{
	int		status = -1;
	int		i;

	if (length <= 0) {
		printf("%s: bad packet size: %d\n", dev->name, length);
		goto Done;
	}

	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
		if (i >= TOUT_LOOP) {
			printf("%s: tx error buffer not ready\n", dev->name);
			goto Done;
		}
	}

	tx_ring[tx_new].buf    = cpu_to_le32(phys_to_bus((u32) packet));
	tx_ring[tx_new].des1   = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
	tx_ring[tx_new].status = cpu_to_le32(T_OWN);

	OUTL(dev, POLL_DEMAND, DE4X5_TPD);

	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
		if (i >= TOUT_LOOP) {
			printf(".%s: tx buffer not ready\n", dev->name);
			goto Done;
		}
	}

	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
#if 0 /* test-only */
		printf("TX error status = 0x%08X\n",
		       le32_to_cpu(tx_ring[tx_new].status));
#endif
		goto Done;
	}

	status = length;

 Done:
	return status;
}

static int dc21x4x_recv(struct eth_device* dev)
{
	s32		status;
	int		length    = 0;

	for ( ; ; ) {
		status = (s32)le32_to_cpu(rx_ring[rx_new].status);

		if (status & R_OWN) {
			break;
		}

		if (status & RD_LS) {
			/* Valid frame status.
			 */
			if (status & RD_ES) {

				/* There was an error.
				 */
				printf("RX error status = 0x%08X\n", status);
			} else {
				/* A valid frame received.
				 */
				length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);

				/* Pass the packet up to the protocol
				 * layers.
				 */
				NetReceive(NetRxPackets[rx_new], length - 4);
			}

			/* Change buffer ownership for this frame, back
			 * to the adapter.
			 */
			rx_ring[rx_new].status = cpu_to_le32(R_OWN);
		}

		/* Update entry information.
		 */
		rx_new = (rx_new + 1) % rxRingSize;
	}

	return length;
}

static void dc21x4x_halt(struct eth_device* dev)
{
	int		devbusfn = (int) dev->priv;

	STOP_DE4X5(dev);
	OUTL(dev, 0, DE4X5_SICR);

	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
}

static void send_setup_frame(struct eth_device* dev, bd_t *bis)
{
	int		i;
	char	setup_frame[SETUP_FRAME_LEN];
	char 	*pa = &setup_frame[0];

	memset(pa, 0xff, SETUP_FRAME_LEN);

	for (i = 0; i < ETH_ALEN; i++) {
		*(pa + (i & 1)) = dev->enetaddr[i];
		if (i & 0x01) {
			pa += 4;
		}
	}

	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
		if (i >= TOUT_LOOP) {
			printf("%s: tx error buffer not ready\n", dev->name);
			goto Done;
		}
	}

	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
	tx_ring[tx_new].status = cpu_to_le32(T_OWN);

	OUTL(dev, POLL_DEMAND, DE4X5_TPD);

	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
		if (i >= TOUT_LOOP) {
			printf("%s: tx buffer not ready\n", dev->name);
			goto Done;
		}
	}

	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
		printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
	}
Done:
	return;
}

/* SROM Read and write routines.
 */

static void
sendto_srom(struct eth_device* dev, u_int command, u_long addr)
{
	OUTL(dev, command, addr);
	udelay(1);
}

static int
getfrom_srom(struct eth_device* dev, u_long addr)
{
	s32 tmp;

	tmp = INL(dev, addr);
	udelay(1);

	return tmp;
}

/* Note: this routine returns extra data bits for size detection. */
static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
{
	int i;
	unsigned retval = 0;
	int read_cmd = location | (SROM_READ_CMD << addr_len);

	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);

#ifdef DEBUG_SROM
	printf(" EEPROM read at %d ", location);
#endif

	/* Shift the read command bits out. */
	for (i = 4 + addr_len; i >= 0; i--) {
		short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
		udelay(10);
		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
		udelay(10);
#ifdef DEBUG_SROM2
		printf("%X", getfrom_srom(dev, ioaddr) & 15);
#endif
		retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
	}

	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);

#ifdef DEBUG_SROM2
	printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
#endif

	for (i = 16; i > 0; i--) {
		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
		udelay(10);
#ifdef DEBUG_SROM2
		printf("%X", getfrom_srom(dev, ioaddr) & 15);
#endif
		retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
		udelay(10);
	}

	/* Terminate the EEPROM access. */
	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);

#ifdef DEBUG_SROM2
	printf(" EEPROM value at %d is %5.5x.\n", location, retval);
#endif

	return retval;
}

/* This executes a generic EEPROM command, typically a write or write enable.
   It returns the data output from the EEPROM, and thus may also be used for
   reads. */
static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
{
	unsigned retval = 0;

#ifdef DEBUG_SROM
	printf(" EEPROM op 0x%x: ", cmd);
#endif

	sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);

	/* Shift the command bits out. */
	do {
		short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
		sendto_srom(dev,dataval, ioaddr);
		udelay(10);

#ifdef DEBUG_SROM2
		printf("%X", getfrom_srom(dev,ioaddr) & 15);
#endif

		sendto_srom(dev,dataval | DT_CLK, ioaddr);
		udelay(10);
		retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
	} while (--cmd_len >= 0);
	sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);

	/* Terminate the EEPROM access. */
	sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);

#ifdef DEBUG_SROM
	printf(" EEPROM result is 0x%5.5x.\n", retval);
#endif

	return retval;
}

static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
{
	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;

	return do_eeprom_cmd(dev, ioaddr,
			     (((SROM_READ_CMD << ee_addr_size) | index) << 16)
			     | 0xffff, 3 + ee_addr_size + 16);
}

#ifdef UPDATE_SROM
static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
{
	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
	int i;
	unsigned short newval;

	udelay(10*1000); /* test-only */

#ifdef DEBUG_SROM
	printf("ee_addr_size=%d.\n", ee_addr_size);
	printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
#endif

	/* Enable programming modes. */
	do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);

	/* Do the actual write. */
	do_eeprom_cmd(dev, ioaddr,
		      (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
		      3 + ee_addr_size + 16);

	/* Poll for write finished. */
	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
	for (i = 0; i < 10000; i++)			/* Typical 2000 ticks */
		if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
			break;

#ifdef DEBUG_SROM
	printf(" Write finished after %d ticks.\n", i);
#endif

	/* Disable programming. */
	do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);

	/* And read the result. */
	newval = do_eeprom_cmd(dev, ioaddr,
			       (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
			       | 0xffff, 3 + ee_addr_size + 16);
#ifdef DEBUG_SROM
	printf("  New value at offset %d is %4.4x.\n", index, newval);
#endif
	return 1;
}
#endif

static void read_hw_addr(struct eth_device *dev, bd_t *bis)
{
	u_short tmp, *p = (short *)(&dev->enetaddr[0]);
	int i, j = 0;

	for (i = 0; i < (ETH_ALEN >> 1); i++) {
		tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
		*p = le16_to_cpu(tmp);
		j += *p++;
	}

	if ((j == 0) || (j == 0x2fffd)) {
		memset (dev->enetaddr, 0, ETH_ALEN);
#ifdef DEBUG
		printf("Warning: can't read HW address from SROM.\n");
#endif
		goto Done;
	}

	return;

Done:
#ifdef UPDATE_SROM
	update_srom(dev, bis);
#endif
	return;
}

#ifdef UPDATE_SROM
static void update_srom(struct eth_device *dev, bd_t *bis)
{
	int i;
	static unsigned short eeprom[0x40] = {
		0x140b, 0x6610, 0x0000, 0x0000, 	/* 00 */
		0x0000, 0x0000, 0x0000, 0x0000, 	/* 04 */
		0x00a3, 0x0103, 0x0000, 0x0000,  	/* 08 */
		0x0000, 0x1f00, 0x0000, 0x0000, 	/* 0c */
		0x0108, 0x038d, 0x0000, 0x0000,  	/* 10 */
		0xe078, 0x0001, 0x0040, 0x0018, 	/* 14 */
		0x0000, 0x0000, 0x0000, 0x0000,  	/* 18 */
		0x0000, 0x0000, 0x0000, 0x0000, 	/* 1c */
		0x0000, 0x0000, 0x0000, 0x0000,  	/* 20 */
		0x0000, 0x0000, 0x0000, 0x0000, 	/* 24 */
		0x0000, 0x0000, 0x0000, 0x0000,  	/* 28 */
		0x0000, 0x0000, 0x0000, 0x0000, 	/* 2c */
		0x0000, 0x0000, 0x0000, 0x0000,  	/* 30 */
		0x0000, 0x0000, 0x0000, 0x0000, 	/* 34 */
		0x0000, 0x0000, 0x0000, 0x0000,  	/* 38 */
		0x0000, 0x0000, 0x0000, 0x4e07,		/* 3c */
	};

	/* Ethernet Addr... */
	eeprom[0x0a] = ((bis->bi_enetaddr[1] & 0xff) << 8) | (bis->bi_enetaddr[0] & 0xff);
	eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff);
	eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff);

	for (i=0; i<0x40; i++)
	{
		write_srom(dev, DE4X5_APROM, i, eeprom[i]);
	}
}
#endif

#endif
Commit	Line	Data
c609719b WD	1	/*
	2	* See file CREDITS for list of people who contributed to this
	3	* project.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20
	21	#include <common.h>
	22
	23	#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
	24	&& defined(CONFIG_TULIP)
	25
	26	#include <malloc.h>
	27	#include <net.h>
	28	#include <pci.h>
	29
	30	#undef DEBUG
	31	#undef DEBUG_SROM
	32	#undef DEBUG_SROM2
	33
	34	#undef UPDATE_SROM
	35
	36	/* PCI Registers.
	37	*/
	38	#define PCI_CFDA_PSM 0x43
	39
	40	#define CFRV_RN 0x000000f0 /* Revision Number */
	41
	42	#define WAKEUP 0x00 /* Power Saving Wakeup */
	43	#define SLEEP 0x80 /* Power Saving Sleep Mode */
	44
	45	#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
	46
	47	/* Ethernet chip registers.
	48	*/
	49	#define DE4X5_BMR 0x000 /* Bus Mode Register */
	50	#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
	51	#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
	52	#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
	53	#define DE4X5_STS 0x028 /* Status Register */
	54	#define DE4X5_OMR 0x030 /* Operation Mode Register */
	55	#define DE4X5_SICR 0x068 /* SIA Connectivity Register */
	56	#define DE4X5_APROM 0x048 /* Ethernet Address PROM */
	57
	58	/* Register bits.
	59	*/
	60	#define BMR_SWR 0x00000001 /* Software Reset */
	61	#define STS_TS 0x00700000 /* Transmit Process State */
	62	#define STS_RS 0x000e0000 /* Receive Process State */
	63	#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
	64	#define OMR_SR 0x00000002 /* Start/Stop Receive */
65	#define OMR_PS 0x00040000 /* Port Select */
66	#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
67	#define OMR_PM 0x00000080 /* Pass All Multicast */
68
69	/* Descriptor bits.
70	*/
71	#define R_OWN 0x80000000 /* Own Bit */
72	#define RD_RER 0x02000000 /* Receive End Of Ring */
73	#define RD_LS 0x00000100 /* Last Descriptor */
74	#define RD_ES 0x00008000 /* Error Summary */
75	#define TD_TER 0x02000000 /* Transmit End Of Ring */
76	#define T_OWN 0x80000000 /* Own Bit */
77	#define TD_LS 0x40000000 /* Last Segment */
78	#define TD_FS 0x20000000 /* First Segment */
79	#define TD_ES 0x00008000 /* Error Summary */
80	#define TD_SET 0x08000000 /* Setup Packet */
81
82	/* The EEPROM commands include the alway-set leading bit. */
83	#define SROM_WRITE_CMD 5
84	#define SROM_READ_CMD 6
85	#define SROM_ERASE_CMD 7
86
87	#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
88	#define SROM_RD 0x00004000 /* Read from Boot ROM */
89	#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
90	#define EE_WRITE_0 0x4801
91	#define EE_WRITE_1 0x4805
92	#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
93	#define SROM_SR 0x00000800 /* Select Serial ROM when set */
94
95	#define DT_IN 0x00000004 /* Serial Data In */
96	#define DT_CLK 0x00000002 /* Serial ROM Clock */
97	#define DT_CS 0x00000001 /* Serial ROM Chip Select */
98
99	#define POLL_DEMAND 1
100
101	#define RESET_DE4X5(dev) {\
102	int i;\
103	i=INL(dev, DE4X5_BMR);\
104	udelay(1000);\
105	OUTL(dev, i \| BMR_SWR, DE4X5_BMR);\
106	udelay(1000);\
107	OUTL(dev, i, DE4X5_BMR);\
108	udelay(1000);\
109	for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
110	udelay(1000);\
111	}
112
113	#define START_DE4X5(dev) {\
114	s32 omr; \
115	omr = INL(dev, DE4X5_OMR);\
116	omr \|= OMR_ST \| OMR_SR;\
117	OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
118	}
119
120	#define STOP_DE4X5(dev) {\
121	s32 omr; \
122	omr = INL(dev, DE4X5_OMR);\
123	omr &= ~(OMR_ST\|OMR_SR);\
124	OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
125	}
126
127	#define NUM_RX_DESC PKTBUFSRX
128	#define NUM_TX_DESC 1 /* Number of TX descriptors */
129	#define RX_BUFF_SZ PKTSIZE_ALIGN
130
131	#define TOUT_LOOP 1000000
132
133	#define SETUP_FRAME_LEN 192
134	#define ETH_ALEN 6
135
136
137	struct de4x5_desc {
138	volatile s32 status;
139	u32 des1;
140	u32 buf;
141	u32 next;
142	};
143
144	static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
145	static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
146	static int rx_new; /* RX descriptor ring pointer */
147	static int tx_new; /* TX descriptor ring pointer */
148
149	static char rxRingSize;
150	static char txRingSize;
151
152	static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
153	static int getfrom_srom(struct eth_device* dev, u_long addr);
154	static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len);
155	static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len);
156	static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
157	#ifdef UPDATE_SROM
158	static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
159	static void update_srom(struct eth_device dev, bd_t bis);
160	#endif
161	static void read_hw_addr(struct eth_device* dev, bd_t * bis);
162	static void send_setup_frame(struct eth_device* dev, bd_t * bis);
163
164	static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
165	static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length);
166	static int dc21x4x_recv(struct eth_device* dev);
167	static void dc21x4x_halt(struct eth_device* dev);
168	#ifdef CONFIG_TULIP_SELECT_MEDIA
169	extern void dc21x4x_select_media(struct eth_device* dev);
170	#endif
171
42d1f039 WD	172	#if defined(CONFIG_E500)
	173	#define phys_to_bus(a) (a)
	174	#else
c609719b	175	#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
42d1f039	176	#endif
c609719b WD	177
	178	static int INL(struct eth_device* dev, u_long addr)
	179	{
	180	return le32_to_cpu((volatile u_long )(addr + dev->iobase));
	181	}
	182
	183	static void OUTL(struct eth_device* dev, int command, u_long addr)
	184	{
	185	(volatile u_long )(addr + dev->iobase) = cpu_to_le32(command);
	186	}
	187
	188	static struct pci_device_id supported[] = {
	189	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
	190	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
	191	{ }
	192	};
	193
	194	int dc21x4x_initialize(bd_t *bis)
	195	{
	196	int idx=0;
	197	int card_number = 0;
	198	int cfrv;
	199	unsigned char timer;
	200	pci_dev_t devbusfn;
	201	unsigned int iobase;
	202	unsigned short status;
	203	struct eth_device* dev;
	204
	205	while(1) {
	206	devbusfn = pci_find_devices(supported, idx++);
	207	if (devbusfn == -1) {
	208	break;
	209	}
	210
	211	/* Get the chip configuration revision register. */
	212	pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
	213
	214	if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
	215	printf("Error: The chip is not DC21143.\n");
	216	continue;
	217	}
	218
	219	pci_read_config_word(devbusfn, PCI_COMMAND, &status);
	220	status \|=
	221	#ifdef CONFIG_TULIP_USE_IO
	222	PCI_COMMAND_IO \|
	223	#else
	224	PCI_COMMAND_MEMORY \|
	225	#endif
	226	PCI_COMMAND_MASTER;
	227	pci_write_config_word(devbusfn, PCI_COMMAND, status);
	228
	229	pci_read_config_word(devbusfn, PCI_COMMAND, &status);
	230	if (!(status & PCI_COMMAND_IO)) {
	231	printf("Error: Can not enable I/O access.\n");
	232	continue;
	233	}
	234
	235	if (!(status & PCI_COMMAND_IO)) {
	236	printf("Error: Can not enable I/O access.\n");
	237	continue;
	238	}
	239
	240	if (!(status & PCI_COMMAND_MASTER)) {
241	printf("Error: Can not enable Bus Mastering.\n");
242	continue;
243	}
244
245	/* Check the latency timer for values >= 0x60. */
246	pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
247
248	if (timer < 0x60) {
249	pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
250	}
251
252	#ifdef CONFIG_TULIP_USE_IO
253	/* read BAR for memory space access */
254	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
255	iobase &= PCI_BASE_ADDRESS_IO_MASK;
256	#else
257	/* read BAR for memory space access */
258	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
259	iobase &= PCI_BASE_ADDRESS_MEM_MASK;
260	#endif
261
262	#ifdef DEBUG
263	printf("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
264	#endif
265
266	dev = (struct eth_device) malloc(sizeof dev);
267
268	sprintf(dev->name, "dc21x4x#%d", card_number);
269	#ifdef CONFIG_TULIP_USE_IO
270	dev->iobase = pci_io_to_phys(devbusfn, iobase);
271	#else
272	dev->iobase = pci_mem_to_phys(devbusfn, iobase);
273	#endif
274	dev->priv = (void*) devbusfn;
275	dev->init = dc21x4x_init;
276	dev->halt = dc21x4x_halt;
277	dev->send = dc21x4x_send;
278	dev->recv = dc21x4x_recv;
279
280	/* Ensure we're not sleeping. */
281	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
282
283	udelay(10 * 1000);
284
285	read_hw_addr(dev, bis);
286
287	eth_register(dev);
288
289	card_number++;
290	}
291
292	return card_number;
293	}
294
295	static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
296	{
297	int i;
298	int devbusfn = (int) dev->priv;
299
300	/* Ensure we're not sleeping. */
301	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
302
303	RESET_DE4X5(dev);
304
305	if ((INL(dev, DE4X5_STS) & (STS_TS \| STS_RS)) != 0) {
306	printf("Error: Cannot reset ethernet controller.\n");
307	return 0;
308	}
309
310	#ifdef CONFIG_TULIP_SELECT_MEDIA
311	dc21x4x_select_media(dev);
312	#else
313	OUTL(dev, OMR_SDP \| OMR_PS \| OMR_PM, DE4X5_OMR);
314	#endif
315
316	for (i = 0; i < NUM_RX_DESC; i++) {
317	rx_ring[i].status = cpu_to_le32(R_OWN);
318	rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
319	rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i]));
320	rx_ring[i].next = 0;
321	}
322
323	for (i=0; i < NUM_TX_DESC; i++) {
324	tx_ring[i].status = 0;
325	tx_ring[i].des1 = 0;
326	tx_ring[i].buf = 0;
327	tx_ring[i].next = 0;
328	}
329
330	rxRingSize = NUM_RX_DESC;
331	txRingSize = NUM_TX_DESC;
332
333	/* Write the end of list marker to the descriptor lists. */
334	rx_ring[rxRingSize - 1].des1 \|= cpu_to_le32(RD_RER);
335	tx_ring[txRingSize - 1].des1 \|= cpu_to_le32(TD_TER);
336
337	/* Tell the adapter where the TX/RX rings are located. */
338	OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
339	OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
340
341	START_DE4X5(dev);
342
343	tx_new = 0;
344	rx_new = 0;
345
346	send_setup_frame(dev, bis);
347
348	return 1;
349	}
350
351	static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length)
352	{
353	int status = -1;
354	int i;
355
356	if (length <= 0) {
357	printf("%s: bad packet size: %d\n", dev->name, length);
358	goto Done;
359	}
360
361	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
362	if (i >= TOUT_LOOP) {
363	printf("%s: tx error buffer not ready\n", dev->name);
364	goto Done;
365	}
366	}
367
368	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet));
369	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER \| TD_LS \| TD_FS \| length);
370	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
371
372	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
373
374	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
375	if (i >= TOUT_LOOP) {
376	printf(".%s: tx buffer not ready\n", dev->name);
377	goto Done;
378	}
379	}
380
381	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
382	#if 0 /* test-only */
383	printf("TX error status = 0x%08X\n",
384	le32_to_cpu(tx_ring[tx_new].status));
385	#endif
386	goto Done;
387	}
388
389	status = length;
390
391	Done:
392	return status;
393	}
394
395	static int dc21x4x_recv(struct eth_device* dev)
396	{
397	s32 status;
398	int length = 0;
399
400	for ( ; ; ) {
401	status = (s32)le32_to_cpu(rx_ring[rx_new].status);
402
403	if (status & R_OWN) {
404	break;
405	}
406
407	if (status & RD_LS) {
408	/* Valid frame status.
409	*/
410	if (status & RD_ES) {
411
412	/* There was an error.
413	*/
414	printf("RX error status = 0x%08X\n", status);
415	} else {
416	/* A valid frame received.
417	*/
418	length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
419
420	/* Pass the packet up to the protocol
421	* layers.
422	*/
423	NetReceive(NetRxPackets[rx_new], length - 4);
424	}
425
426	/* Change buffer ownership for this frame, back
427	* to the adapter.
428	*/
429	rx_ring[rx_new].status = cpu_to_le32(R_OWN);
430	}
431
432	/* Update entry information.
433	*/
434	rx_new = (rx_new + 1) % rxRingSize;
435	}
436
437	return length;
438	}
439
440	static void dc21x4x_halt(struct eth_device* dev)
441	{
442	int devbusfn = (int) dev->priv;
443
444	STOP_DE4X5(dev);
445	OUTL(dev, 0, DE4X5_SICR);
446
447	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
448	}
449
450	static void send_setup_frame(struct eth_device* dev, bd_t *bis)
451	{
452	int i;
453	char setup_frame[SETUP_FRAME_LEN];
454	char *pa = &setup_frame[0];
455
456	memset(pa, 0xff, SETUP_FRAME_LEN);
457
458	for (i = 0; i < ETH_ALEN; i++) {
459	*(pa + (i & 1)) = dev->enetaddr[i];
460	if (i & 0x01) {
461	pa += 4;
462	}
463	}
464
465	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
466	if (i >= TOUT_LOOP) {
467	printf("%s: tx error buffer not ready\n", dev->name);
468	goto Done;
469	}
470	}
471
472	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
473	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER \| TD_SET\| SETUP_FRAME_LEN);
474	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
475
476	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
477
478	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
479	if (i >= TOUT_LOOP) {
480	printf("%s: tx buffer not ready\n", dev->name);
481	goto Done;
482	}
483	}
484
485	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
486	printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
487	}
488	Done:
489	return;
490	}
491
492	/* SROM Read and write routines.
493	*/
494
495	static void
496	sendto_srom(struct eth_device* dev, u_int command, u_long addr)
497	{
498	OUTL(dev, command, addr);
499	udelay(1);
500	}
501
502	static int
503	getfrom_srom(struct eth_device* dev, u_long addr)
504	{
505	s32 tmp;
506
507	tmp = INL(dev, addr);
508	udelay(1);
509
510	return tmp;
511	}
512
513	/* Note: this routine returns extra data bits for size detection. */
514	static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
515	{
516	int i;
517	unsigned retval = 0;
518	int read_cmd = location \| (SROM_READ_CMD << addr_len);
519
520	sendto_srom(dev, SROM_RD \| SROM_SR, ioaddr);
521	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS, ioaddr);
522
523	#ifdef DEBUG_SROM
524	printf(" EEPROM read at %d ", location);
525	#endif
526
527	/* Shift the read command bits out. */
528	for (i = 4 + addr_len; i >= 0; i--) {
529	short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
530	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS \| dataval, ioaddr);
531	udelay(10);
532	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS \| dataval \| DT_CLK, ioaddr);
533	udelay(10);
534	#ifdef DEBUG_SROM2
535	printf("%X", getfrom_srom(dev, ioaddr) & 15);
536	#endif
537	retval = (retval << 1) \| ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
538	}
539
540	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS, ioaddr);
541
542	#ifdef DEBUG_SROM2
543	printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
544	#endif
545
546	for (i = 16; i > 0; i--) {
547	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS \| DT_CLK, ioaddr);
548	udelay(10);
549	#ifdef DEBUG_SROM2
550	printf("%X", getfrom_srom(dev, ioaddr) & 15);
551	#endif
552	retval = (retval << 1) \| ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
553	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS, ioaddr);
554	udelay(10);
555	}
556
557	/* Terminate the EEPROM access. */
558	sendto_srom(dev, SROM_RD \| SROM_SR, ioaddr);
559
560	#ifdef DEBUG_SROM2
561	printf(" EEPROM value at %d is %5.5x.\n", location, retval);
562	#endif
563
564	return retval;
565	}
566
567	/* This executes a generic EEPROM command, typically a write or write enable.
568	It returns the data output from the EEPROM, and thus may also be used for
569	reads. */
570	static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
571	{
572	unsigned retval = 0;
573
574	#ifdef DEBUG_SROM
575	printf(" EEPROM op 0x%x: ", cmd);
576	#endif
577
578	sendto_srom(dev,SROM_RD \| SROM_SR \| DT_CS \| DT_CLK, ioaddr);
579
580	/* Shift the command bits out. */
581	do {
582	short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
583	sendto_srom(dev,dataval, ioaddr);
584	udelay(10);
585
586	#ifdef DEBUG_SROM2
587	printf("%X", getfrom_srom(dev,ioaddr) & 15);
588	#endif
589
590	sendto_srom(dev,dataval \| DT_CLK, ioaddr);
591	udelay(10);
592	retval = (retval << 1) \| ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
593	} while (--cmd_len >= 0);
594	sendto_srom(dev,SROM_RD \| SROM_SR \| DT_CS, ioaddr);
595
596	/* Terminate the EEPROM access. */
597	sendto_srom(dev,SROM_RD \| SROM_SR, ioaddr);
598
599	#ifdef DEBUG_SROM
600	printf(" EEPROM result is 0x%5.5x.\n", retval);
601	#endif
602
603	return retval;
604	}
605
606	static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
607	{
608	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
609
610	return do_eeprom_cmd(dev, ioaddr,
611	(((SROM_READ_CMD << ee_addr_size) \| index) << 16)
612	\| 0xffff, 3 + ee_addr_size + 16);
613	}
614
615	#ifdef UPDATE_SROM
616	static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
617	{
618	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
619	int i;
620	unsigned short newval;
621
622	udelay(101000); / test-only */
623
624	#ifdef DEBUG_SROM
625	printf("ee_addr_size=%d.\n", ee_addr_size);
626	printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
627	#endif
628
629	/* Enable programming modes. */
630	do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
631
632	/* Do the actual write. */
633	do_eeprom_cmd(dev, ioaddr,
634	(((SROM_WRITE_CMD<<ee_addr_size)\|index) << 16) \| new_value,
635	3 + ee_addr_size + 16);
636
637	/* Poll for write finished. */
638	sendto_srom(dev, SROM_RD \| SROM_SR \| DT_CS, ioaddr);
639	for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
640	if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
641	break;
642
643	#ifdef DEBUG_SROM
644	printf(" Write finished after %d ticks.\n", i);
645	#endif
646
647	/* Disable programming. */
648	do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
649
650	/* And read the result. */
651	newval = do_eeprom_cmd(dev, ioaddr,
652	(((SROM_READ_CMD<<ee_addr_size)\|index) << 16)
653	\| 0xffff, 3 + ee_addr_size + 16);
654	#ifdef DEBUG_SROM
655	printf(" New value at offset %d is %4.4x.\n", index, newval);
656	#endif
657	return 1;
658	}
659	#endif
660
661	static void read_hw_addr(struct eth_device dev, bd_t bis)
662	{
663	u_short tmp, p = (short )(&dev->enetaddr[0]);
664	int i, j = 0;
665
666	for (i = 0; i < (ETH_ALEN >> 1); i++) {
667	tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
668	*p = le16_to_cpu(tmp);
669	j += *p++;
670	}
671
672	if ((j == 0) \|\| (j == 0x2fffd)) {
673	memset (dev->enetaddr, 0, ETH_ALEN);
674	#ifdef DEBUG
675	printf("Warning: can't read HW address from SROM.\n");
676	#endif
677	goto Done;
678	}
679
680	return;
681
682	Done:
683	#ifdef UPDATE_SROM
684	update_srom(dev, bis);
685	#endif
686	return;
687	}
688
689	#ifdef UPDATE_SROM
690	static void update_srom(struct eth_device dev, bd_t bis)
691	{
692	int i;
693	static unsigned short eeprom[0x40] = {
694	0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
695	0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
696	0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
697	0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
698	0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
699	0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
700	0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
701	0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
702	0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
703	0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
704	0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
705	0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
706	0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
707	0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
708	0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
709	0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
710	};
711
712	/* Ethernet Addr... */
713	eeprom[0x0a] = ((bis->bi_enetaddr[1] & 0xff) << 8) \| (bis->bi_enetaddr[0] & 0xff);
714	eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) \| (bis->bi_enetaddr[2] & 0xff);
715	eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) \| (bis->bi_enetaddr[4] & 0xff);
716
717	for (i=0; i<0x40; i++)
718	{
719	write_srom(dev, DE4X5_APROM, i, eeprom[i]);
720	}
721	}
722	#endif
723
724	#endif