[people/ms/u-boot.git] / drivers / ddr / altera / sdram.c

/*
 * Copyright Altera Corporation (C) 2014-2015
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <errno.h>
#include <div64.h>
#include <watchdog.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/sdram.h>
#include <asm/arch/system_manager.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

struct sdram_prot_rule {
	u32	sdram_start;	/* SDRAM start address */
	u32	sdram_end;	/* SDRAM end address */
	u32	rule;		/* SDRAM protection rule number: 0-19 */
	int	valid;		/* Rule valid or not? 1 - valid, 0 not*/

	u32	security;
	u32	portmask;
	u32	result;
	u32	lo_prot_id;
	u32	hi_prot_id;
};

static struct socfpga_system_manager *sysmgr_regs =
	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct socfpga_sdr_ctrl *sdr_ctrl =
	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;

/**
 * get_errata_rows() - Up the number of DRAM rows to cover entire address space
 * @cfg:	SDRAM controller configuration data
 *
 * SDRAM Failure happens when accessing non-existent memory. Artificially
 * increase the number of rows so that the memory controller thinks it has
 * 4GB of RAM. This function returns such amount of rows.
 */
static int get_errata_rows(const struct socfpga_sdram_config *cfg)
{
	/* Define constant for 4G memory - used for SDRAM errata workaround */
#define MEMSIZE_4G	(4ULL * 1024ULL * 1024ULL * 1024ULL)
	const unsigned long long memsize = MEMSIZE_4G;
	const unsigned int cs =
		((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
	const unsigned int rows =
		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
	const unsigned int banks =
		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
	const unsigned int cols =
		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
	const unsigned int width = 8;

	unsigned long long newrows;
	int bits, inewrowslog2;

	debug("workaround rows - memsize %lld\n", memsize);
	debug("workaround rows - cs        %d\n", cs);
	debug("workaround rows - width     %d\n", width);
	debug("workaround rows - rows      %d\n", rows);
	debug("workaround rows - banks     %d\n", banks);
	debug("workaround rows - cols      %d\n", cols);

	newrows = lldiv(memsize, cs * (width / 8));
	debug("rows workaround - term1 %lld\n", newrows);

	newrows = lldiv(newrows, (1 << banks) * (1 << cols));
	debug("rows workaround - term2 %lld\n", newrows);

	/*
	 * Compute the hamming weight - same as number of bits set.
	 * Need to see if result is ordinal power of 2 before
	 * attempting log2 of result.
	 */
	bits = generic_hweight32(newrows);

	debug("rows workaround - bits %d\n", bits);

	if (bits != 1) {
		printf("SDRAM workaround failed, bits set %d\n", bits);
		return rows;
	}

	if (newrows > UINT_MAX) {
		printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
		return rows;
	}

	inewrowslog2 = __ilog2(newrows);

	debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);

	if (inewrowslog2 == -1) {
		printf("SDRAM workaround failed, newrows %lld\n", newrows);
		return rows;
	}

	return inewrowslog2;
}

/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
static void sdram_set_rule(struct sdram_prot_rule *prule)
{
	u32 lo_addr_bits;
	u32 hi_addr_bits;
	int ruleno = prule->rule;

	/* Select the rule */
	writel(ruleno, &sdr_ctrl->prot_rule_rdwr);

	/* Obtain the address bits */
	lo_addr_bits = prule->sdram_start >> 20ULL;
	hi_addr_bits = prule->sdram_end >> 20ULL;

	debug("sdram set rule start %x, %d\n", lo_addr_bits,
	      prule->sdram_start);
	debug("sdram set rule end   %x, %d\n", hi_addr_bits,
	      prule->sdram_end);

	/* Set rule addresses */
	writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);

	/* Set rule protection ids */
	writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
	       &sdr_ctrl->prot_rule_id);

	/* Set the rule data */
	writel(prule->security | (prule->valid << 2) |
	       (prule->portmask << 3) | (prule->result << 13),
	       &sdr_ctrl->prot_rule_data);

	/* write the rule */
	writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);

	/* Set rule number to 0 by default */
	writel(0, &sdr_ctrl->prot_rule_rdwr);
}

static void sdram_get_rule(struct sdram_prot_rule *prule)
{
	u32 addr;
	u32 id;
	u32 data;
	int ruleno = prule->rule;

	/* Read the rule */
	writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
	writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);

	/* Get the addresses */
	addr = readl(&sdr_ctrl->prot_rule_addr);
	prule->sdram_start = (addr & 0xFFF) << 20;
	prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;

	/* Get the configured protection IDs */
	id = readl(&sdr_ctrl->prot_rule_id);
	prule->lo_prot_id = id & 0xFFF;
	prule->hi_prot_id = (id >> 12) & 0xFFF;

	/* Get protection data */
	data = readl(&sdr_ctrl->prot_rule_data);

	prule->security = data & 0x3;
	prule->valid = (data >> 2) & 0x1;
	prule->portmask = (data >> 3) & 0x3FF;
	prule->result = (data >> 13) & 0x1;
}

static void
sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
{
	struct sdram_prot_rule rule;
	int rules;

	/* Start with accepting all SDRAM transaction */
	writel(0x0, &sdr_ctrl->protport_default);

	/* Clear all protection rules for warm boot case */
	memset(&rule, 0, sizeof(rule));

	for (rules = 0; rules < 20; rules++) {
		rule.rule = rules;
		sdram_set_rule(&rule);
	}

	/* new rule: accept SDRAM */
	rule.sdram_start = sdram_start;
	rule.sdram_end = sdram_end;
	rule.lo_prot_id = 0x0;
	rule.hi_prot_id = 0xFFF;
	rule.portmask = 0x3FF;
	rule.security = 0x3;
	rule.result = 0;
	rule.valid = 1;
	rule.rule = 0;

	/* set new rule */
	sdram_set_rule(&rule);

	/* default rule: reject everything */
	writel(0x3ff, &sdr_ctrl->protport_default);
}

static void sdram_dump_protection_config(void)
{
	struct sdram_prot_rule rule;
	int rules;

	debug("SDRAM Prot rule, default %x\n",
	      readl(&sdr_ctrl->protport_default));

	for (rules = 0; rules < 20; rules++) {
		rule.rule = rules;
		sdram_get_rule(&rule);
		debug("Rule %d, rules ...\n", rules);
		debug("    sdram start %x\n", rule.sdram_start);
		debug("    sdram end   %x\n", rule.sdram_end);
		debug("    low prot id %d, hi prot id %d\n",
		      rule.lo_prot_id,
		      rule.hi_prot_id);
		debug("    portmask %x\n", rule.portmask);
		debug("    security %d\n", rule.security);
		debug("    result %d\n", rule.result);
		debug("    valid %d\n", rule.valid);
	}
}

/**
 * sdram_write_verify() - write to register and verify the write.
 * @addr:	Register address
 * @val:	Value to be written and verified
 *
 * This function writes to a register, reads back the value and compares
 * the result with the written value to check if the data match.
 */
static unsigned sdram_write_verify(const u32 *addr, const u32 val)
{
	u32 rval;

	debug("   Write - Address 0x%p Data 0x%08x\n", addr, val);
	writel(val, addr);

	debug("   Read and verify...");
	rval = readl(addr);
	if (rval != val) {
		debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
		      addr, val, rval);
		return -EINVAL;
	}

	debug("correct!\n");
	return 0;
}

/**
 * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
 * @cfg:	SDRAM controller configuration data
 *
 * Return the value of DRAM CTRLCFG register.
 */
static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
{
	const u32 csbits =
		((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
	u32 addrorder =
		(cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;

	u32 ctrl_cfg = cfg->ctrl_cfg;

	/*
	 * SDRAM Failure When Accessing Non-Existent Memory
	 * Set the addrorder field of the SDRAM control register
	 * based on the CSBITs setting.
	 */
	if (csbits == 1) {
		if (addrorder != 0)
			debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
		addrorder = 0;
	} else if (csbits == 2) {
		if (addrorder != 2)
			debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
		addrorder = 2;
	}

	ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
	ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;

	return ctrl_cfg;
}

/**
 * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
 * @cfg:	SDRAM controller configuration data
 *
 * Return the value of DRAM ADDRW register.
 */
static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
{
	/*
	 * SDRAM Failure When Accessing Non-Existent Memory
	 * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
	 * log2(number of chip select bits). Since there's only
	 * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
	 * which is the same as "chip selects" - 1.
	 */
	const int rows = get_errata_rows(cfg);
	u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;

	return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
}

/**
 * sdr_load_regs() - Load SDRAM controller registers
 * @cfg:	SDRAM controller configuration data
 *
 * This function loads the register values into the SDRAM controller block.
 */
static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
{
	const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
	const u32 dram_addrw = sdr_get_addr_rw(cfg);

	debug("\nConfiguring CTRLCFG\n");
	writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);

	debug("Configuring DRAMTIMING1\n");
	writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);

	debug("Configuring DRAMTIMING2\n");
	writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);

	debug("Configuring DRAMTIMING3\n");
	writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);

	debug("Configuring DRAMTIMING4\n");
	writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);

	debug("Configuring LOWPWRTIMING\n");
	writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);

	debug("Configuring DRAMADDRW\n");
	writel(dram_addrw, &sdr_ctrl->dram_addrw);

	debug("Configuring DRAMIFWIDTH\n");
	writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);

	debug("Configuring DRAMDEVWIDTH\n");
	writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);

	debug("Configuring LOWPWREQ\n");
	writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);

	debug("Configuring DRAMINTR\n");
	writel(cfg->dram_intr, &sdr_ctrl->dram_intr);

	debug("Configuring STATICCFG\n");
	writel(cfg->static_cfg, &sdr_ctrl->static_cfg);

	debug("Configuring CTRLWIDTH\n");
	writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);

	debug("Configuring PORTCFG\n");
	writel(cfg->port_cfg, &sdr_ctrl->port_cfg);

	debug("Configuring FIFOCFG\n");
	writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);

	debug("Configuring MPPRIORITY\n");
	writel(cfg->mp_priority, &sdr_ctrl->mp_priority);

	debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
	writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
	writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
	writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
	writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);

	debug("Configuring MPPACING_MPPACING_0\n");
	writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
	writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
	writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
	writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);

	debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
	writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
	writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
	writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);

	debug("Configuring PHYCTRL_PHYCTRL_0\n");
	writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);

	debug("Configuring CPORTWIDTH\n");
	writel(cfg->cport_width, &sdr_ctrl->cport_width);

	debug("Configuring CPORTWMAP\n");
	writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);

	debug("Configuring CPORTRMAP\n");
	writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);

	debug("Configuring RFIFOCMAP\n");
	writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);

	debug("Configuring WFIFOCMAP\n");
	writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);

	debug("Configuring CPORTRDWR\n");
	writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);

	debug("Configuring DRAMODT\n");
	writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
}

/**
 * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 * @sdr_phy_reg:	Value of the PHY control register 0
 *
 * Initialize the SDRAM MMR.
 */
int sdram_mmr_init_full(unsigned int sdr_phy_reg)
{
	const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
	const unsigned int rows =
		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
	int ret;

	writel(rows, &sysmgr_regs->iswgrp_handoff[4]);

	sdr_load_regs(cfg);

	/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
	writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);

	/* only enable if the FPGA is programmed */
	if (fpgamgr_test_fpga_ready()) {
		ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
					 cfg->fpgaport_rst);
		if (ret)
			return ret;
	}

	/* Restore the SDR PHY Register if valid */
	if (sdr_phy_reg != 0xffffffff)
		writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);

	/* Final step - apply configuration changes */
	debug("Configuring STATICCFG\n");
	clrsetbits_le32(&sdr_ctrl->static_cfg,
			SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
			1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);

	sdram_set_protection_config(0, sdram_calculate_size() - 1);

	sdram_dump_protection_config();

	return 0;
}

/**
 * sdram_calculate_size() - Calculate SDRAM size
 *
 * Calculate SDRAM device size based on SDRAM controller parameters.
 * Size is specified in bytes.
 */
unsigned long sdram_calculate_size(void)
{
	unsigned long temp;
	unsigned long row, bank, col, cs, width;
	const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
	const unsigned int csbits =
		((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
	const unsigned int rowbits =
		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;

	temp = readl(&sdr_ctrl->dram_addrw);
	col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
		SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;

	/*
	 * SDRAM Failure When Accessing Non-Existent Memory
	 * Use ROWBITS from Quartus/QSys to calculate SDRAM size
	 * since the FB specifies we modify ROWBITs to work around SDRAM
	 * controller issue.
	 */
	row = readl(&sysmgr_regs->iswgrp_handoff[4]);
	if (row == 0)
		row = rowbits;
	/*
	 * If the stored handoff value for rows is greater than
	 * the field width in the sdr.dramaddrw register then
	 * something is very wrong. Revert to using the the #define
	 * value handed off by the SOCEDS tool chain instead of
	 * using a broken value.
	 */
	if (row > 31)
		row = rowbits;

	bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
		SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;

	/*
	 * SDRAM Failure When Accessing Non-Existent Memory
	 * Use CSBITs from Quartus/QSys to calculate SDRAM size
	 * since the FB specifies we modify CSBITs to work around SDRAM
	 * controller issue.
	 */
	cs = csbits;

	width = readl(&sdr_ctrl->dram_if_width);

	/* ECC would not be calculated as its not addressible */
	if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
		width = 32;
	if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
		width = 16;

	/* calculate the SDRAM size base on this info */
	temp = 1 << (row + bank + col);
	temp = temp * cs * (width  / 8);

	debug("%s returns %ld\n", __func__, temp);

	return temp;
}
Commit	Line	Data
9bbd2132 DN	1	/*
	2	* Copyright Altera Corporation (C) 2014-2015
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#include <common.h>
99f453e9	7	#include <errno.h>
9bbd2132 DN	8	#include <div64.h>
	9	#include <watchdog.h>
	10	#include <asm/arch/fpga_manager.h>
	11	#include <asm/arch/sdram.h>
9bbd2132 DN	12	#include <asm/arch/system_manager.h>
	13	#include <asm/io.h>
	14
9bbd2132 DN	15	DECLARE_GLOBAL_DATA_PTR;
9bbd2132 DN	16
42f7ebb8	17	struct sdram_prot_rule {
08eb9470 MV	18	u32 sdram_start; /* SDRAM start address */
08eb9470 MV	19	u32 sdram_end; /* SDRAM end address */
42f7ebb8 MV	20	u32 rule; /* SDRAM protection rule number: 0-19 */
	21	int valid; /* Rule valid or not? 1 - valid, 0 not*/
	22
	23	u32 security;
	24	u32 portmask;
	25	u32 result;
	26	u32 lo_prot_id;
	27	u32 hi_prot_id;
	28	};
	29
9bbd2132 DN	30	static struct socfpga_system_manager *sysmgr_regs =
	31	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
	32	static struct socfpga_sdr_ctrl *sdr_ctrl =
17fdc916	33	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
9bbd2132	34
f3671697 MV	35	/**
f3671697 MV	36	* get_errata_rows() - Up the number of DRAM rows to cover entire address space
764aa9a9	37	* @cfg: SDRAM controller configuration data
f3671697 MV	38	*
	39	* SDRAM Failure happens when accessing non-existent memory. Artificially
	40	* increase the number of rows so that the memory controller thinks it has
	41	* 4GB of RAM. This function returns such amount of rows.
	42	*/
5af91418	43	static int get_errata_rows(const struct socfpga_sdram_config *cfg)
9bbd2132	44	{
f3671697 MV	45	/* Define constant for 4G memory - used for SDRAM errata workaround */
	46	#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
	47	const unsigned long long memsize = MEMSIZE_4G;
764aa9a9 MV	48	const unsigned int cs =
	49	((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
	50	SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
	51	const unsigned int rows =
	52	(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
	53	SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
	54	const unsigned int banks =
	55	(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
	56	SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
	57	const unsigned int cols =
	58	(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
	59	SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
f3671697 MV	60	const unsigned int width = 8;
f3671697 MV	61
9bbd2132	62	unsigned long long newrows;
f3671697	63	int bits, inewrowslog2;
9bbd2132 DN	64
	65	debug("workaround rows - memsize %lld\n", memsize);
	66	debug("workaround rows - cs %d\n", cs);
	67	debug("workaround rows - width %d\n", width);
	68	debug("workaround rows - rows %d\n", rows);
	69	debug("workaround rows - banks %d\n", banks);
	70	debug("workaround rows - cols %d\n", cols);
	71
791d20e1	72	newrows = lldiv(memsize, cs * (width / 8));
9bbd2132 DN	73	debug("rows workaround - term1 %lld\n", newrows);
9bbd2132 DN	74
791d20e1	75	newrows = lldiv(newrows, (1 << banks) * (1 << cols));
9bbd2132 DN	76	debug("rows workaround - term2 %lld\n", newrows);
9bbd2132 DN	77
791d20e1 MV	78	/*
791d20e1 MV	79	* Compute the hamming weight - same as number of bits set.
9bbd2132 DN	80	* Need to see if result is ordinal power of 2 before
	81	* attempting log2 of result.
	82	*/
58d86144	83	bits = generic_hweight32(newrows);
9bbd2132 DN	84
	85	debug("rows workaround - bits %d\n", bits);
	86
	87	if (bits != 1) {
	88	printf("SDRAM workaround failed, bits set %d\n", bits);
	89	return rows;
	90	}
	91
	92	if (newrows > UINT_MAX) {
	93	printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
	94	return rows;
	95	}
	96
791d20e1	97	inewrowslog2 = __ilog2(newrows);
9bbd2132	98
791d20e1	99	debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
9bbd2132 DN	100
9bbd2132 DN	101	if (inewrowslog2 == -1) {
791d20e1	102	printf("SDRAM workaround failed, newrows %lld\n", newrows);
9bbd2132 DN	103	return rows;
	104	}
	105
	106	return inewrowslog2;
	107	}
	108
	109	/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
	110	static void sdram_set_rule(struct sdram_prot_rule *prule)
	111	{
08eb9470 MV	112	u32 lo_addr_bits;
08eb9470 MV	113	u32 hi_addr_bits;
9bbd2132 DN	114	int ruleno = prule->rule;
	115
	116	/* Select the rule */
	117	writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
	118
	119	/* Obtain the address bits */
a003740a	120	lo_addr_bits = prule->sdram_start >> 20ULL;
08eb9470	121	hi_addr_bits = prule->sdram_end >> 20ULL;
9bbd2132	122
08eb9470	123	debug("sdram set rule start %x, %d\n", lo_addr_bits,
9bbd2132	124	prule->sdram_start);
08eb9470	125	debug("sdram set rule end %x, %d\n", hi_addr_bits,
9bbd2132 DN	126	prule->sdram_end);
	127
	128	/* Set rule addresses */
	129	writel(lo_addr_bits \| (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
	130
	131	/* Set rule protection ids */
	132	writel(prule->lo_prot_id \| (prule->hi_prot_id << 12),
	133	&sdr_ctrl->prot_rule_id);
	134
	135	/* Set the rule data */
	136	writel(prule->security \| (prule->valid << 2) \|
	137	(prule->portmask << 3) \| (prule->result << 13),
	138	&sdr_ctrl->prot_rule_data);
	139
	140	/* write the rule */
a003740a	141	writel(ruleno \| (1 << 5), &sdr_ctrl->prot_rule_rdwr);
9bbd2132 DN	142
	143	/* Set rule number to 0 by default */
	144	writel(0, &sdr_ctrl->prot_rule_rdwr);
	145	}
	146
	147	static void sdram_get_rule(struct sdram_prot_rule *prule)
	148	{
6d01595f MV	149	u32 addr;
	150	u32 id;
	151	u32 data;
9bbd2132 DN	152	int ruleno = prule->rule;
	153
	154	/* Read the rule */
	155	writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
6d01595f	156	writel(ruleno \| (1 << 6), &sdr_ctrl->prot_rule_rdwr);
9bbd2132 DN	157
	158	/* Get the addresses */
	159	addr = readl(&sdr_ctrl->prot_rule_addr);
	160	prule->sdram_start = (addr & 0xFFF) << 20;
	161	prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
	162
	163	/* Get the configured protection IDs */
	164	id = readl(&sdr_ctrl->prot_rule_id);
	165	prule->lo_prot_id = id & 0xFFF;
	166	prule->hi_prot_id = (id >> 12) & 0xFFF;
	167
	168	/* Get protection data */
	169	data = readl(&sdr_ctrl->prot_rule_data);
	170
	171	prule->security = data & 0x3;
	172	prule->valid = (data >> 2) & 0x1;
	173	prule->portmask = (data >> 3) & 0x3FF;
	174	prule->result = (data >> 13) & 0x1;
	175	}
	176
08eb9470 MV	177	static void
08eb9470 MV	178	sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
9bbd2132 DN	179	{
	180	struct sdram_prot_rule rule;
	181	int rules;
	182
	183	/* Start with accepting all SDRAM transaction */
	184	writel(0x0, &sdr_ctrl->protport_default);
	185
	186	/* Clear all protection rules for warm boot case */
a003740a	187	memset(&rule, 0, sizeof(rule));
9bbd2132 DN	188
	189	for (rules = 0; rules < 20; rules++) {
	190	rule.rule = rules;
	191	sdram_set_rule(&rule);
	192	}
	193
	194	/* new rule: accept SDRAM */
	195	rule.sdram_start = sdram_start;
	196	rule.sdram_end = sdram_end;
	197	rule.lo_prot_id = 0x0;
	198	rule.hi_prot_id = 0xFFF;
	199	rule.portmask = 0x3FF;
	200	rule.security = 0x3;
	201	rule.result = 0;
	202	rule.valid = 1;
	203	rule.rule = 0;
	204
	205	/* set new rule */
	206	sdram_set_rule(&rule);
	207
	208	/* default rule: reject everything */
	209	writel(0x3ff, &sdr_ctrl->protport_default);
	210	}
	211
	212	static void sdram_dump_protection_config(void)
	213	{
	214	struct sdram_prot_rule rule;
	215	int rules;
	216
	217	debug("SDRAM Prot rule, default %x\n",
	218	readl(&sdr_ctrl->protport_default));
	219
	220	for (rules = 0; rules < 20; rules++) {
1720fad0	221	rule.rule = rules;
9bbd2132 DN	222	sdram_get_rule(&rule);
9bbd2132 DN	223	debug("Rule %d, rules ...\n", rules);
08eb9470 MV	224	debug(" sdram start %x\n", rule.sdram_start);
08eb9470 MV	225	debug(" sdram end %x\n", rule.sdram_end);
9bbd2132 DN	226	debug(" low prot id %d, hi prot id %d\n",
	227	rule.lo_prot_id,
	228	rule.hi_prot_id);
	229	debug(" portmask %x\n", rule.portmask);
	230	debug(" security %d\n", rule.security);
	231	debug(" result %d\n", rule.result);
	232	debug(" valid %d\n", rule.valid);
	233	}
	234	}
	235
269de4f0 MV	236	/**
	237	* sdram_write_verify() - write to register and verify the write.
	238	* @addr: Register address
	239	* @val: Value to be written and verified
	240	*
	241	* This function writes to a register, reads back the value and compares
	242	* the result with the written value to check if the data match.
	243	*/
	244	static unsigned sdram_write_verify(const u32 *addr, const u32 val)
9bbd2132	245	{
269de4f0 MV	246	u32 rval;
	247
	248	debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
	249	writel(val, addr);
	250
9bbd2132	251	debug(" Read and verify...");
269de4f0 MV	252	rval = readl(addr);
	253	if (rval != val) {
	254	debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
	255	addr, val, rval);
	256	return -EINVAL;
9bbd2132	257	}
269de4f0	258
9bbd2132	259	debug("correct!\n");
9bbd2132 DN	260	return 0;
	261	}
	262
96b869b6 MV	263	/**
	264	* sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
	265	* @cfg: SDRAM controller configuration data
	266	*
	267	* Return the value of DRAM CTRLCFG register.
	268	*/
5af91418	269	static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
9bbd2132	270	{
764aa9a9 MV	271	const u32 csbits =
	272	((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
	273	SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
	274	u32 addrorder =
	275	(cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
	276	SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
	277
04ae4489	278	u32 ctrl_cfg = cfg->ctrl_cfg;
9bbd2132	279
067c853f MV	280	/*
067c853f MV	281	* SDRAM Failure When Accessing Non-Existent Memory
9bbd2132 DN	282	* Set the addrorder field of the SDRAM control register
	283	* based on the CSBITs setting.
	284	*/
764aa9a9 MV	285	if (csbits == 1) {
764aa9a9 MV	286	if (addrorder != 0)
067c853f	287	debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
764aa9a9 MV	288	addrorder = 0;
	289	} else if (csbits == 2) {
	290	if (addrorder != 2)
067c853f	291	debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
764aa9a9	292	addrorder = 2;
9bbd2132 DN	293	}
9bbd2132 DN	294
764aa9a9	295	ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
067c853f	296	ctrl_cfg \|= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
9bbd2132	297
9d6b012c	298	return ctrl_cfg;
9bbd2132 DN	299	}
9bbd2132 DN	300
96b869b6 MV	301	/**
	302	* sdr_get_addr_rw() - Get the value of DRAM ADDRW register
	303	* @cfg: SDRAM controller configuration data
	304	*
	305	* Return the value of DRAM ADDRW register.
	306	*/
5af91418	307	static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
9bbd2132	308	{
9bbd2132 DN	309	/*
9bbd2132 DN	310	* SDRAM Failure When Accessing Non-Existent Memory
9bbd2132 DN	311	* Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
	312	* log2(number of chip select bits). Since there's only
	313	* 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
	314	* which is the same as "chip selects" - 1.
	315	*/
764aa9a9 MV	316	const int rows = get_errata_rows(cfg);
764aa9a9 MV	317	u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
04ae4489	318
9d6b012c	319	return dram_addrw \| (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
9bbd2132 DN	320	}
9bbd2132 DN	321
1a302a45 MV	322	/**
	323	* sdr_load_regs() - Load SDRAM controller registers
	324	* @cfg: SDRAM controller configuration data
	325	*
	326	* This function loads the register values into the SDRAM controller block.
	327	*/
5af91418	328	static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
9bbd2132	329	{
9d6b012c MV	330	const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
	331	const u32 dram_addrw = sdr_get_addr_rw(cfg);
	332
9d6b012c MV	333	debug("\nConfiguring CTRLCFG\n");
9d6b012c MV	334	writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
076470ee MV	335
	336	debug("Configuring DRAMTIMING1\n");
	337	writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
	338
	339	debug("Configuring DRAMTIMING2\n");
	340	writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
	341
	342	debug("Configuring DRAMTIMING3\n");
	343	writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
	344
	345	debug("Configuring DRAMTIMING4\n");
	346	writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
	347
	348	debug("Configuring LOWPWRTIMING\n");
	349	writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
	350
9d6b012c MV	351	debug("Configuring DRAMADDRW\n");
9d6b012c MV	352	writel(dram_addrw, &sdr_ctrl->dram_addrw);
9bbd2132 DN	353
9bbd2132 DN	354	debug("Configuring DRAMIFWIDTH\n");
dc3b91d9	355	writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
9bbd2132 DN	356
9bbd2132 DN	357	debug("Configuring DRAMDEVWIDTH\n");
dc3b91d9	358	writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
9bbd2132 DN	359
9bbd2132 DN	360	debug("Configuring LOWPWREQ\n");
dc3b91d9	361	writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
9bbd2132 DN	362
9bbd2132 DN	363	debug("Configuring DRAMINTR\n");
dc3b91d9	364	writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
9bbd2132	365
076470ee MV	366	debug("Configuring STATICCFG\n");
076470ee MV	367	writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
9bbd2132 DN	368
9bbd2132 DN	369	debug("Configuring CTRLWIDTH\n");
dc3b91d9	370	writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
9bbd2132 DN	371
9bbd2132 DN	372	debug("Configuring PORTCFG\n");
dc3b91d9	373	writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
9bbd2132	374
076470ee MV	375	debug("Configuring FIFOCFG\n");
076470ee MV	376	writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
9bbd2132 DN	377
9bbd2132 DN	378	debug("Configuring MPPRIORITY\n");
dc3b91d9	379	writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
9bbd2132	380
076470ee MV	381	debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
	382	writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
	383	writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
	384	writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
	385	writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
	386
	387	debug("Configuring MPPACING_MPPACING_0\n");
	388	writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
	389	writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
	390	writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
	391	writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
	392
	393	debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
	394	writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
	395	writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
	396	writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
9bbd2132 DN	397
9bbd2132 DN	398	debug("Configuring PHYCTRL_PHYCTRL_0\n");
dc3b91d9	399	writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
9bbd2132 DN	400
9bbd2132 DN	401	debug("Configuring CPORTWIDTH\n");
dc3b91d9	402	writel(cfg->cport_width, &sdr_ctrl->cport_width);
9bbd2132 DN	403
9bbd2132 DN	404	debug("Configuring CPORTWMAP\n");
dc3b91d9	405	writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
9bbd2132 DN	406
9bbd2132 DN	407	debug("Configuring CPORTRMAP\n");
dc3b91d9	408	writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
9bbd2132 DN	409
9bbd2132 DN	410	debug("Configuring RFIFOCMAP\n");
dc3b91d9	411	writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
9bbd2132 DN	412
9bbd2132 DN	413	debug("Configuring WFIFOCMAP\n");
dc3b91d9	414	writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
9bbd2132 DN	415
9bbd2132 DN	416	debug("Configuring CPORTRDWR\n");
dc3b91d9	417	writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
9bbd2132 DN	418
9bbd2132 DN	419	debug("Configuring DRAMODT\n");
dc3b91d9	420	writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
1a302a45 MV	421	}
1a302a45 MV	422
1e8a85f8 MV	423	/**
	424	* sdram_mmr_init_full() - Function to initialize SDRAM MMR
	425	* @sdr_phy_reg: Value of the PHY control register 0
	426	*
	427	* Initialize the SDRAM MMR.
	428	*/
99f453e9	429	int sdram_mmr_init_full(unsigned int sdr_phy_reg)
1a302a45	430	{
5af91418	431	const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
1a302a45 MV	432	const unsigned int rows =
	433	(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
	434	SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
269de4f0	435	int ret;
1a302a45 MV	436
	437	writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
	438
	439	sdr_load_regs(cfg);
9bbd2132 DN	440
9bbd2132 DN	441	/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
dc3b91d9	442	writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
9bbd2132 DN	443
	444	/* only enable if the FPGA is programmed */
	445	if (fpgamgr_test_fpga_ready()) {
269de4f0 MV	446	ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
	447	cfg->fpgaport_rst);
	448	if (ret)
	449	return ret;
9bbd2132 DN	450	}
	451
	452	/* Restore the SDR PHY Register if valid */
	453	if (sdr_phy_reg != 0xffffffff)
	454	writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
	455
dc3b91d9 MV	456	/* Final step - apply configuration changes */
	457	debug("Configuring STATICCFG\n");
	458	clrsetbits_le32(&sdr_ctrl->static_cfg,
	459	SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
9bbd2132	460	1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
9bbd2132	461
08eb9470	462	sdram_set_protection_config(0, sdram_calculate_size() - 1);
9bbd2132 DN	463
	464	sdram_dump_protection_config();
	465
269de4f0	466	return 0;
9bbd2132 DN	467	}
9bbd2132 DN	468
f97606f2 MV	469	/**
f97606f2 MV	470	* sdram_calculate_size() - Calculate SDRAM size
9bbd2132	471	*
f97606f2 MV	472	* Calculate SDRAM device size based on SDRAM controller parameters.
f97606f2 MV	473	* Size is specified in bytes.
9bbd2132 DN	474	*/
	475	unsigned long sdram_calculate_size(void)
	476	{
	477	unsigned long temp;
	478	unsigned long row, bank, col, cs, width;
bb056d9c MV	479	const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
	480	const unsigned int csbits =
	481	((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
	482	SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
	483	const unsigned int rowbits =
	484	(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
	485	SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
9bbd2132 DN	486
	487	temp = readl(&sdr_ctrl->dram_addrw);
	488	col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
	489	SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
	490
f97606f2 MV	491	/*
f97606f2 MV	492	* SDRAM Failure When Accessing Non-Existent Memory
9bbd2132 DN	493	* Use ROWBITS from Quartus/QSys to calculate SDRAM size
	494	* since the FB specifies we modify ROWBITs to work around SDRAM
	495	* controller issue.
9bbd2132 DN	496	*/
	497	row = readl(&sysmgr_regs->iswgrp_handoff[4]);
	498	if (row == 0)
bb056d9c	499	row = rowbits;
f97606f2 MV	500	/*
f97606f2 MV	501	* If the stored handoff value for rows is greater than
9bbd2132 DN	502	* the field width in the sdr.dramaddrw register then
	503	* something is very wrong. Revert to using the the #define
	504	* value handed off by the SOCEDS tool chain instead of
	505	* using a broken value.
	506	*/
	507	if (row > 31)
bb056d9c	508	row = rowbits;
9bbd2132 DN	509
	510	bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
	511	SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
	512
f97606f2 MV	513	/*
f97606f2 MV	514	* SDRAM Failure When Accessing Non-Existent Memory
9bbd2132 DN	515	* Use CSBITs from Quartus/QSys to calculate SDRAM size
	516	* since the FB specifies we modify CSBITs to work around SDRAM
	517	* controller issue.
	518	*/
bb056d9c	519	cs = csbits;
9bbd2132 DN	520
9bbd2132 DN	521	width = readl(&sdr_ctrl->dram_if_width);
f97606f2	522
9bbd2132 DN	523	/* ECC would not be calculated as its not addressible */
	524	if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
	525	width = 32;
	526	if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
	527	width = 16;
	528
	529	/* calculate the SDRAM size base on this info */
	530	temp = 1 << (row + bank + col);
	531	temp = temp * cs * (width / 8);
	532
f97606f2	533	debug("%s returns %ld\n", __func__, temp);
9bbd2132 DN	534
	535	return temp;
	536	}