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driver/ddr/fsl: Update DDR4 MR6 for Vref range
[people/ms/u-boot.git] / drivers / ddr / fsl / ctrl_regs.c
CommitLineData
58e5e9af 1/*
34e026f9 2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
58e5e9af 3 *
1a459660 4 * SPDX-License-Identifier: GPL-2.0+
58e5e9af
KG		 5 */
6
7/*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13#include <common.h>
5614e71b 14#include <fsl_ddr_sdram.h>
58e5e9af 15
5614e71b 16#include <fsl_ddr.h>
9a17eb5b 17#include <fsl_immap.h>
5614e71b 18#include <asm/io.h>
58e5e9af 19
58e5e9af
KG		 20/*
21 * Determine Rtt value.
22 *
23 * This should likely be either board or controller specific.
24 *
c360ceac 25 * Rtt(nominal) - DDR2:
58e5e9af
KG		 26 * 0 = Rtt disabled
27 * 1 = 75 ohm
28 * 2 = 150 ohm
29 * 3 = 50 ohm
c360ceac
DL		 30 * Rtt(nominal) - DDR3:
31 * 0 = Rtt disabled
32 * 1 = 60 ohm
33 * 2 = 120 ohm
34 * 3 = 40 ohm
35 * 4 = 20 ohm
36 * 5 = 30 ohm
58e5e9af
KG		 37 *
38 * FIXME: Apparently 8641 needs a value of 2
39 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
40 *
41 * FIXME: There was some effort down this line earlier:
42 *
43 * unsigned int i;
44 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
45 * if (popts->dimmslot[i].num_valid_cs
46 * && (popts->cs_local_opts[2*i].odt_rd_cfg
47 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
48 * rtt = 2;
49 * break;
50 * }
51 * }
52 */
53static inline int fsl_ddr_get_rtt(void)
54{
55 int rtt;
56
5614e71b 57#if defined(CONFIG_SYS_FSL_DDR1)
58e5e9af 58 rtt = 0;
5614e71b 59#elif defined(CONFIG_SYS_FSL_DDR2)
58e5e9af
KG		 60 rtt = 3;
61#else
c360ceac 62 rtt = 0;
58e5e9af
KG		 63#endif
64
65 return rtt;
66}
67
34e026f9
YS		 68#ifdef CONFIG_SYS_FSL_DDR4
69/*
70 * compute CAS write latency according to DDR4 spec
71 * CWL = 9 for <= 1600MT/s
72 * 10 for <= 1866MT/s
73 * 11 for <= 2133MT/s
74 * 12 for <= 2400MT/s
75 * 14 for <= 2667MT/s
76 * 16 for <= 2933MT/s
77 * 18 for higher
78 */
03e664d8
YS		 79static inline unsigned int compute_cas_write_latency(
80 const unsigned int ctrl_num)
34e026f9
YS		 81{
82 unsigned int cwl;
03e664d8 83 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
34e026f9
YS		 84 if (mclk_ps >= 1250)
85 cwl = 9;
86 else if (mclk_ps >= 1070)
87 cwl = 10;
88 else if (mclk_ps >= 935)
89 cwl = 11;
90 else if (mclk_ps >= 833)
91 cwl = 12;
92 else if (mclk_ps >= 750)
93 cwl = 14;
94 else if (mclk_ps >= 681)
95 cwl = 16;
96 else
97 cwl = 18;
98
99 return cwl;
100}
101#else
c360ceac
DL		 102/*
103 * compute the CAS write latency according to DDR3 spec
104 * CWL = 5 if tCK >= 2.5ns
105 * 6 if 2.5ns > tCK >= 1.875ns
106 * 7 if 1.875ns > tCK >= 1.5ns
107 * 8 if 1.5ns > tCK >= 1.25ns
2bba85f4
YS		 108 * 9 if 1.25ns > tCK >= 1.07ns
109 * 10 if 1.07ns > tCK >= 0.935ns
110 * 11 if 0.935ns > tCK >= 0.833ns
111 * 12 if 0.833ns > tCK >= 0.75ns
c360ceac 112 */
03e664d8
YS		 113static inline unsigned int compute_cas_write_latency(
114 const unsigned int ctrl_num)
c360ceac
DL		 115{
116 unsigned int cwl;
03e664d8 117 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
c360ceac
DL		 118
119 if (mclk_ps >= 2500)
120 cwl = 5;
121 else if (mclk_ps >= 1875)
122 cwl = 6;
123 else if (mclk_ps >= 1500)
124 cwl = 7;
125 else if (mclk_ps >= 1250)
126 cwl = 8;
2bba85f4
YS		 127 else if (mclk_ps >= 1070)
128 cwl = 9;
129 else if (mclk_ps >= 935)
130 cwl = 10;
131 else if (mclk_ps >= 833)
132 cwl = 11;
133 else if (mclk_ps >= 750)
134 cwl = 12;
135 else {
136 cwl = 12;
137 printf("Warning: CWL is out of range\n");
138 }
c360ceac
DL		 139 return cwl;
140}
34e026f9 141#endif
c360ceac 142
58e5e9af 143/* Chip Select Configuration (CSn_CONFIG) */
5800e7ab 144static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
58e5e9af
KG		 145 const memctl_options_t *popts,
146 const dimm_params_t *dimm_params)
147{
148 unsigned int cs_n_en = 0; /* Chip Select enable */
149 unsigned int intlv_en = 0; /* Memory controller interleave enable */
150 unsigned int intlv_ctl = 0; /* Interleaving control */
151 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
152 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
153 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
154 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
155 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
156 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
5800e7ab 157 int go_config = 0;
34e026f9
YS		 158#ifdef CONFIG_SYS_FSL_DDR4
159 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
160#else
161 unsigned int n_banks_per_sdram_device;
162#endif
58e5e9af
KG		 163
164 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
5800e7ab
YS		 165 switch (i) {
166 case 0:
167 if (dimm_params[dimm_number].n_ranks > 0) {
168 go_config = 1;
58e5e9af 169 /* These fields only available in CS0_CONFIG */
a4c66509
YS		 170 if (!popts->memctl_interleaving)
171 break;
172 switch (popts->memctl_interleaving_mode) {
6b1e1254 173 case FSL_DDR_256B_INTERLEAVING:
a4c66509
YS		 174 case FSL_DDR_CACHE_LINE_INTERLEAVING:
175 case FSL_DDR_PAGE_INTERLEAVING:
176 case FSL_DDR_BANK_INTERLEAVING:
177 case FSL_DDR_SUPERBANK_INTERLEAVING:
178 intlv_en = popts->memctl_interleaving;
179 intlv_ctl = popts->memctl_interleaving_mode;
180 break;
181 default:
182 break;
183 }
58e5e9af 184 }
5800e7ab
YS		 185 break;
186 case 1:
187 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
188 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
189 go_config = 1;
190 break;
191 case 2:
192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
cae7c1b5 193 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
5800e7ab
YS		 194 go_config = 1;
195 break;
196 case 3:
197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
198 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
199 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
200 go_config = 1;
201 break;
202 default:
203 break;
204 }
205 if (go_config) {
5800e7ab 206 cs_n_en = 1;
58e5e9af
KG		 207 ap_n_en = popts->cs_local_opts[i].auto_precharge;
208 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
209 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
34e026f9
YS		 210#ifdef CONFIG_SYS_FSL_DDR4
211 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
212 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
213#else
58e5e9af 214 n_banks_per_sdram_device
5800e7ab 215 = dimm_params[dimm_number].n_banks_per_sdram_device;
58e5e9af 216 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
34e026f9 217#endif
5800e7ab
YS		 218 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
219 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
58e5e9af 220 }
58e5e9af
KG		 221 ddr->cs[i].config = (0
222 | ((cs_n_en & 0x1) << 31)
223 | ((intlv_en & 0x3) << 29)
dbbbb3ab 224 | ((intlv_ctl & 0xf) << 24)
58e5e9af
KG		 225 | ((ap_n_en & 0x1) << 23)
226
227 /* XXX: some implementation only have 1 bit starting at left */
228 | ((odt_rd_cfg & 0x7) << 20)
229
230 /* XXX: Some implementation only have 1 bit starting at left */
231 | ((odt_wr_cfg & 0x7) << 16)
232
233 | ((ba_bits_cs_n & 0x3) << 14)
234 | ((row_bits_cs_n & 0x7) << 8)
34e026f9
YS		 235#ifdef CONFIG_SYS_FSL_DDR4
236 | ((bg_bits_cs_n & 0x3) << 4)
237#endif
58e5e9af
KG		 238 | ((col_bits_cs_n & 0x7) << 0)
239 );
1f293b41 240 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
58e5e9af
KG		 241}
242
243/* Chip Select Configuration 2 (CSn_CONFIG_2) */
244/* FIXME: 8572 */
245static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
246{
247 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
248
249 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
1f293b41 250 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
58e5e9af
KG		 251}
252
253/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
254
5614e71b 255#if !defined(CONFIG_SYS_FSL_DDR1)
84baed2a
YS		 256/*
257 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
258 * Return 1 if other two slots configuration. Return 0 if single slot.
259 */
123922b1
YS		 260static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
261{
262#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
263 if (dimm_params[0].n_ranks == 4)
84baed2a 264 return 2;
123922b1
YS		 265#endif
266
267#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
268 if ((dimm_params[0].n_ranks == 2) &&
269 (dimm_params[1].n_ranks == 2))
84baed2a 270 return 2;
123922b1
YS		 271
272#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
273 if (dimm_params[0].n_ranks == 4)
84baed2a 274 return 2;
123922b1 275#endif
84baed2a
YS		 276
277 if ((dimm_params[0].n_ranks != 0) &&
278 (dimm_params[2].n_ranks != 0))
279 return 1;
123922b1
YS		 280#endif
281 return 0;
282}
283
58e5e9af
KG		 284/*
285 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
286 *
287 * Avoid writing for DDR I. The new PQ38 DDR controller
288 * dreams up non-zero default values to be backwards compatible.
289 */
03e664d8
YS		 290static void set_timing_cfg_0(const unsigned int ctrl_num,
291 fsl_ddr_cfg_regs_t *ddr,
123922b1
YS		 292 const memctl_options_t *popts,
293 const dimm_params_t *dimm_params)
58e5e9af
KG		 294{
295 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
296 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
297 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
298 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
299 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
300
301 /* Active powerdown exit timing (tXARD and tXARDS). */
302 unsigned char act_pd_exit_mclk;
303 /* Precharge powerdown exit timing (tXP). */
304 unsigned char pre_pd_exit_mclk;
5fb8a8a7 305 /* ODT powerdown exit timing (tAXPD). */
34e026f9 306 unsigned char taxpd_mclk = 0;
58e5e9af
KG		 307 /* Mode register set cycle time (tMRD). */
308 unsigned char tmrd_mclk;
bb578322 309#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
03e664d8 310 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
bb578322 311#endif
58e5e9af 312
34e026f9
YS		 313#ifdef CONFIG_SYS_FSL_DDR4
314 /* tXP=max(4nCK, 6ns) */
b4141195 315 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
66869f95
YS		 316 unsigned int data_rate = get_ddr_freq(ctrl_num);
317
318 /* for faster clock, need more time for data setup */
319 trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
34e026f9 320 twrt_mclk = 1;
03e664d8 321 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
34e026f9
YS		 322 pre_pd_exit_mclk = act_pd_exit_mclk;
323 /*
324 * MRS_CYC = max(tMRD, tMOD)
325 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
326 */
03e664d8 327 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
34e026f9 328#elif defined(CONFIG_SYS_FSL_DDR3)
03e664d8 329 unsigned int data_rate = get_ddr_freq(ctrl_num);
bb578322 330 int txp;
938bbb60 331 unsigned int ip_rev;
84baed2a 332 int odt_overlap;
c360ceac
DL		 333 /*
334 * (tXARD and tXARDS). Empirical?
335 * The DDR3 spec has not tXARD,
336 * we use the tXP instead of it.
bb578322
YS		 337 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
338 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
c360ceac 339 * spec has not the tAXPD, we use
5fb8a8a7 340 * tAXPD=1, need design to confirm.
c360ceac 341 */
b4141195 342 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
bb578322 343
66869f95 344 ip_rev = fsl_ddr_get_version(ctrl_num);
938bbb60
YS		 345 if (ip_rev >= 0x40700) {
346 /*
347 * MRS_CYC = max(tMRD, tMOD)
348 * tMRD = 4nCK (8nCK for RDIMM)
349 * tMOD = max(12nCK, 15ns)
350 */
03e664d8
YS		 351 tmrd_mclk = max((unsigned int)12,
352 picos_to_mclk(ctrl_num, 15000));
938bbb60
YS		 353 } else {
354 /*
355 * MRS_CYC = tMRD
356 * tMRD = 4nCK (8nCK for RDIMM)
357 */
358 if (popts->registered_dimm_en)
359 tmrd_mclk = 8;
360 else
361 tmrd_mclk = 4;
362 }
363
99bac479 364 /* set the turnaround time */
123922b1
YS		 365
366 /*
84baed2a 367 * for single quad-rank DIMM and two-slot DIMMs
123922b1
YS		 368 * to avoid ODT overlap
369 */
84baed2a
YS		 370 odt_overlap = avoid_odt_overlap(dimm_params);
371 switch (odt_overlap) {
372 case 2:
123922b1
YS		 373 twwt_mclk = 2;
374 trrt_mclk = 1;
84baed2a
YS		 375 break;
376 case 1:
377 twwt_mclk = 1;
378 trrt_mclk = 0;
379 break;
380 default:
381 break;
123922b1 382 }
84baed2a 383
123922b1
YS		 384 /* for faster clock, need more time for data setup */
385 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
386
856e4b0d
YS		 387 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
388 twrt_mclk = 1;
e1fd16b6
YS		 389
390 if (popts->dynamic_power == 0) { /* powerdown is not used */
391 act_pd_exit_mclk = 1;
392 pre_pd_exit_mclk = 1;
393 taxpd_mclk = 1;
394 } else {
395 /* act_pd_exit_mclk = tXARD, see above */
03e664d8 396 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
e1fd16b6
YS		 397 /* Mode register MR0[A12] is '1' - fast exit */
398 pre_pd_exit_mclk = act_pd_exit_mclk;
399 taxpd_mclk = 1;
400 }
5614e71b 401#else /* CONFIG_SYS_FSL_DDR2 */
c360ceac
DL		 402 /*
403 * (tXARD and tXARDS). Empirical?
404 * tXARD = 2 for DDR2
405 * tXP=2
406 * tAXPD=8
407 */
408 act_pd_exit_mclk = 2;
409 pre_pd_exit_mclk = 2;
410 taxpd_mclk = 8;
58e5e9af 411 tmrd_mclk = 2;
c360ceac 412#endif
58e5e9af 413
23f9670f
YS		 414 if (popts->trwt_override)
415 trwt_mclk = popts->trwt;
416
58e5e9af
KG		 417 ddr->timing_cfg_0 = (0
418 | ((trwt_mclk & 0x3) << 30) /* RWT */
419 | ((twrt_mclk & 0x3) << 28) /* WRT */
420 | ((trrt_mclk & 0x3) << 26) /* RRT */
421 | ((twwt_mclk & 0x3) << 24) /* WWT */
d4263b8a 422 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
22ff3d01 423 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
58e5e9af 424 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
d4263b8a 425 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
58e5e9af
KG		 426 );
427 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
428}
84baed2a 429#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
58e5e9af
KG		 430
431/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
03e664d8
YS		 432static void set_timing_cfg_3(const unsigned int ctrl_num,
433 fsl_ddr_cfg_regs_t *ddr,
434 const memctl_options_t *popts,
435 const common_timing_params_t *common_dimm,
436 unsigned int cas_latency,
437 unsigned int additive_latency)
58e5e9af 438{
45064adc
YS		 439 /* Extended precharge to activate interval (tRP) */
440 unsigned int ext_pretoact = 0;
58e5e9af
KG		 441 /* Extended Activate to precharge interval (tRAS) */
442 unsigned int ext_acttopre = 0;
45064adc
YS		 443 /* Extended activate to read/write interval (tRCD) */
444 unsigned int ext_acttorw = 0;
445 /* Extended refresh recovery time (tRFC) */
446 unsigned int ext_refrec;
447 /* Extended MCAS latency from READ cmd */
448 unsigned int ext_caslat = 0;
d4263b8a
YS		 449 /* Extended additive latency */
450 unsigned int ext_add_lat = 0;
45064adc
YS		 451 /* Extended last data to precharge interval (tWR) */
452 unsigned int ext_wrrec = 0;
453 /* Control Adjust */
454 unsigned int cntl_adj = 0;
455
03e664d8
YS		 456 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
457 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
458 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
45064adc 459 ext_caslat = (2 * cas_latency - 1) >> 4;
d4263b8a 460 ext_add_lat = additive_latency >> 4;
34e026f9 461#ifdef CONFIG_SYS_FSL_DDR4
03e664d8 462 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
34e026f9 463#else
03e664d8 464 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
45064adc 465 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
34e026f9 466#endif
03e664d8 467 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
0dd38a35 468 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
c360ceac 469
58e5e9af 470 ddr->timing_cfg_3 = (0
45064adc 471 | ((ext_pretoact & 0x1) << 28)
c45f5c08 472 | ((ext_acttopre & 0x3) << 24)
45064adc
YS		 473 | ((ext_acttorw & 0x1) << 22)
474 | ((ext_refrec & 0x1F) << 16)
475 | ((ext_caslat & 0x3) << 12)
d4263b8a 476 | ((ext_add_lat & 0x1) << 10)
45064adc 477 | ((ext_wrrec & 0x1) << 8)
58e5e9af
KG		 478 | ((cntl_adj & 0x7) << 0)
479 );
1f293b41 480 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
58e5e9af
KG		 481}
482
483/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
03e664d8
YS		 484static void set_timing_cfg_1(const unsigned int ctrl_num,
485 fsl_ddr_cfg_regs_t *ddr,
486 const memctl_options_t *popts,
487 const common_timing_params_t *common_dimm,
488 unsigned int cas_latency)
58e5e9af
KG		 489{
490 /* Precharge-to-activate interval (tRP) */
491 unsigned char pretoact_mclk;
492 /* Activate to precharge interval (tRAS) */
493 unsigned char acttopre_mclk;
494 /* Activate to read/write interval (tRCD) */
495 unsigned char acttorw_mclk;
496 /* CASLAT */
497 unsigned char caslat_ctrl;
498 /* Refresh recovery time (tRFC) ; trfc_low */
499 unsigned char refrec_ctrl;
500 /* Last data to precharge minimum interval (tWR) */
501 unsigned char wrrec_mclk;
502 /* Activate-to-activate interval (tRRD) */
503 unsigned char acttoact_mclk;
504 /* Last write data pair to read command issue interval (tWTR) */
505 unsigned char wrtord_mclk;
34e026f9
YS		 506#ifdef CONFIG_SYS_FSL_DDR4
507 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
508 static const u8 wrrec_table[] = {
509 10, 10, 10, 10, 10,
510 10, 10, 10, 10, 10,
511 12, 12, 14, 14, 16,
512 16, 18, 18, 20, 20,
513 24, 24, 24, 24};
514#else
f5b6fb7c
YS		 515 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
516 static const u8 wrrec_table[] = {
517 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
34e026f9 518#endif
58e5e9af 519
03e664d8
YS		 520 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
521 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
522 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
58e5e9af
KG		 523
524 /*
525 * Translate CAS Latency to a DDR controller field value:
526 *
527 * CAS Lat DDR I DDR II Ctrl
528 * Clocks SPD Bit SPD Bit Value
529 * ------- ------- ------- -----
530 * 1.0 0 0001
531 * 1.5 1 0010
532 * 2.0 2 2 0011
533 * 2.5 3 0100
534 * 3.0 4 3 0101
535 * 3.5 5 0110
536 * 4.0 4 0111
537 * 4.5 1000
538 * 5.0 5 1001
539 */
5614e71b 540#if defined(CONFIG_SYS_FSL_DDR1)
58e5e9af 541 caslat_ctrl = (cas_latency + 1) & 0x07;
5614e71b 542#elif defined(CONFIG_SYS_FSL_DDR2)
58e5e9af
KG		 543 caslat_ctrl = 2 * cas_latency - 1;
544#else
c360ceac
DL		 545 /*
546 * if the CAS latency more than 8 cycle,
547 * we need set extend bit for it at
548 * TIMING_CFG_3[EXT_CASLAT]
549 */
66869f95 550 if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
34e026f9
YS		 551 caslat_ctrl = 2 * cas_latency - 1;
552 else
553 caslat_ctrl = (cas_latency - 1) << 1;
58e5e9af
KG		 554#endif
555
34e026f9 556#ifdef CONFIG_SYS_FSL_DDR4
03e664d8
YS		 557 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
558 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
559 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
560 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
349689b8
YS		 561 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
562 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
34e026f9
YS		 563 else
564 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
565#else
03e664d8
YS		 566 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
567 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
568 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
569 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
349689b8
YS		 570 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
571 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
45064adc
YS		 572 else
573 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
34e026f9 574#endif
0dd38a35 575 if (popts->otf_burst_chop_en)
c360ceac
DL		 576 wrrec_mclk += 2;
577
c360ceac
DL		 578 /*
579 * JEDEC has min requirement for tRRD
580 */
5614e71b 581#if defined(CONFIG_SYS_FSL_DDR3)
c360ceac
DL		 582 if (acttoact_mclk < 4)
583 acttoact_mclk = 4;
584#endif
c360ceac
DL		 585 /*
586 * JEDEC has some min requirements for tWTR
587 */
5614e71b 588#if defined(CONFIG_SYS_FSL_DDR2)
c360ceac
DL		 589 if (wrtord_mclk < 2)
590 wrtord_mclk = 2;
5614e71b 591#elif defined(CONFIG_SYS_FSL_DDR3)
c360ceac
DL		 592 if (wrtord_mclk < 4)
593 wrtord_mclk = 4;
594#endif
0dd38a35 595 if (popts->otf_burst_chop_en)
c360ceac 596 wrtord_mclk += 2;
58e5e9af
KG		 597
598 ddr->timing_cfg_1 = (0
80ee3ce6 599 | ((pretoact_mclk & 0x0F) << 28)
58e5e9af 600 | ((acttopre_mclk & 0x0F) << 24)
80ee3ce6 601 | ((acttorw_mclk & 0xF) << 20)
58e5e9af
KG		 602 | ((caslat_ctrl & 0xF) << 16)
603 | ((refrec_ctrl & 0xF) << 12)
80ee3ce6 604 | ((wrrec_mclk & 0x0F) << 8)
57495e4e
YS		 605 | ((acttoact_mclk & 0x0F) << 4)
606 | ((wrtord_mclk & 0x0F) << 0)
58e5e9af 607 );
1f293b41 608 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
58e5e9af
KG		 609}
610
611/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
03e664d8
YS		 612static void set_timing_cfg_2(const unsigned int ctrl_num,
613 fsl_ddr_cfg_regs_t *ddr,
614 const memctl_options_t *popts,
615 const common_timing_params_t *common_dimm,
616 unsigned int cas_latency,
617 unsigned int additive_latency)
58e5e9af
KG		 618{
619 /* Additive latency */
620 unsigned char add_lat_mclk;
621 /* CAS-to-preamble override */
622 unsigned short cpo;
623 /* Write latency */
624 unsigned char wr_lat;
625 /* Read to precharge (tRTP) */
626 unsigned char rd_to_pre;
627 /* Write command to write data strobe timing adjustment */
628 unsigned char wr_data_delay;
629 /* Minimum CKE pulse width (tCKE) */
630 unsigned char cke_pls;
631 /* Window for four activates (tFAW) */
632 unsigned short four_act;
bb578322 633#ifdef CONFIG_SYS_FSL_DDR3
03e664d8 634 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
bb578322 635#endif
58e5e9af
KG		 636
637 /* FIXME add check that this must be less than acttorw_mclk */
638 add_lat_mclk = additive_latency;
639 cpo = popts->cpo_override;
640
5614e71b 641#if defined(CONFIG_SYS_FSL_DDR1)
58e5e9af
KG		 642 /*
643 * This is a lie. It should really be 1, but if it is
644 * set to 1, bits overlap into the old controller's
645 * otherwise unused ACSM field. If we leave it 0, then
646 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
647 */
648 wr_lat = 0;
5614e71b 649#elif defined(CONFIG_SYS_FSL_DDR2)
6a819783 650 wr_lat = cas_latency - 1;
58e5e9af 651#else
03e664d8 652 wr_lat = compute_cas_write_latency(ctrl_num);
58e5e9af
KG		 653#endif
654
34e026f9 655#ifdef CONFIG_SYS_FSL_DDR4
03e664d8 656 rd_to_pre = picos_to_mclk(ctrl_num, 7500);
34e026f9 657#else
03e664d8 658 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
34e026f9 659#endif
c360ceac
DL		 660 /*
661 * JEDEC has some min requirements for tRTP
662 */
5614e71b 663#if defined(CONFIG_SYS_FSL_DDR2)
c360ceac
DL		 664 if (rd_to_pre < 2)
665 rd_to_pre = 2;
34e026f9 666#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
c360ceac
DL		 667 if (rd_to_pre < 4)
668 rd_to_pre = 4;
6a819783 669#endif
0dd38a35 670 if (popts->otf_burst_chop_en)
c360ceac
DL		 671 rd_to_pre += 2; /* according to UM */
672
58e5e9af 673 wr_data_delay = popts->write_data_delay;
34e026f9
YS		 674#ifdef CONFIG_SYS_FSL_DDR4
675 cpo = 0;
03e664d8 676 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
bb578322
YS		 677#elif defined(CONFIG_SYS_FSL_DDR3)
678 /*
679 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
680 * max(3nCK, 5.625ns) for DDR3-1066, 1333
681 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
682 */
03e664d8
YS		 683 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
684 (mclk_ps > 1245 ? 5625 : 5000)));
34e026f9 685#else
bb578322 686 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
34e026f9 687#endif
03e664d8
YS		 688 four_act = picos_to_mclk(ctrl_num,
689 popts->tfaw_window_four_activates_ps);
58e5e9af
KG		 690
691 ddr->timing_cfg_2 = (0
22ff3d01 692 | ((add_lat_mclk & 0xf) << 28)
58e5e9af 693 | ((cpo & 0x1f) << 23)
22ff3d01 694 | ((wr_lat & 0xf) << 19)
34e026f9 695 | ((wr_lat & 0x10) << 14)
c360ceac
DL		 696 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
697 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
58e5e9af 698 | ((cke_pls & 0x7) << 6)
22ff3d01 699 | ((four_act & 0x3f) << 0)
58e5e9af 700 );
1f293b41 701 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
58e5e9af
KG		 702}
703
9490ff48
YS		 704/* DDR SDRAM Register Control Word */
705static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
e1fd16b6 706 const memctl_options_t *popts,
9490ff48
YS		 707 const common_timing_params_t *common_dimm)
708{
0dd38a35
PJ		 709 if (common_dimm->all_dimms_registered &&
710 !common_dimm->all_dimms_unbuffered) {
e1fd16b6
YS		 711 if (popts->rcw_override) {
712 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
713 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
714 } else {
715 ddr->ddr_sdram_rcw_1 =
716 common_dimm->rcw[0] << 28 | \
717 common_dimm->rcw[1] << 24 | \
718 common_dimm->rcw[2] << 20 | \
719 common_dimm->rcw[3] << 16 | \
720 common_dimm->rcw[4] << 12 | \
721 common_dimm->rcw[5] << 8 | \
722 common_dimm->rcw[6] << 4 | \
723 common_dimm->rcw[7];
724 ddr->ddr_sdram_rcw_2 =
725 common_dimm->rcw[8] << 28 | \
726 common_dimm->rcw[9] << 24 | \
727 common_dimm->rcw[10] << 20 | \
728 common_dimm->rcw[11] << 16 | \
729 common_dimm->rcw[12] << 12 | \
730 common_dimm->rcw[13] << 8 | \
731 common_dimm->rcw[14] << 4 | \
732 common_dimm->rcw[15];
733 }
9490ff48
YS		 734 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
735 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
736 }
737}
738
58e5e9af
KG		 739/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
740static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
741 const memctl_options_t *popts,
742 const common_timing_params_t *common_dimm)
743{
744 unsigned int mem_en; /* DDR SDRAM interface logic enable */
745 unsigned int sren; /* Self refresh enable (during sleep) */
746 unsigned int ecc_en; /* ECC enable. */
747 unsigned int rd_en; /* Registered DIMM enable */
748 unsigned int sdram_type; /* Type of SDRAM */
749 unsigned int dyn_pwr; /* Dynamic power management mode */
750 unsigned int dbw; /* DRAM dta bus width */
22ff3d01 751 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
58e5e9af 752 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
0dd38a35
PJ		 753 unsigned int threet_en; /* Enable 3T timing */
754 unsigned int twot_en; /* Enable 2T timing */
58e5e9af
KG		 755 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
756 unsigned int x32_en = 0; /* x32 enable */
757 unsigned int pchb8 = 0; /* precharge bit 8 enable */
758 unsigned int hse; /* Global half strength override */
d28cb671 759 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
58e5e9af
KG		 760 unsigned int mem_halt = 0; /* memory controller halt */
761 unsigned int bi = 0; /* Bypass initialization */
762
763 mem_en = 1;
764 sren = popts->self_refresh_in_sleep;
0dd38a35 765 if (common_dimm->all_dimms_ecc_capable) {
58e5e9af 766 /* Allow setting of ECC only if all DIMMs are ECC. */
0dd38a35 767 ecc_en = popts->ecc_mode;
58e5e9af
KG		 768 } else {
769 ecc_en = 0;
770 }
771
0dd38a35
PJ		 772 if (common_dimm->all_dimms_registered &&
773 !common_dimm->all_dimms_unbuffered) {
e1fd16b6 774 rd_en = 1;
0dd38a35 775 twot_en = 0;
e1fd16b6
YS		 776 } else {
777 rd_en = 0;
0dd38a35 778 twot_en = popts->twot_en;
e1fd16b6 779 }
58e5e9af
KG		 780
781 sdram_type = CONFIG_FSL_SDRAM_TYPE;
782
783 dyn_pwr = popts->dynamic_power;
784 dbw = popts->data_bus_width;
c360ceac
DL		 785 /* 8-beat burst enable DDR-III case
786 * we must clear it when use the on-the-fly mode,
787 * must set it when use the 32-bits bus mode.
788 */
34e026f9
YS		 789 if ((sdram_type == SDRAM_TYPE_DDR3) ||
790 (sdram_type == SDRAM_TYPE_DDR4)) {
c360ceac
DL		 791 if (popts->burst_length == DDR_BL8)
792 eight_be = 1;
793 if (popts->burst_length == DDR_OTF)
794 eight_be = 0;
795 if (dbw == 0x1)
796 eight_be = 1;
797 }
798
0dd38a35 799 threet_en = popts->threet_en;
58e5e9af
KG		 800 ba_intlv_ctl = popts->ba_intlv_ctl;
801 hse = popts->half_strength_driver_enable;
802
d28cb671
YS		 803 /* set when ddr bus width < 64 */
804 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
805
58e5e9af
KG		 806 ddr->ddr_sdram_cfg = (0
807 | ((mem_en & 0x1) << 31)
808 | ((sren & 0x1) << 30)
809 | ((ecc_en & 0x1) << 29)
810 | ((rd_en & 0x1) << 28)
811 | ((sdram_type & 0x7) << 24)
812 | ((dyn_pwr & 0x1) << 21)
813 | ((dbw & 0x3) << 19)
814 | ((eight_be & 0x1) << 18)
815 | ((ncap & 0x1) << 17)
0dd38a35
PJ		 816 | ((threet_en & 0x1) << 16)
817 | ((twot_en & 0x1) << 15)
58e5e9af
KG		 818 | ((ba_intlv_ctl & 0x7F) << 8)
819 | ((x32_en & 0x1) << 5)
820 | ((pchb8 & 0x1) << 4)
821 | ((hse & 0x1) << 3)
d28cb671 822 | ((acc_ecc_en & 0x1) << 2)
58e5e9af
KG		 823 | ((mem_halt & 0x1) << 1)
824 | ((bi & 0x1) << 0)
825 );
1f293b41 826 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
58e5e9af
KG		 827}
828
829/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
03e664d8
YS		 830static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
831 fsl_ddr_cfg_regs_t *ddr,
e1fd16b6
YS		 832 const memctl_options_t *popts,
833 const unsigned int unq_mrs_en)
58e5e9af
KG		 834{
835 unsigned int frc_sr = 0; /* Force self refresh */
836 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
cae7c1b5 837 unsigned int odt_cfg = 0; /* ODT configuration */
58e5e9af 838 unsigned int num_pr; /* Number of posted refreshes */
57495e4e 839 unsigned int slow = 0; /* DDR will be run less than 1250 */
b61e0615 840 unsigned int x4_en = 0; /* x4 DRAM enable */
58e5e9af
KG		 841 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
842 unsigned int ap_en; /* Address Parity Enable */
843 unsigned int d_init; /* DRAM data initialization */
844 unsigned int rcw_en = 0; /* Register Control Word Enable */
845 unsigned int md_en = 0; /* Mirrored DIMM Enable */
5800e7ab 846 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
cae7c1b5 847 int i;
34e026f9
YS		 848#ifndef CONFIG_SYS_FSL_DDR4
849 unsigned int dll_rst_dis = 1; /* DLL reset disable */
850 unsigned int dqs_cfg; /* DQS configuration */
58e5e9af 851
0dd38a35 852 dqs_cfg = popts->dqs_config;
34e026f9 853#endif
cae7c1b5
YS		 854 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
855 if (popts->cs_local_opts[i].odt_rd_cfg
856 || popts->cs_local_opts[i].odt_wr_cfg) {
857 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
858 break;
859 }
58e5e9af 860 }
e368c206 861 sr_ie = popts->self_refresh_interrupt_en;
58e5e9af
KG		 862 num_pr = 1; /* Make this configurable */
863
864 /*
865 * 8572 manual says
866 * {TIMING_CFG_1[PRETOACT]
867 * + [DDR_SDRAM_CFG_2[NUM_PR]
868 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
869 * << DDR_SDRAM_INTERVAL[REFINT]
870 */
34e026f9 871#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
0dd38a35 872 obc_cfg = popts->otf_burst_chop_en;
c360ceac
DL		 873#else
874 obc_cfg = 0;
875#endif
58e5e9af 876
57495e4e 877#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
03e664d8 878 slow = get_ddr_freq(ctrl_num) < 1249000000;
57495e4e
YS		 879#endif
880
e1fd16b6
YS		 881 if (popts->registered_dimm_en) {
882 rcw_en = 1;
883 ap_en = popts->ap_en;
884 } else {
e1fd16b6
YS		 885 ap_en = 0;
886 }
58e5e9af 887
b61e0615
YS		 888 x4_en = popts->x4_en ? 1 : 0;
889
58e5e9af
KG		 890#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
891 /* Use the DDR controller to auto initialize memory. */
0dd38a35 892 d_init = popts->ecc_init_using_memctl;
58e5e9af
KG		 893 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
894 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
895#else
896 /* Memory will be initialized via DMA, or not at all. */
897 d_init = 0;
898#endif
899
34e026f9 900#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
c360ceac
DL		 901 md_en = popts->mirrored_dimm;
902#endif
5800e7ab 903 qd_en = popts->quad_rank_present ? 1 : 0;
58e5e9af
KG		 904 ddr->ddr_sdram_cfg_2 = (0
905 | ((frc_sr & 0x1) << 31)
906 | ((sr_ie & 0x1) << 30)
34e026f9 907#ifndef CONFIG_SYS_FSL_DDR4
58e5e9af
KG		 908 | ((dll_rst_dis & 0x1) << 29)
909 | ((dqs_cfg & 0x3) << 26)
34e026f9 910#endif
58e5e9af
KG		 911 | ((odt_cfg & 0x3) << 21)
912 | ((num_pr & 0xf) << 12)
57495e4e 913 | ((slow & 1) << 11)
b61e0615 914 | (x4_en << 10)
5800e7ab 915 | (qd_en << 9)
e1fd16b6 916 | (unq_mrs_en << 8)
58e5e9af
KG		 917 | ((obc_cfg & 0x1) << 6)
918 | ((ap_en & 0x1) << 5)
919 | ((d_init & 0x1) << 4)
920 | ((rcw_en & 0x1) << 2)
921 | ((md_en & 0x1) << 0)
922 );
1f293b41 923 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
58e5e9af
KG		 924}
925
34e026f9 926#ifdef CONFIG_SYS_FSL_DDR4
58e5e9af 927/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
03e664d8
YS		 928static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
929 fsl_ddr_cfg_regs_t *ddr,
e1fd16b6 930 const memctl_options_t *popts,
7e157b0a 931 const common_timing_params_t *common_dimm,
e1fd16b6 932 const unsigned int unq_mrs_en)
58e5e9af
KG		 933{
934 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
935 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
34e026f9
YS		 936 int i;
937 unsigned int wr_crc = 0; /* Disable */
938 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
939 unsigned int srt = 0; /* self-refresh temerature, normal range */
03e664d8 940 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
34e026f9
YS		 941 unsigned int mpr = 0; /* serial */
942 unsigned int wc_lat;
03e664d8 943 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
58e5e9af 944
34e026f9
YS		 945 if (popts->rtt_override)
946 rtt_wr = popts->rtt_wr_override_value;
947 else
948 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
949
950 if (common_dimm->extended_op_srt)
951 srt = common_dimm->extended_op_srt;
952
953 esdmode2 = (0
954 | ((wr_crc & 0x1) << 12)
955 | ((rtt_wr & 0x3) << 9)
956 | ((srt & 0x3) << 6)
957 | ((cwl & 0x7) << 3));
958
959 if (mclk_ps >= 1250)
960 wc_lat = 0;
961 else if (mclk_ps >= 833)
962 wc_lat = 1;
963 else
964 wc_lat = 2;
965
966 esdmode3 = (0
967 | ((mpr & 0x3) << 11)
968 | ((wc_lat & 0x3) << 9));
969
970 ddr->ddr_sdram_mode_2 = (0
971 | ((esdmode2 & 0xFFFF) << 16)
972 | ((esdmode3 & 0xFFFF) << 0)
973 );
974 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
975
976 if (unq_mrs_en) { /* unique mode registers are supported */
977 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
978 if (popts->rtt_override)
979 rtt_wr = popts->rtt_wr_override_value;
980 else
981 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
982
983 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
984 esdmode2 |= (rtt_wr & 0x3) << 9;
985 switch (i) {
986 case 1:
987 ddr->ddr_sdram_mode_4 = (0
988 | ((esdmode2 & 0xFFFF) << 16)
989 | ((esdmode3 & 0xFFFF) << 0)
990 );
991 break;
992 case 2:
993 ddr->ddr_sdram_mode_6 = (0
994 | ((esdmode2 & 0xFFFF) << 16)
995 | ((esdmode3 & 0xFFFF) << 0)
996 );
997 break;
998 case 3:
999 ddr->ddr_sdram_mode_8 = (0
1000 | ((esdmode2 & 0xFFFF) << 16)
1001 | ((esdmode3 & 0xFFFF) << 0)
1002 );
1003 break;
1004 }
1005 }
1006 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1007 ddr->ddr_sdram_mode_4);
1008 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1009 ddr->ddr_sdram_mode_6);
1010 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1011 ddr->ddr_sdram_mode_8);
1012 }
1013}
1014#elif defined(CONFIG_SYS_FSL_DDR3)
1015/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
03e664d8
YS		 1016static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1017 fsl_ddr_cfg_regs_t *ddr,
34e026f9
YS		 1018 const memctl_options_t *popts,
1019 const common_timing_params_t *common_dimm,
1020 const unsigned int unq_mrs_en)
1021{
1022 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1023 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
92966835 1024 int i;
1aa3d08a 1025 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
c360ceac
DL		 1026 unsigned int srt = 0; /* self-refresh temerature, normal range */
1027 unsigned int asr = 0; /* auto self-refresh disable */
03e664d8 1028 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
c360ceac
DL		 1029 unsigned int pasr = 0; /* partial array self refresh disable */
1030
1aa3d08a
DL		 1031 if (popts->rtt_override)
1032 rtt_wr = popts->rtt_wr_override_value;
e1fd16b6
YS		 1033 else
1034 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
7e157b0a
VL		 1035
1036 if (common_dimm->extended_op_srt)
1037 srt = common_dimm->extended_op_srt;
1038
c360ceac
DL		 1039 esdmode2 = (0
1040 | ((rtt_wr & 0x3) << 9)
1041 | ((srt & 0x1) << 7)
1042 | ((asr & 0x1) << 6)
1043 | ((cwl & 0x7) << 3)
1044 | ((pasr & 0x7) << 0));
58e5e9af
KG		 1045 ddr->ddr_sdram_mode_2 = (0
1046 | ((esdmode2 & 0xFFFF) << 16)
1047 | ((esdmode3 & 0xFFFF) << 0)
1048 );
1f293b41 1049 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
e1fd16b6 1050
e1fd16b6 1051 if (unq_mrs_en) { /* unique mode registers are supported */
dea7f887 1052 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
e1fd16b6
YS		 1053 if (popts->rtt_override)
1054 rtt_wr = popts->rtt_wr_override_value;
1055 else
1056 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1057
1058 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1059 esdmode2 |= (rtt_wr & 0x3) << 9;
1060 switch (i) {
1061 case 1:
1062 ddr->ddr_sdram_mode_4 = (0
1063 | ((esdmode2 & 0xFFFF) << 16)
1064 | ((esdmode3 & 0xFFFF) << 0)
1065 );
1066 break;
1067 case 2:
1068 ddr->ddr_sdram_mode_6 = (0
1069 | ((esdmode2 & 0xFFFF) << 16)
1070 | ((esdmode3 & 0xFFFF) << 0)
1071 );
1072 break;
1073 case 3:
1074 ddr->ddr_sdram_mode_8 = (0
1075 | ((esdmode2 & 0xFFFF) << 16)
1076 | ((esdmode3 & 0xFFFF) << 0)
1077 );
1078 break;
1079 }
1080 }
1081 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1082 ddr->ddr_sdram_mode_4);
1083 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1084 ddr->ddr_sdram_mode_6);
1085 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1086 ddr->ddr_sdram_mode_8);
1087 }
34e026f9
YS		 1088}
1089
1090#else /* for DDR2 and DDR1 */
1091/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
03e664d8
YS		 1092static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1093 fsl_ddr_cfg_regs_t *ddr,
34e026f9
YS		 1094 const memctl_options_t *popts,
1095 const common_timing_params_t *common_dimm,
1096 const unsigned int unq_mrs_en)
1097{
1098 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1099 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1100
1101 ddr->ddr_sdram_mode_2 = (0
1102 | ((esdmode2 & 0xFFFF) << 16)
1103 | ((esdmode3 & 0xFFFF) << 0)
1104 );
1105 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1106}
e1fd16b6 1107#endif
34e026f9
YS		 1108
1109#ifdef CONFIG_SYS_FSL_DDR4
1110/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1111static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1112 const memctl_options_t *popts,
1113 const common_timing_params_t *common_dimm,
1114 const unsigned int unq_mrs_en)
1115{
1116 int i;
1117 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1118 unsigned short esdmode5; /* Extended SDRAM mode 5 */
6b95be22 1119 int rtt_park = 0;
34e026f9 1120
6b95be22
YS		 1121 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1122 esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */
1123 rtt_park = 1;
1124 } else {
1125 esdmode5 = 0x00000400; /* Data mask enabled */
1126 }
34e026f9
YS		 1127
1128 ddr->ddr_sdram_mode_9 = (0
1129 | ((esdmode4 & 0xffff) << 16)
1130 | ((esdmode5 & 0xffff) << 0)
1131 );
66869f95
YS		 1132
1133 /* only mode_9 use 0x500, others use 0x400 */
66869f95 1134
34e026f9
YS		 1135 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1136 if (unq_mrs_en) { /* unique mode registers are supported */
1137 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
6b95be22
YS		 1138 if (!rtt_park &&
1139 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1140 esdmode5 |= 0x00000500; /* RTT_PARK */
1141 rtt_park = 1;
1142 } else {
1143 esdmode5 = 0x00000400;
1144 }
34e026f9
YS		 1145 switch (i) {
1146 case 1:
1147 ddr->ddr_sdram_mode_11 = (0
1148 | ((esdmode4 & 0xFFFF) << 16)
1149 | ((esdmode5 & 0xFFFF) << 0)
1150 );
1151 break;
1152 case 2:
1153 ddr->ddr_sdram_mode_13 = (0
1154 | ((esdmode4 & 0xFFFF) << 16)
1155 | ((esdmode5 & 0xFFFF) << 0)
1156 );
1157 break;
1158 case 3:
1159 ddr->ddr_sdram_mode_15 = (0
1160 | ((esdmode4 & 0xFFFF) << 16)
1161 | ((esdmode5 & 0xFFFF) << 0)
1162 );
1163 break;
1164 }
1165 }
1166 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1167 ddr->ddr_sdram_mode_11);
1168 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1169 ddr->ddr_sdram_mode_13);
1170 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1171 ddr->ddr_sdram_mode_15);
1172 }
1173}
1174
1175/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
03e664d8
YS		 1176static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1177 fsl_ddr_cfg_regs_t *ddr,
34e026f9
YS		 1178 const memctl_options_t *popts,
1179 const common_timing_params_t *common_dimm,
1180 const unsigned int unq_mrs_en)
1181{
1182 int i;
1183 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1184 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
03e664d8 1185 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
34e026f9
YS		 1186
1187 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1188
0fb71974
YS		 1189 if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1190 esdmode6 |= 1 << 6; /* Range 2 */
1191
34e026f9
YS		 1192 ddr->ddr_sdram_mode_10 = (0
1193 | ((esdmode6 & 0xffff) << 16)
1194 | ((esdmode7 & 0xffff) << 0)
1195 );
1196 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1197 if (unq_mrs_en) { /* unique mode registers are supported */
1198 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1199 switch (i) {
1200 case 1:
1201 ddr->ddr_sdram_mode_12 = (0
1202 | ((esdmode6 & 0xFFFF) << 16)
1203 | ((esdmode7 & 0xFFFF) << 0)
1204 );
1205 break;
1206 case 2:
1207 ddr->ddr_sdram_mode_14 = (0
1208 | ((esdmode6 & 0xFFFF) << 16)
1209 | ((esdmode7 & 0xFFFF) << 0)
1210 );
1211 break;
1212 case 3:
1213 ddr->ddr_sdram_mode_16 = (0
1214 | ((esdmode6 & 0xFFFF) << 16)
1215 | ((esdmode7 & 0xFFFF) << 0)
1216 );
1217 break;
1218 }
1219 }
1220 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1221 ddr->ddr_sdram_mode_12);
1222 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1223 ddr->ddr_sdram_mode_14);
1224 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1225 ddr->ddr_sdram_mode_16);
1226 }
58e5e9af
KG		 1227}
1228
34e026f9
YS		 1229#endif
1230
58e5e9af 1231/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
03e664d8
YS		 1232static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1233 fsl_ddr_cfg_regs_t *ddr,
1234 const memctl_options_t *popts,
1235 const common_timing_params_t *common_dimm)
58e5e9af
KG		 1236{
1237 unsigned int refint; /* Refresh interval */
1238 unsigned int bstopre; /* Precharge interval */
1239
03e664d8 1240 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
58e5e9af
KG		 1241
1242 bstopre = popts->bstopre;
1243
1244 /* refint field used 0x3FFF in earlier controllers */
1245 ddr->ddr_sdram_interval = (0
1246 | ((refint & 0xFFFF) << 16)
1247 | ((bstopre & 0x3FFF) << 0)
1248 );
1f293b41 1249 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
58e5e9af
KG		 1250}
1251
34e026f9 1252#ifdef CONFIG_SYS_FSL_DDR4
c360ceac 1253/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
03e664d8
YS		 1254static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1255 fsl_ddr_cfg_regs_t *ddr,
c360ceac
DL		 1256 const memctl_options_t *popts,
1257 const common_timing_params_t *common_dimm,
1258 unsigned int cas_latency,
e1fd16b6
YS		 1259 unsigned int additive_latency,
1260 const unsigned int unq_mrs_en)
c360ceac 1261{
34e026f9
YS		 1262 int i;
1263 unsigned short esdmode; /* Extended SDRAM mode */
1264 unsigned short sdmode; /* SDRAM mode */
1265
1266 /* Mode Register - MR1 */
1267 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1268 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1269 unsigned int rtt;
1270 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1271 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1272 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1273 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1274 0=Disable (Test/Debug) */
1275
1276 /* Mode Register - MR0 */
1277 unsigned int wr = 0; /* Write Recovery */
1278 unsigned int dll_rst; /* DLL Reset */
1279 unsigned int mode; /* Normal=0 or Test=1 */
1280 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1281 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1282 unsigned int bt;
1283 unsigned int bl; /* BL: Burst Length */
1284
1285 unsigned int wr_mclk;
1286 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1287 static const u8 wr_table[] = {
1288 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1289 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1290 static const u8 cas_latency_table[] = {
1291 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1292 9, 9, 10, 10, 11, 11};
1293
1294 if (popts->rtt_override)
1295 rtt = popts->rtt_override_value;
1296 else
1297 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1298
1299 if (additive_latency == (cas_latency - 1))
1300 al = 1;
1301 if (additive_latency == (cas_latency - 2))
1302 al = 2;
1303
1304 if (popts->quad_rank_present)
1305 dic = 1; /* output driver impedance 240/7 ohm */
1306
1307 /*
1308 * The esdmode value will also be used for writing
1309 * MR1 during write leveling for DDR3, although the
1310 * bits specifically related to the write leveling
1311 * scheme will be handled automatically by the DDR
1312 * controller. so we set the wrlvl_en = 0 here.
1313 */
1314 esdmode = (0
1315 | ((qoff & 0x1) << 12)
1316 | ((tdqs_en & 0x1) << 11)
1317 | ((rtt & 0x7) << 8)
1318 | ((wrlvl_en & 0x1) << 7)
1319 | ((al & 0x3) << 3)
1320 | ((dic & 0x3) << 1) /* DIC field is split */
1321 | ((dll_en & 0x1) << 0)
1322 );
1323
1324 /*
1325 * DLL control for precharge PD
1326 * 0=slow exit DLL off (tXPDLL)
1327 * 1=fast exit DLL on (tXP)
1328 */
1329
03e664d8 1330 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
34e026f9
YS		 1331 if (wr_mclk <= 24) {
1332 wr = wr_table[wr_mclk - 10];
1333 } else {
1334 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1335 wr_mclk);
1336 }
1337
1338 dll_rst = 0; /* dll no reset */
1339 mode = 0; /* normal mode */
1340
1341 /* look up table to get the cas latency bits */
1342 if (cas_latency >= 9 && cas_latency <= 24)
1343 caslat = cas_latency_table[cas_latency - 9];
1344 else
1345 printf("Error: unsupported cas latency for mode register\n");
1346
1347 bt = 0; /* Nibble sequential */
1348
1349 switch (popts->burst_length) {
1350 case DDR_BL8:
1351 bl = 0;
1352 break;
1353 case DDR_OTF:
1354 bl = 1;
1355 break;
1356 case DDR_BC4:
1357 bl = 2;
1358 break;
1359 default:
1360 printf("Error: invalid burst length of %u specified. ",
1361 popts->burst_length);
1362 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1363 bl = 1;
1364 break;
1365 }
1366
1367 sdmode = (0
1368 | ((wr & 0x7) << 9)
1369 | ((dll_rst & 0x1) << 8)
1370 | ((mode & 0x1) << 7)
1371 | (((caslat >> 1) & 0x7) << 4)
1372 | ((bt & 0x1) << 3)
1373 | ((caslat & 1) << 2)
1374 | ((bl & 0x3) << 0)
1375 );
1376
1377 ddr->ddr_sdram_mode = (0
1378 | ((esdmode & 0xFFFF) << 16)
1379 | ((sdmode & 0xFFFF) << 0)
1380 );
1381
1382 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1383
1384 if (unq_mrs_en) { /* unique mode registers are supported */
1385 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1386 if (popts->rtt_override)
1387 rtt = popts->rtt_override_value;
1388 else
1389 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1390
1391 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1392 esdmode |= (rtt & 0x7) << 8;
1393 switch (i) {
1394 case 1:
1395 ddr->ddr_sdram_mode_3 = (0
1396 | ((esdmode & 0xFFFF) << 16)
1397 | ((sdmode & 0xFFFF) << 0)
1398 );
1399 break;
1400 case 2:
1401 ddr->ddr_sdram_mode_5 = (0
1402 | ((esdmode & 0xFFFF) << 16)
1403 | ((sdmode & 0xFFFF) << 0)
1404 );
1405 break;
1406 case 3:
1407 ddr->ddr_sdram_mode_7 = (0
1408 | ((esdmode & 0xFFFF) << 16)
1409 | ((sdmode & 0xFFFF) << 0)
1410 );
1411 break;
1412 }
1413 }
1414 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1415 ddr->ddr_sdram_mode_3);
1416 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1417 ddr->ddr_sdram_mode_5);
1418 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1419 ddr->ddr_sdram_mode_5);
1420 }
1421}
1422
1423#elif defined(CONFIG_SYS_FSL_DDR3)
1424/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
03e664d8
YS		 1425static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1426 fsl_ddr_cfg_regs_t *ddr,
34e026f9
YS		 1427 const memctl_options_t *popts,
1428 const common_timing_params_t *common_dimm,
1429 unsigned int cas_latency,
1430 unsigned int additive_latency,
1431 const unsigned int unq_mrs_en)
1432{
1433 int i;
c360ceac
DL		 1434 unsigned short esdmode; /* Extended SDRAM mode */
1435 unsigned short sdmode; /* SDRAM mode */
1436
1437 /* Mode Register - MR1 */
1438 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1439 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1440 unsigned int rtt;
1441 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1442 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
e1fd16b6 1443 unsigned int dic = 0; /* Output driver impedance, 40ohm */
c360ceac
DL		 1444 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1445 1=Disable (Test/Debug) */
1446
1447 /* Mode Register - MR0 */
1448 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
fcea3068 1449 unsigned int wr = 0; /* Write Recovery */
c360ceac
DL		 1450 unsigned int dll_rst; /* DLL Reset */
1451 unsigned int mode; /* Normal=0 or Test=1 */
1452 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1453 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1454 unsigned int bt;
1455 unsigned int bl; /* BL: Burst Length */
1456
1457 unsigned int wr_mclk;
f5b6fb7c
YS		 1458 /*
1459 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1460 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1461 * for this table
1462 */
1463 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
c360ceac 1464
c360ceac
DL		 1465 if (popts->rtt_override)
1466 rtt = popts->rtt_override_value;
e1fd16b6
YS		 1467 else
1468 rtt = popts->cs_local_opts[0].odt_rtt_norm;
c360ceac
DL		 1469
1470 if (additive_latency == (cas_latency - 1))
1471 al = 1;
1472 if (additive_latency == (cas_latency - 2))
1473 al = 2;
1474
e1fd16b6
YS		 1475 if (popts->quad_rank_present)
1476 dic = 1; /* output driver impedance 240/7 ohm */
1477
c360ceac
DL		 1478 /*
1479 * The esdmode value will also be used for writing
1480 * MR1 during write leveling for DDR3, although the
1481 * bits specifically related to the write leveling
1482 * scheme will be handled automatically by the DDR
1483 * controller. so we set the wrlvl_en = 0 here.
1484 */
1485 esdmode = (0
1486 | ((qoff & 0x1) << 12)
1487 | ((tdqs_en & 0x1) << 11)
6d8565a1 1488 | ((rtt & 0x4) << 7) /* rtt field is split */
c360ceac 1489 | ((wrlvl_en & 0x1) << 7)
6d8565a1
KG		 1490 | ((rtt & 0x2) << 5) /* rtt field is split */
1491 | ((dic & 0x2) << 4) /* DIC field is split */
c360ceac 1492 | ((al & 0x3) << 3)
6d8565a1 1493 | ((rtt & 0x1) << 2) /* rtt field is split */
c360ceac
DL		 1494 | ((dic & 0x1) << 1) /* DIC field is split */
1495 | ((dll_en & 0x1) << 0)
1496 );
1497
1498 /*
1499 * DLL control for precharge PD
1500 * 0=slow exit DLL off (tXPDLL)
1501 * 1=fast exit DLL on (tXP)
1502 */
1503 dll_on = 1;
f5b6fb7c 1504
03e664d8 1505 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
fcea3068
YS		 1506 if (wr_mclk <= 16) {
1507 wr = wr_table[wr_mclk - 5];
1508 } else {
1509 printf("Error: unsupported write recovery for mode register "
1510 "wr_mclk = %d\n", wr_mclk);
1511 }
f5b6fb7c 1512
c360ceac
DL		 1513 dll_rst = 0; /* dll no reset */
1514 mode = 0; /* normal mode */
1515
1516 /* look up table to get the cas latency bits */
fcea3068
YS		 1517 if (cas_latency >= 5 && cas_latency <= 16) {
1518 unsigned char cas_latency_table[] = {
c360ceac
DL		 1519 0x2, /* 5 clocks */
1520 0x4, /* 6 clocks */
1521 0x6, /* 7 clocks */
1522 0x8, /* 8 clocks */
1523 0xa, /* 9 clocks */
1524 0xc, /* 10 clocks */
fcea3068
YS		 1525 0xe, /* 11 clocks */
1526 0x1, /* 12 clocks */
1527 0x3, /* 13 clocks */
1528 0x5, /* 14 clocks */
1529 0x7, /* 15 clocks */
1530 0x9, /* 16 clocks */
c360ceac
DL		 1531 };
1532 caslat = cas_latency_table[cas_latency - 5];
fcea3068
YS		 1533 } else {
1534 printf("Error: unsupported cas latency for mode register\n");
c360ceac 1535 }
fcea3068 1536
c360ceac
DL		 1537 bt = 0; /* Nibble sequential */
1538
1539 switch (popts->burst_length) {
1540 case DDR_BL8:
1541 bl = 0;
1542 break;
1543 case DDR_OTF:
1544 bl = 1;
1545 break;
1546 case DDR_BC4:
1547 bl = 2;
1548 break;
1549 default:
1550 printf("Error: invalid burst length of %u specified. "
1551 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1552 popts->burst_length);
1553 bl = 1;
1554 break;
1555 }
1556
1557 sdmode = (0
1558 | ((dll_on & 0x1) << 12)
1559 | ((wr & 0x7) << 9)
1560 | ((dll_rst & 0x1) << 8)
1561 | ((mode & 0x1) << 7)
1562 | (((caslat >> 1) & 0x7) << 4)
1563 | ((bt & 0x1) << 3)
fcea3068 1564 | ((caslat & 1) << 2)
c360ceac
DL		 1565 | ((bl & 0x3) << 0)
1566 );
1567
1568 ddr->ddr_sdram_mode = (0
1569 | ((esdmode & 0xFFFF) << 16)
1570 | ((sdmode & 0xFFFF) << 0)
1571 );
1572
1573 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
e1fd16b6
YS		 1574
1575 if (unq_mrs_en) { /* unique mode registers are supported */
dea7f887 1576 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
e1fd16b6
YS		 1577 if (popts->rtt_override)
1578 rtt = popts->rtt_override_value;
1579 else
1580 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1581
1582 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1583 esdmode |= (0
1584 | ((rtt & 0x4) << 7) /* rtt field is split */
1585 | ((rtt & 0x2) << 5) /* rtt field is split */
1586 | ((rtt & 0x1) << 2) /* rtt field is split */
1587 );
1588 switch (i) {
1589 case 1:
1590 ddr->ddr_sdram_mode_3 = (0
1591 | ((esdmode & 0xFFFF) << 16)
1592 | ((sdmode & 0xFFFF) << 0)
1593 );
1594 break;
1595 case 2:
1596 ddr->ddr_sdram_mode_5 = (0
1597 | ((esdmode & 0xFFFF) << 16)
1598 | ((sdmode & 0xFFFF) << 0)
1599 );
1600 break;
1601 case 3:
1602 ddr->ddr_sdram_mode_7 = (0
1603 | ((esdmode & 0xFFFF) << 16)
1604 | ((sdmode & 0xFFFF) << 0)
1605 );
1606 break;
1607 }
1608 }
1609 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1610 ddr->ddr_sdram_mode_3);
1611 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1612 ddr->ddr_sdram_mode_5);
1613 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1614 ddr->ddr_sdram_mode_5);
1615 }
c360ceac
DL		 1616}
1617
5614e71b 1618#else /* !CONFIG_SYS_FSL_DDR3 */
c360ceac 1619
58e5e9af 1620/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
03e664d8
YS		 1621static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1622 fsl_ddr_cfg_regs_t *ddr,
58e5e9af
KG		 1623 const memctl_options_t *popts,
1624 const common_timing_params_t *common_dimm,
1625 unsigned int cas_latency,
e1fd16b6
YS		 1626 unsigned int additive_latency,
1627 const unsigned int unq_mrs_en)
58e5e9af
KG		 1628{
1629 unsigned short esdmode; /* Extended SDRAM mode */
1630 unsigned short sdmode; /* SDRAM mode */
1631
1632 /*
1633 * FIXME: This ought to be pre-calculated in a
1634 * technology-specific routine,
1635 * e.g. compute_DDR2_mode_register(), and then the
1636 * sdmode and esdmode passed in as part of common_dimm.
1637 */
1638
1639 /* Extended Mode Register */
1640 unsigned int mrs = 0; /* Mode Register Set */
1641 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1642 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1643 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1644 unsigned int ocd = 0; /* 0x0=OCD not supported,
1645 0x7=OCD default state */
1646 unsigned int rtt;
1647 unsigned int al; /* Posted CAS# additive latency (AL) */
1648 unsigned int ods = 0; /* Output Drive Strength:
1649 0 = Full strength (18ohm)
1650 1 = Reduced strength (4ohm) */
1651 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1652 1=Disable (Test/Debug) */
1653
1654 /* Mode Register (MR) */
1655 unsigned int mr; /* Mode Register Definition */
1656 unsigned int pd; /* Power-Down Mode */
1657 unsigned int wr; /* Write Recovery */
1658 unsigned int dll_res; /* DLL Reset */
1659 unsigned int mode; /* Normal=0 or Test=1 */
302e52e0 1660 unsigned int caslat = 0;/* CAS# latency */
58e5e9af
KG		 1661 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1662 unsigned int bt;
1663 unsigned int bl; /* BL: Burst Length */
1664
0dd38a35 1665 dqs_en = !popts->dqs_config;
58e5e9af
KG		 1666 rtt = fsl_ddr_get_rtt();
1667
1668 al = additive_latency;
1669
1670 esdmode = (0
1671 | ((mrs & 0x3) << 14)
1672 | ((outputs & 0x1) << 12)
1673 | ((rdqs_en & 0x1) << 11)
1674 | ((dqs_en & 0x1) << 10)
1675 | ((ocd & 0x7) << 7)
1676 | ((rtt & 0x2) << 5) /* rtt field is split */
1677 | ((al & 0x7) << 3)
1678 | ((rtt & 0x1) << 2) /* rtt field is split */
1679 | ((ods & 0x1) << 1)
1680 | ((dll_en & 0x1) << 0)
1681 );
1682
1683 mr = 0; /* FIXME: CHECKME */
1684
1685 /*
1686 * 0 = Fast Exit (Normal)
1687 * 1 = Slow Exit (Low Power)
1688 */
1689 pd = 0;
1690
5614e71b 1691#if defined(CONFIG_SYS_FSL_DDR1)
58e5e9af 1692 wr = 0; /* Historical */
5614e71b 1693#elif defined(CONFIG_SYS_FSL_DDR2)
03e664d8 1694 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
58e5e9af
KG		 1695#endif
1696 dll_res = 0;
1697 mode = 0;
1698
5614e71b 1699#if defined(CONFIG_SYS_FSL_DDR1)
58e5e9af
KG		 1700 if (1 <= cas_latency && cas_latency <= 4) {
1701 unsigned char mode_caslat_table[4] = {
1702 0x5, /* 1.5 clocks */
1703 0x2, /* 2.0 clocks */
1704 0x6, /* 2.5 clocks */
1705 0x3 /* 3.0 clocks */
1706 };
302e52e0
KG		 1707 caslat = mode_caslat_table[cas_latency - 1];
1708 } else {
1709 printf("Warning: unknown cas_latency %d\n", cas_latency);
58e5e9af 1710 }
5614e71b 1711#elif defined(CONFIG_SYS_FSL_DDR2)
58e5e9af 1712 caslat = cas_latency;
58e5e9af
KG		 1713#endif
1714 bt = 0;
1715
1716 switch (popts->burst_length) {
c360ceac 1717 case DDR_BL4:
58e5e9af
KG		 1718 bl = 2;
1719 break;
c360ceac 1720 case DDR_BL8:
58e5e9af
KG		 1721 bl = 3;
1722 break;
1723 default:
1724 printf("Error: invalid burst length of %u specified. "
1725 " Defaulting to 4 beats.\n",
1726 popts->burst_length);
1727 bl = 2;
1728 break;
1729 }
1730
1731 sdmode = (0
1732 | ((mr & 0x3) << 14)
1733 | ((pd & 0x1) << 12)
1734 | ((wr & 0x7) << 9)
1735 | ((dll_res & 0x1) << 8)
1736 | ((mode & 0x1) << 7)
1737 | ((caslat & 0x7) << 4)
1738 | ((bt & 0x1) << 3)
1739 | ((bl & 0x7) << 0)
1740 );
1741
1742 ddr->ddr_sdram_mode = (0
1743 | ((esdmode & 0xFFFF) << 16)
1744 | ((sdmode & 0xFFFF) << 0)
1745 );
1f293b41 1746 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
58e5e9af 1747}
c360ceac 1748#endif
58e5e9af
KG		 1749
1750/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1751static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1752{
1753 unsigned int init_value; /* Initialization value */
1754
5b933943
AG		 1755#ifdef CONFIG_MEM_INIT_VALUE
1756 init_value = CONFIG_MEM_INIT_VALUE;
1757#else
58e5e9af 1758 init_value = 0xDEADBEEF;
5b933943 1759#endif
58e5e9af
KG		 1760 ddr->ddr_data_init = init_value;
1761}
1762
1763/*
1764 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1765 * The old controller on the 8540/60 doesn't have this register.
1766 * Hope it's OK to set it (to 0) anyway.
1767 */
1768static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1769 const memctl_options_t *popts)
1770{
1771 unsigned int clk_adjust; /* Clock adjust */
d7c865bd 1772 unsigned int ss_en = 0; /* Source synchronous enable */
58e5e9af 1773
d7c865bd
CB		 1774#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
1775 /* Per FSL Application Note: AN2805 */
1776 ss_en = 1;
1777#endif
58e5e9af 1778 clk_adjust = popts->clk_adjust;
d7c865bd
CB		 1779 ddr->ddr_sdram_clk_cntl = (0
1780 | ((ss_en & 0x1) << 31)
1781 | ((clk_adjust & 0xF) << 23)
1782 );
9490ff48 1783 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
58e5e9af
KG		 1784}
1785
1786/* DDR Initialization Address (DDR_INIT_ADDR) */
1787static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1788{
1789 unsigned int init_addr = 0; /* Initialization address */
1790
1791 ddr->ddr_init_addr = init_addr;
1792}
1793
1794/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1795static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1796{
1797 unsigned int uia = 0; /* Use initialization address */
1798 unsigned int init_ext_addr = 0; /* Initialization address */
1799
1800 ddr->ddr_init_ext_addr = (0
1801 | ((uia & 0x1) << 31)
1802 | (init_ext_addr & 0xF)
1803 );
1804}
1805
1806/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
ec145e87
DL		 1807static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1808 const memctl_options_t *popts)
58e5e9af
KG		 1809{
1810 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1811 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1812 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1813 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1814 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1815
34e026f9 1816#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
ec145e87
DL		 1817 if (popts->burst_length == DDR_BL8) {
1818 /* We set BL/2 for fixed BL8 */
1819 rrt = 0; /* BL/2 clocks */
1820 wwt = 0; /* BL/2 clocks */
1821 } else {
1822 /* We need to set BL/2 + 2 to BC4 and OTF */
1823 rrt = 2; /* BL/2 + 2 clocks */
1824 wwt = 2; /* BL/2 + 2 clocks */
1825 }
34e026f9
YS		 1826#endif
1827
1828#ifdef CONFIG_SYS_FSL_DDR4
1829 dll_lock = 2; /* tDLLK = 1024 clocks */
1830#elif defined(CONFIG_SYS_FSL_DDR3)
c360ceac
DL		 1831 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1832#endif
58e5e9af
KG		 1833 ddr->timing_cfg_4 = (0
1834 | ((rwt & 0xf) << 28)
1835 | ((wrt & 0xf) << 24)
1836 | ((rrt & 0xf) << 20)
1837 | ((wwt & 0xf) << 16)
1838 | (dll_lock & 0x3)
1839 );
1f293b41 1840 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
58e5e9af
KG		 1841}
1842
1843/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
e1fd16b6 1844static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
58e5e9af
KG		 1845{
1846 unsigned int rodt_on = 0; /* Read to ODT on */
1847 unsigned int rodt_off = 0; /* Read to ODT off */
1848 unsigned int wodt_on = 0; /* Write to ODT on */
1849 unsigned int wodt_off = 0; /* Write to ODT off */
1850
34e026f9
YS		 1851#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1852 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1853 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
e1fd16b6 1854 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
34e026f9
YS		 1855 if (cas_latency >= wr_lat)
1856 rodt_on = cas_latency - wr_lat + 1;
c360ceac 1857 rodt_off = 4; /* 4 clocks */
5fb8a8a7 1858 wodt_on = 1; /* 1 clocks */
c360ceac
DL		 1859 wodt_off = 4; /* 4 clocks */
1860#endif
1861
58e5e9af 1862 ddr->timing_cfg_5 = (0
22ff3d01
DL		 1863 | ((rodt_on & 0x1f) << 24)
1864 | ((rodt_off & 0x7) << 20)
1865 | ((wodt_on & 0x1f) << 12)
1866 | ((wodt_off & 0x7) << 8)
58e5e9af 1867 );
1f293b41 1868 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
58e5e9af
KG		 1869}
1870
34e026f9
YS		 1871#ifdef CONFIG_SYS_FSL_DDR4
1872static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1873{
1874 unsigned int hs_caslat = 0;
1875 unsigned int hs_wrlat = 0;
1876 unsigned int hs_wrrec = 0;
1877 unsigned int hs_clkadj = 0;
1878 unsigned int hs_wrlvl_start = 0;
1879
1880 ddr->timing_cfg_6 = (0
1881 | ((hs_caslat & 0x1f) << 24)
1882 | ((hs_wrlat & 0x1f) << 19)
1883 | ((hs_wrrec & 0x1f) << 12)
1884 | ((hs_clkadj & 0x1f) << 6)
1885 | ((hs_wrlvl_start & 0x1f) << 0)
1886 );
1887 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1888}
1889
03e664d8
YS		 1890static void set_timing_cfg_7(const unsigned int ctrl_num,
1891 fsl_ddr_cfg_regs_t *ddr,
1892 const common_timing_params_t *common_dimm)
34e026f9
YS		 1893{
1894 unsigned int txpr, tcksre, tcksrx;
1895 unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1896
03e664d8
YS		 1897 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1898 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1899 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
34e026f9
YS		 1900 par_lat = 0;
1901 cs_to_cmd = 0;
1902
1903 if (txpr <= 200)
1904 cke_rst = 0;
1905 else if (txpr <= 256)
1906 cke_rst = 1;
1907 else if (txpr <= 512)
1908 cke_rst = 2;
1909 else
1910 cke_rst = 3;
1911
1912 if (tcksre <= 19)
1913 cksre = tcksre - 5;
1914 else
1915 cksre = 15;
1916
1917 if (tcksrx <= 19)
1918 cksrx = tcksrx - 5;
1919 else
1920 cksrx = 15;
1921
1922 ddr->timing_cfg_7 = (0
1923 | ((cke_rst & 0x3) << 28)
1924 | ((cksre & 0xf) << 24)
1925 | ((cksrx & 0xf) << 20)
1926 | ((par_lat & 0xf) << 16)
1927 | ((cs_to_cmd & 0xf) << 4)
1928 );
1929 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1930}
1931
03e664d8
YS		 1932static void set_timing_cfg_8(const unsigned int ctrl_num,
1933 fsl_ddr_cfg_regs_t *ddr,
34e026f9
YS		 1934 const memctl_options_t *popts,
1935 const common_timing_params_t *common_dimm,
1936 unsigned int cas_latency)
1937{
1938 unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1939 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
03e664d8 1940 unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
34e026f9
YS		 1941 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1942 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1943
1944 rwt_bg = cas_latency + 2 + 4 - wr_lat;
1945 if (rwt_bg < tccdl)
1946 rwt_bg = tccdl - rwt_bg;
1947 else
1948 rwt_bg = 0;
1949
1950 wrt_bg = wr_lat + 4 + 1 - cas_latency;
1951 if (wrt_bg < tccdl)
1952 wrt_bg = tccdl - wrt_bg;
1953 else
1954 wrt_bg = 0;
1955
1956 if (popts->burst_length == DDR_BL8) {
1957 rrt_bg = tccdl - 4;
1958 wwt_bg = tccdl - 4;
1959 } else {
1960 rrt_bg = tccdl - 2;
dc1437af 1961 wwt_bg = tccdl - 2;
34e026f9
YS		 1962 }
1963
03e664d8
YS		 1964 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
1965 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
3d75ec95
YS		 1966 if (popts->otf_burst_chop_en)
1967 wrtord_bg += 2;
1968
34e026f9
YS		 1969 pre_all_rec = 0;
1970
1971 ddr->timing_cfg_8 = (0
1972 | ((rwt_bg & 0xf) << 28)
1973 | ((wrt_bg & 0xf) << 24)
1974 | ((rrt_bg & 0xf) << 20)
1975 | ((wwt_bg & 0xf) << 16)
1976 | ((acttoact_bg & 0xf) << 12)
1977 | ((wrtord_bg & 0xf) << 8)
1978 | ((pre_all_rec & 0x1f) << 0)
1979 );
1980
1981 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1982}
1983
1984static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1985{
1986 ddr->timing_cfg_9 = 0;
1987 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1988}
1989
f80d6472 1990/* This function needs to be called after set_ddr_sdram_cfg() is called */
34e026f9
YS		 1991static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1992 const dimm_params_t *dimm_params)
1993{
f80d6472 1994 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
6b95be22
YS		 1995 int i;
1996
1997 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
1998 if (dimm_params[i].n_ranks)
1999 break;
2000 }
2001 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2002 puts("DDR error: no DIMM found!\n");
2003 return;
2004 }
f80d6472 2005
6b95be22
YS		 2006 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2007 ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2008 ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2009 ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2010 ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
34e026f9 2011
6b95be22
YS		 2012 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2013 ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2014 ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2015 ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2016 ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
34e026f9 2017
6b95be22
YS		 2018 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2019 ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2020 ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2021 ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2022 ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
34e026f9 2023
f80d6472 2024 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
6b95be22
YS		 2025 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2026 ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
f80d6472 2027 (acc_ecc_en ? 0 :
6b95be22
YS		 2028 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2029 dimm_params[i].dq_mapping_ors;
34e026f9
YS		 2030
2031 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2032 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2033 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2034 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2035}
2036static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2037 const memctl_options_t *popts)
2038{
2039 int rd_pre;
2040
2041 rd_pre = popts->quad_rank_present ? 1 : 0;
2042
2043 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2044
2045 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2046}
2047#endif /* CONFIG_SYS_FSL_DDR4 */
2048
58e5e9af 2049/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
c360ceac 2050static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
58e5e9af 2051{
58e5e9af
KG		 2052 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2053 /* Normal Operation Full Calibration Time (tZQoper) */
2054 unsigned int zqoper = 0;
2055 /* Normal Operation Short Calibration Time (tZQCS) */
2056 unsigned int zqcs = 0;
34e026f9
YS		 2057#ifdef CONFIG_SYS_FSL_DDR4
2058 unsigned int zqcs_init;
2059#endif
58e5e9af 2060
c360ceac 2061 if (zq_en) {
34e026f9
YS		 2062#ifdef CONFIG_SYS_FSL_DDR4
2063 zqinit = 10; /* 1024 clocks */
2064 zqoper = 9; /* 512 clocks */
2065 zqcs = 7; /* 128 clocks */
2066 zqcs_init = 5; /* 1024 refresh sequences */
2067#else
c360ceac
DL		 2068 zqinit = 9; /* 512 clocks */
2069 zqoper = 8; /* 256 clocks */
2070 zqcs = 6; /* 64 clocks */
34e026f9 2071#endif
c360ceac
DL		 2072 }
2073
58e5e9af
KG		 2074 ddr->ddr_zq_cntl = (0
2075 | ((zq_en & 0x1) << 31)
2076 | ((zqinit & 0xF) << 24)
2077 | ((zqoper & 0xF) << 16)
2078 | ((zqcs & 0xF) << 8)
34e026f9
YS		 2079#ifdef CONFIG_SYS_FSL_DDR4
2080 | ((zqcs_init & 0xF) << 0)
2081#endif
58e5e9af 2082 );
e1fd16b6 2083 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
58e5e9af
KG		 2084}
2085
2086/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
bdc9f7b5
DL		 2087static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2088 const memctl_options_t *popts)
58e5e9af 2089{
58e5e9af
KG		 2090 /*
2091 * First DQS pulse rising edge after margining mode
2092 * is programmed (tWL_MRD)
2093 */
2094 unsigned int wrlvl_mrd = 0;
2095 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2096 unsigned int wrlvl_odten = 0;
2097 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2098 unsigned int wrlvl_dqsen = 0;
2099 /* WRLVL_SMPL: Write leveling sample time */
2100 unsigned int wrlvl_smpl = 0;
2101 /* WRLVL_WLR: Write leveling repeition time */
2102 unsigned int wrlvl_wlr = 0;
2103 /* WRLVL_START: Write leveling start time */
2104 unsigned int wrlvl_start = 0;
2105
c360ceac
DL		 2106 /* suggest enable write leveling for DDR3 due to fly-by topology */
2107 if (wrlvl_en) {
2108 /* tWL_MRD min = 40 nCK, we set it 64 */
2109 wrlvl_mrd = 0x6;
2110 /* tWL_ODTEN 128 */
2111 wrlvl_odten = 0x7;
2112 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2113 wrlvl_dqsen = 0x5;
2114 /*
bdc9f7b5
DL		 2115 * Write leveling sample time at least need 6 clocks
2116 * higher than tWLO to allow enough time for progagation
2117 * delay and sampling the prime data bits.
c360ceac
DL		 2118 */
2119 wrlvl_smpl = 0xf;
2120 /*
2121 * Write leveling repetition time
2122 * at least tWLO + 6 clocks clocks
5fb8a8a7 2123 * we set it 64
c360ceac 2124 */
5fb8a8a7 2125 wrlvl_wlr = 0x6;
c360ceac
DL		 2126 /*
2127 * Write leveling start time
2128 * The value use for the DQS_ADJUST for the first sample
e1fd16b6
YS		 2129 * when write leveling is enabled. It probably needs to be
2130 * overriden per platform.
c360ceac
DL		 2131 */
2132 wrlvl_start = 0x8;
bdc9f7b5
DL		 2133 /*
2134 * Override the write leveling sample and start time
2135 * according to specific board
2136 */
2137 if (popts->wrlvl_override) {
2138 wrlvl_smpl = popts->wrlvl_sample;
2139 wrlvl_start = popts->wrlvl_start;
2140 }
c360ceac
DL		 2141 }
2142
58e5e9af
KG		 2143 ddr->ddr_wrlvl_cntl = (0
2144 | ((wrlvl_en & 0x1) << 31)
2145 | ((wrlvl_mrd & 0x7) << 24)
2146 | ((wrlvl_odten & 0x7) << 20)
2147 | ((wrlvl_dqsen & 0x7) << 16)
2148 | ((wrlvl_smpl & 0xf) << 12)
2149 | ((wrlvl_wlr & 0x7) << 8)
22ff3d01 2150 | ((wrlvl_start & 0x1F) << 0)
58e5e9af 2151 );
e1fd16b6 2152 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
57495e4e
YS		 2153 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2154 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2155 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2156 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2157
58e5e9af
KG		 2158}
2159
2160/* DDR Self Refresh Counter (DDR_SR_CNTR) */
22cca7e1 2161static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
58e5e9af 2162{
22cca7e1 2163 /* Self Refresh Idle Threshold */
58e5e9af
KG		 2164 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2165}
2166
7fd101c9
YS		 2167static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2168{
2169 if (popts->addr_hash) {
2170 ddr->ddr_eor = 0x40000000; /* address hash enable */
c2a63f48 2171 puts("Address hashing enabled.\n");
7fd101c9
YS		 2172 }
2173}
2174
e1fd16b6
YS		 2175static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2176{
2177 ddr->ddr_cdr1 = popts->ddr_cdr1;
2178 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2179}
2180
57495e4e
YS		 2181static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2182{
2183 ddr->ddr_cdr2 = popts->ddr_cdr2;
2184 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2185}
2186
58e5e9af
KG		 2187unsigned int
2188check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2189{
2190 unsigned int res = 0;
2191
2192 /*
2193 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2194 * not set at the same time.
2195 */
2196 if (ddr->ddr_sdram_cfg & 0x10000000
2197 && ddr->ddr_sdram_cfg & 0x00008000) {
2198 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2199 " should not be set at the same time.\n");
2200 res++;
2201 }
2202
2203 return res;
2204}
2205
2206unsigned int
03e664d8
YS		 2207compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2208 const memctl_options_t *popts,
58e5e9af
KG		 2209 fsl_ddr_cfg_regs_t *ddr,
2210 const common_timing_params_t *common_dimm,
2211 const dimm_params_t *dimm_params,
fc0c2b6f
HW		 2212 unsigned int dbw_cap_adj,
2213 unsigned int size_only)
58e5e9af
KG		 2214{
2215 unsigned int i;
2216 unsigned int cas_latency;
2217 unsigned int additive_latency;
22cca7e1 2218 unsigned int sr_it;
c360ceac
DL		 2219 unsigned int zq_en;
2220 unsigned int wrlvl_en;
e1fd16b6
YS		 2221 unsigned int ip_rev = 0;
2222 unsigned int unq_mrs_en = 0;
58edbc9c 2223 int cs_en = 1;
58e5e9af
KG		 2224
2225 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2226
2227 if (common_dimm == NULL) {
2228 printf("Error: subset DIMM params struct null pointer\n");
2229 return 1;
2230 }
2231
2232 /*
2233 * Process overrides first.
2234 *
2235 * FIXME: somehow add dereated caslat to this
2236 */
2237 cas_latency = (popts->cas_latency_override)
2238 ? popts->cas_latency_override_value
34e026f9 2239 : common_dimm->lowest_common_spd_caslat;
58e5e9af
KG		 2240
2241 additive_latency = (popts->additive_latency_override)
2242 ? popts->additive_latency_override_value
2243 : common_dimm->additive_latency;
2244
22cca7e1
DL		 2245 sr_it = (popts->auto_self_refresh_en)
2246 ? popts->sr_it
2247 : 0;
c360ceac
DL		 2248 /* ZQ calibration */
2249 zq_en = (popts->zq_en) ? 1 : 0;
2250 /* write leveling */
2251 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
22cca7e1 2252
58e5e9af
KG		 2253 /* Chip Select Memory Bounds (CSn_BNDS) */
2254 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
a4c66509 2255 unsigned long long ea, sa;
076bff8f
YS		 2256 unsigned int cs_per_dimm
2257 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2258 unsigned int dimm_number
2259 = i / cs_per_dimm;
2260 unsigned long long rank_density
a4c66509 2261 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
076bff8f 2262
076bff8f 2263 if (dimm_params[dimm_number].n_ranks == 0) {
58e5e9af 2264 debug("Skipping setup of CS%u "
5800e7ab 2265 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
58e5e9af
KG		 2266 continue;
2267 }
a4c66509 2268 if (popts->memctl_interleaving) {
076bff8f 2269 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
a4c66509
YS		 2270 case FSL_DDR_CS0_CS1_CS2_CS3:
2271 break;
076bff8f
YS		 2272 case FSL_DDR_CS0_CS1:
2273 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
58edbc9c
YS		 2274 if (i > 1)
2275 cs_en = 0;
076bff8f
YS		 2276 break;
2277 case FSL_DDR_CS2_CS3:
a4c66509 2278 default:
58edbc9c
YS		 2279 if (i > 0)
2280 cs_en = 0;
076bff8f 2281 break;
076bff8f 2282 }
a4c66509 2283 sa = common_dimm->base_address;
123922b1 2284 ea = sa + common_dimm->total_mem - 1;
a4c66509 2285 } else if (!popts->memctl_interleaving) {
58e5e9af
KG		 2286 /*
2287 * If memory interleaving between controllers is NOT
2288 * enabled, the starting address for each memory
2289 * controller is distinct. However, because rank
2290 * interleaving is enabled, the starting and ending
2291 * addresses of the total memory on that memory
2292 * controller needs to be programmed into its
2293 * respective CS0_BNDS.
2294 */
dbbbb3ab
HW		 2295 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2296 case FSL_DDR_CS0_CS1_CS2_CS3:
dbbbb3ab 2297 sa = common_dimm->base_address;
123922b1 2298 ea = sa + common_dimm->total_mem - 1;
dbbbb3ab
HW		 2299 break;
2300 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
a4c66509 2301 if ((i >= 2) && (dimm_number == 0)) {
076bff8f 2302 sa = dimm_params[dimm_number].base_address +
a4c66509
YS		 2303 2 * rank_density;
2304 ea = sa + 2 * rank_density - 1;
076bff8f
YS		 2305 } else {
2306 sa = dimm_params[dimm_number].base_address;
a4c66509 2307 ea = sa + 2 * rank_density - 1;
dbbbb3ab
HW		 2308 }
2309 break;
2310 case FSL_DDR_CS0_CS1:
076bff8f
YS		 2311 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2312 sa = dimm_params[dimm_number].base_address;
a4c66509
YS		 2313 ea = sa + rank_density - 1;
2314 if (i != 1)
2315 sa += (i % cs_per_dimm) * rank_density;
2316 ea += (i % cs_per_dimm) * rank_density;
076bff8f
YS		 2317 } else {
2318 sa = 0;
2319 ea = 0;
2320 }
2321 if (i == 0)
a4c66509 2322 ea += rank_density;
dbbbb3ab
HW		 2323 break;
2324 case FSL_DDR_CS2_CS3:
076bff8f
YS		 2325 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2326 sa = dimm_params[dimm_number].base_address;
a4c66509
YS		 2327 ea = sa + rank_density - 1;
2328 if (i != 3)
2329 sa += (i % cs_per_dimm) * rank_density;
2330 ea += (i % cs_per_dimm) * rank_density;
076bff8f
YS		 2331 } else {
2332 sa = 0;
2333 ea = 0;
dbbbb3ab 2334 }
076bff8f
YS		 2335 if (i == 2)
2336 ea += (rank_density >> dbw_cap_adj);
dbbbb3ab
HW		 2337 break;
2338 default: /* No bank(chip-select) interleaving */
a4c66509
YS		 2339 sa = dimm_params[dimm_number].base_address;
2340 ea = sa + rank_density - 1;
2341 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2342 sa += (i % cs_per_dimm) * rank_density;
2343 ea += (i % cs_per_dimm) * rank_density;
2344 } else {
2345 sa = 0;
2346 ea = 0;
2347 }
dbbbb3ab
HW		 2348 break;
2349 }
58e5e9af 2350 }
58e5e9af
KG		 2351
2352 sa >>= 24;
2353 ea >>= 24;
2354
123922b1
YS		 2355 if (cs_en) {
2356 ddr->cs[i].bnds = (0
d4263b8a
YS		 2357 | ((sa & 0xffff) << 16) /* starting address */
2358 | ((ea & 0xffff) << 0) /* ending address */
123922b1
YS		 2359 );
2360 } else {
d8556db1
YS		 2361 /* setting bnds to 0xffffffff for inactive CS */
2362 ddr->cs[i].bnds = 0xffffffff;
123922b1 2363 }
58e5e9af 2364
1f293b41 2365 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
123922b1
YS		 2366 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2367 set_csn_config_2(i, ddr);
58e5e9af
KG		 2368 }
2369
fc0c2b6f
HW		 2370 /*
2371 * In the case we only need to compute the ddr sdram size, we only need
2372 * to set csn registers, so return from here.
2373 */
2374 if (size_only)
2375 return 0;
2376
7fd101c9
YS		 2377 set_ddr_eor(ddr, popts);
2378
5614e71b 2379#if !defined(CONFIG_SYS_FSL_DDR1)
03e664d8 2380 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
58e5e9af
KG		 2381#endif
2382
03e664d8 2383 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
d4263b8a 2384 additive_latency);
03e664d8
YS		 2385 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2386 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2387 cas_latency, additive_latency);
58e5e9af 2388
e1fd16b6 2389 set_ddr_cdr1(ddr, popts);
57495e4e 2390 set_ddr_cdr2(ddr, popts);
58e5e9af 2391 set_ddr_sdram_cfg(ddr, popts, common_dimm);
66869f95 2392 ip_rev = fsl_ddr_get_version(ctrl_num);
e1fd16b6
YS		 2393 if (ip_rev > 0x40400)
2394 unq_mrs_en = 1;
58e5e9af 2395
f80d6472 2396 if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
ef87cab6
YS		 2397 ddr->debug[18] = popts->cswl_override;
2398
03e664d8
YS		 2399 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2400 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2401 cas_latency, additive_latency, unq_mrs_en);
2402 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
34e026f9
YS		 2403#ifdef CONFIG_SYS_FSL_DDR4
2404 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
03e664d8 2405 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
34e026f9 2406#endif
03e664d8 2407 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
58e5e9af
KG		 2408 set_ddr_data_init(ddr);
2409 set_ddr_sdram_clk_cntl(ddr, popts);
2410 set_ddr_init_addr(ddr);
2411 set_ddr_init_ext_addr(ddr);
ec145e87 2412 set_timing_cfg_4(ddr, popts);
e1fd16b6 2413 set_timing_cfg_5(ddr, cas_latency);
34e026f9
YS		 2414#ifdef CONFIG_SYS_FSL_DDR4
2415 set_ddr_sdram_cfg_3(ddr, popts);
2416 set_timing_cfg_6(ddr);
03e664d8
YS		 2417 set_timing_cfg_7(ctrl_num, ddr, common_dimm);
2418 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
34e026f9
YS		 2419 set_timing_cfg_9(ddr);
2420 set_ddr_dq_mapping(ddr, dimm_params);
2421#endif
58e5e9af 2422
c360ceac 2423 set_ddr_zq_cntl(ddr, zq_en);
bdc9f7b5 2424 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
58e5e9af 2425
22cca7e1 2426 set_ddr_sr_cntr(ddr, sr_it);
58e5e9af 2427
e1fd16b6 2428 set_ddr_sdram_rcw(ddr, popts, common_dimm);
58e5e9af 2429
cb93071b
YS		 2430#ifdef CONFIG_SYS_FSL_DDR_EMU
2431 /* disble DDR training for emulator */
2432 ddr->debug[2] = 0x00000400;
1f3402e7
YS		 2433 ddr->debug[4] = 0xff800800;
2434 ddr->debug[5] = 0x08000800;
2435 ddr->debug[6] = 0x08000800;
2436 ddr->debug[7] = 0x08000800;
2437 ddr->debug[8] = 0x08000800;
cb93071b 2438#endif
9855b3be
YS		 2439#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2440 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2441 ddr->debug[2] |= 0x00000200; /* set bit 22 */
2442#endif
2443
58e5e9af
KG		 2444 return check_fsl_memctl_config_regs(ddr);
2445}
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